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1331 lines
35 KiB
1331 lines
35 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* |
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* Implementation of primary alsa driver code base for Intel HD Audio. |
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* |
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* Copyright(c) 2004 Intel Corporation. All rights reserved. |
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* |
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* Copyright (c) 2004 Takashi Iwai <[email protected]> |
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* PeiSen Hou <[email protected]> |
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*/ |
|
|
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#include <linux/clocksource.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/slab.h> |
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|
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#ifdef CONFIG_X86 |
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/* for art-tsc conversion */ |
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#include <asm/tsc.h> |
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#endif |
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|
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#include <sound/core.h> |
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#include <sound/initval.h> |
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#include "hda_controller.h" |
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|
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#define CREATE_TRACE_POINTS |
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#include "hda_controller_trace.h" |
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|
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/* DSP lock helpers */ |
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#define dsp_lock(dev) snd_hdac_dsp_lock(azx_stream(dev)) |
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#define dsp_unlock(dev) snd_hdac_dsp_unlock(azx_stream(dev)) |
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#define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev)) |
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|
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/* assign a stream for the PCM */ |
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static inline struct azx_dev * |
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azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) |
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{ |
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struct hdac_stream *s; |
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|
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s = snd_hdac_stream_assign(azx_bus(chip), substream); |
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if (!s) |
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return NULL; |
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return stream_to_azx_dev(s); |
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} |
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|
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/* release the assigned stream */ |
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static inline void azx_release_device(struct azx_dev *azx_dev) |
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{ |
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snd_hdac_stream_release(azx_stream(azx_dev)); |
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} |
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|
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static inline struct hda_pcm_stream * |
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to_hda_pcm_stream(struct snd_pcm_substream *substream) |
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{ |
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
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return &apcm->info->stream[substream->stream]; |
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} |
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|
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static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream, |
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u64 nsec) |
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{ |
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
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struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
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u64 codec_frames, codec_nsecs; |
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|
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if (!hinfo->ops.get_delay) |
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return nsec; |
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|
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codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); |
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codec_nsecs = div_u64(codec_frames * 1000000000LL, |
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substream->runtime->rate); |
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|
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
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return nsec + codec_nsecs; |
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|
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return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; |
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} |
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|
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/* |
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* PCM ops |
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*/ |
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|
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static int azx_pcm_close(struct snd_pcm_substream *substream) |
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{ |
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
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struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
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struct azx *chip = apcm->chip; |
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struct azx_dev *azx_dev = get_azx_dev(substream); |
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|
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trace_azx_pcm_close(chip, azx_dev); |
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mutex_lock(&chip->open_mutex); |
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azx_release_device(azx_dev); |
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if (hinfo->ops.close) |
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hinfo->ops.close(hinfo, apcm->codec, substream); |
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snd_hda_power_down(apcm->codec); |
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mutex_unlock(&chip->open_mutex); |
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snd_hda_codec_pcm_put(apcm->info); |
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return 0; |
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} |
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|
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static int azx_pcm_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *hw_params) |
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{ |
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
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struct azx *chip = apcm->chip; |
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struct azx_dev *azx_dev = get_azx_dev(substream); |
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int ret = 0; |
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|
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trace_azx_pcm_hw_params(chip, azx_dev); |
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dsp_lock(azx_dev); |
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if (dsp_is_locked(azx_dev)) { |
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ret = -EBUSY; |
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goto unlock; |
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} |
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|
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azx_dev->core.bufsize = 0; |
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azx_dev->core.period_bytes = 0; |
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azx_dev->core.format_val = 0; |
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|
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unlock: |
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dsp_unlock(azx_dev); |
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return ret; |
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} |
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|
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static int azx_pcm_hw_free(struct snd_pcm_substream *substream) |
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{ |
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
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struct azx_dev *azx_dev = get_azx_dev(substream); |
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struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
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|
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/* reset BDL address */ |
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dsp_lock(azx_dev); |
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if (!dsp_is_locked(azx_dev)) |
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snd_hdac_stream_cleanup(azx_stream(azx_dev)); |
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|
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snd_hda_codec_cleanup(apcm->codec, hinfo, substream); |
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|
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azx_stream(azx_dev)->prepared = 0; |
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dsp_unlock(azx_dev); |
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return 0; |
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} |
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|
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static int azx_pcm_prepare(struct snd_pcm_substream *substream) |
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{ |
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
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struct azx *chip = apcm->chip; |
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struct azx_dev *azx_dev = get_azx_dev(substream); |
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struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
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struct snd_pcm_runtime *runtime = substream->runtime; |
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unsigned int format_val, stream_tag; |
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int err; |
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struct hda_spdif_out *spdif = |
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snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); |
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unsigned short ctls = spdif ? spdif->ctls : 0; |
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|
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trace_azx_pcm_prepare(chip, azx_dev); |
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dsp_lock(azx_dev); |
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if (dsp_is_locked(azx_dev)) { |
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err = -EBUSY; |
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goto unlock; |
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} |
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|
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snd_hdac_stream_reset(azx_stream(azx_dev)); |
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format_val = snd_hdac_calc_stream_format(runtime->rate, |
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runtime->channels, |
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runtime->format, |
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hinfo->maxbps, |
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ctls); |
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if (!format_val) { |
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dev_err(chip->card->dev, |
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"invalid format_val, rate=%d, ch=%d, format=%d\n", |
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runtime->rate, runtime->channels, runtime->format); |
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err = -EINVAL; |
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goto unlock; |
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} |
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|
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err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val); |
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if (err < 0) |
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goto unlock; |
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snd_hdac_stream_setup(azx_stream(azx_dev)); |
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|
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stream_tag = azx_dev->core.stream_tag; |
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/* CA-IBG chips need the playback stream starting from 1 */ |
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if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && |
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stream_tag > chip->capture_streams) |
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stream_tag -= chip->capture_streams; |
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err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, |
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azx_dev->core.format_val, substream); |
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|
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unlock: |
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if (!err) |
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azx_stream(azx_dev)->prepared = 1; |
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dsp_unlock(azx_dev); |
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return err; |
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} |
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|
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static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
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{ |
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
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struct azx *chip = apcm->chip; |
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struct hdac_bus *bus = azx_bus(chip); |
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struct azx_dev *azx_dev; |
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struct snd_pcm_substream *s; |
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struct hdac_stream *hstr; |
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bool start; |
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int sbits = 0; |
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int sync_reg; |
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azx_dev = get_azx_dev(substream); |
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trace_azx_pcm_trigger(chip, azx_dev, cmd); |
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hstr = azx_stream(azx_dev); |
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if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) |
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sync_reg = AZX_REG_OLD_SSYNC; |
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else |
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sync_reg = AZX_REG_SSYNC; |
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|
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if (dsp_is_locked(azx_dev) || !hstr->prepared) |
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return -EPIPE; |
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|
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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start = true; |
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break; |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_STOP: |
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start = false; |
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break; |
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default: |
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return -EINVAL; |
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} |
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|
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snd_pcm_group_for_each_entry(s, substream) { |
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if (s->pcm->card != substream->pcm->card) |
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continue; |
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azx_dev = get_azx_dev(s); |
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sbits |= 1 << azx_dev->core.index; |
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snd_pcm_trigger_done(s, substream); |
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} |
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spin_lock(&bus->reg_lock); |
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|
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/* first, set SYNC bits of corresponding streams */ |
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snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg); |
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snd_pcm_group_for_each_entry(s, substream) { |
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if (s->pcm->card != substream->pcm->card) |
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continue; |
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azx_dev = get_azx_dev(s); |
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if (start) { |
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azx_dev->insufficient = 1; |
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snd_hdac_stream_start(azx_stream(azx_dev), true); |
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} else { |
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snd_hdac_stream_stop(azx_stream(azx_dev)); |
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} |
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} |
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spin_unlock(&bus->reg_lock); |
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|
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snd_hdac_stream_sync(hstr, start, sbits); |
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|
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spin_lock(&bus->reg_lock); |
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/* reset SYNC bits */ |
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snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg); |
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if (start) |
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snd_hdac_stream_timecounter_init(hstr, sbits); |
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spin_unlock(&bus->reg_lock); |
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return 0; |
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} |
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unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev) |
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{ |
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return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); |
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} |
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EXPORT_SYMBOL_GPL(azx_get_pos_lpib); |
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|
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unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev) |
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{ |
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return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev)); |
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} |
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EXPORT_SYMBOL_GPL(azx_get_pos_posbuf); |
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|
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unsigned int azx_get_position(struct azx *chip, |
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struct azx_dev *azx_dev) |
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{ |
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struct snd_pcm_substream *substream = azx_dev->core.substream; |
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unsigned int pos; |
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int stream = substream->stream; |
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int delay = 0; |
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|
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if (chip->get_position[stream]) |
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pos = chip->get_position[stream](chip, azx_dev); |
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else /* use the position buffer as default */ |
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pos = azx_get_pos_posbuf(chip, azx_dev); |
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|
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if (pos >= azx_dev->core.bufsize) |
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pos = 0; |
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|
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if (substream->runtime) { |
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
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struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
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|
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if (chip->get_delay[stream]) |
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delay += chip->get_delay[stream](chip, azx_dev, pos); |
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if (hinfo->ops.get_delay) |
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delay += hinfo->ops.get_delay(hinfo, apcm->codec, |
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substream); |
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substream->runtime->delay = delay; |
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} |
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trace_azx_get_position(chip, azx_dev, pos, delay); |
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return pos; |
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} |
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EXPORT_SYMBOL_GPL(azx_get_position); |
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static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) |
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{ |
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
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struct azx *chip = apcm->chip; |
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struct azx_dev *azx_dev = get_azx_dev(substream); |
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return bytes_to_frames(substream->runtime, |
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azx_get_position(chip, azx_dev)); |
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} |
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|
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/* |
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* azx_scale64: Scale base by mult/div while not overflowing sanely |
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* |
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* Derived from scale64_check_overflow in kernel/time/timekeeping.c |
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* |
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* The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which |
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* is about 384307 ie ~4.5 days. |
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* |
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* This scales the calculation so that overflow will happen but after 2^64 / |
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* 48000 secs, which is pretty large! |
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* |
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* In caln below: |
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* base may overflow, but since there isn’t any additional division |
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* performed on base it’s OK |
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* rem can’t overflow because both are 32-bit values |
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*/ |
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|
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#ifdef CONFIG_X86 |
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static u64 azx_scale64(u64 base, u32 num, u32 den) |
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{ |
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u64 rem; |
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|
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rem = do_div(base, den); |
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|
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base *= num; |
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rem *= num; |
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|
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do_div(rem, den); |
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|
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return base + rem; |
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} |
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|
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static int azx_get_sync_time(ktime_t *device, |
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struct system_counterval_t *system, void *ctx) |
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{ |
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struct snd_pcm_substream *substream = ctx; |
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struct azx_dev *azx_dev = get_azx_dev(substream); |
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
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struct azx *chip = apcm->chip; |
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struct snd_pcm_runtime *runtime; |
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u64 ll_counter, ll_counter_l, ll_counter_h; |
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u64 tsc_counter, tsc_counter_l, tsc_counter_h; |
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u32 wallclk_ctr, wallclk_cycles; |
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bool direction; |
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u32 dma_select; |
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u32 timeout; |
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u32 retry_count = 0; |
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|
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runtime = substream->runtime; |
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|
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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direction = 1; |
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else |
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direction = 0; |
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|
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/* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */ |
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do { |
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timeout = 100; |
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dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) | |
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(azx_dev->core.stream_tag - 1); |
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snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select); |
|
|
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/* Enable the capture */ |
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snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK); |
|
|
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while (timeout) { |
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if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) & |
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GTSCC_TSCCD_MASK) |
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break; |
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|
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timeout--; |
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} |
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|
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if (!timeout) { |
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dev_err(chip->card->dev, "GTSCC capture Timedout!\n"); |
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return -EIO; |
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} |
|
|
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/* Read wall clock counter */ |
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wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC); |
|
|
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/* Read TSC counter */ |
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tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL); |
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tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU); |
|
|
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/* Read Link counter */ |
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ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL); |
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ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU); |
|
|
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/* Ack: registers read done */ |
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snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT); |
|
|
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tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) | |
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tsc_counter_l; |
|
|
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ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) | ll_counter_l; |
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wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK; |
|
|
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/* |
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* An error occurs near frame "rollover". The clocks in |
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* frame value indicates whether this error may have |
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* occurred. Here we use the value of 10 i.e., |
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* HDA_MAX_CYCLE_OFFSET |
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*/ |
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if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET |
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&& wallclk_cycles > HDA_MAX_CYCLE_OFFSET) |
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break; |
|
|
|
/* |
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* Sleep before we read again, else we may again get |
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* value near to MAX_CYCLE. Try to sleep for different |
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* amount of time so we dont hit the same number again |
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*/ |
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udelay(retry_count++); |
|
|
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} while (retry_count != HDA_MAX_CYCLE_READ_RETRY); |
|
|
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if (retry_count == HDA_MAX_CYCLE_READ_RETRY) { |
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dev_err_ratelimited(chip->card->dev, |
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"Error in WALFCC cycle count\n"); |
|
return -EIO; |
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} |
|
|
|
*device = ns_to_ktime(azx_scale64(ll_counter, |
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NSEC_PER_SEC, runtime->rate)); |
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*device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) / |
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((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate)); |
|
|
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*system = convert_art_to_tsc(tsc_counter); |
|
|
|
return 0; |
|
} |
|
|
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#else |
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static int azx_get_sync_time(ktime_t *device, |
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struct system_counterval_t *system, void *ctx) |
|
{ |
|
return -ENXIO; |
|
} |
|
#endif |
|
|
|
static int azx_get_crosststamp(struct snd_pcm_substream *substream, |
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struct system_device_crosststamp *xtstamp) |
|
{ |
|
return get_device_system_crosststamp(azx_get_sync_time, |
|
substream, NULL, xtstamp); |
|
} |
|
|
|
static inline bool is_link_time_supported(struct snd_pcm_runtime *runtime, |
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struct snd_pcm_audio_tstamp_config *ts) |
|
{ |
|
if (runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME) |
|
if (ts->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED) |
|
return true; |
|
|
|
return false; |
|
} |
|
|
|
static int azx_get_time_info(struct snd_pcm_substream *substream, |
|
struct timespec64 *system_ts, struct timespec64 *audio_ts, |
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struct snd_pcm_audio_tstamp_config *audio_tstamp_config, |
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struct snd_pcm_audio_tstamp_report *audio_tstamp_report) |
|
{ |
|
struct azx_dev *azx_dev = get_azx_dev(substream); |
|
struct snd_pcm_runtime *runtime = substream->runtime; |
|
struct system_device_crosststamp xtstamp; |
|
int ret; |
|
u64 nsec; |
|
|
|
if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) && |
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(audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) { |
|
|
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snd_pcm_gettime(substream->runtime, system_ts); |
|
|
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nsec = timecounter_read(&azx_dev->core.tc); |
|
nsec = div_u64(nsec, 3); /* can be optimized */ |
|
if (audio_tstamp_config->report_delay) |
|
nsec = azx_adjust_codec_delay(substream, nsec); |
|
|
|
*audio_ts = ns_to_timespec64(nsec); |
|
|
|
audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK; |
|
audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */ |
|
audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */ |
|
|
|
} else if (is_link_time_supported(runtime, audio_tstamp_config)) { |
|
|
|
ret = azx_get_crosststamp(substream, &xtstamp); |
|
if (ret) |
|
return ret; |
|
|
|
switch (runtime->tstamp_type) { |
|
case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC: |
|
return -EINVAL; |
|
|
|
case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW: |
|
*system_ts = ktime_to_timespec64(xtstamp.sys_monoraw); |
|
break; |
|
|
|
default: |
|
*system_ts = ktime_to_timespec64(xtstamp.sys_realtime); |
|
break; |
|
|
|
} |
|
|
|
*audio_ts = ktime_to_timespec64(xtstamp.device); |
|
|
|
audio_tstamp_report->actual_type = |
|
SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED; |
|
audio_tstamp_report->accuracy_report = 1; |
|
/* 24 MHz WallClock == 42ns resolution */ |
|
audio_tstamp_report->accuracy = 42; |
|
|
|
} else { |
|
audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct snd_pcm_hardware azx_pcm_hw = { |
|
.info = (SNDRV_PCM_INFO_MMAP | |
|
SNDRV_PCM_INFO_INTERLEAVED | |
|
SNDRV_PCM_INFO_BLOCK_TRANSFER | |
|
SNDRV_PCM_INFO_MMAP_VALID | |
|
/* No full-resume yet implemented */ |
|
/* SNDRV_PCM_INFO_RESUME |*/ |
|
SNDRV_PCM_INFO_PAUSE | |
|
SNDRV_PCM_INFO_SYNC_START | |
|
SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */ |
|
SNDRV_PCM_INFO_HAS_LINK_ATIME | |
|
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), |
|
.formats = SNDRV_PCM_FMTBIT_S16_LE, |
|
.rates = SNDRV_PCM_RATE_48000, |
|
.rate_min = 48000, |
|
.rate_max = 48000, |
|
.channels_min = 2, |
|
.channels_max = 2, |
|
.buffer_bytes_max = AZX_MAX_BUF_SIZE, |
|
.period_bytes_min = 128, |
|
.period_bytes_max = AZX_MAX_BUF_SIZE / 2, |
|
.periods_min = 2, |
|
.periods_max = AZX_MAX_FRAG, |
|
.fifo_size = 0, |
|
}; |
|
|
|
static int azx_pcm_open(struct snd_pcm_substream *substream) |
|
{ |
|
struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
|
struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
|
struct azx *chip = apcm->chip; |
|
struct azx_dev *azx_dev; |
|
struct snd_pcm_runtime *runtime = substream->runtime; |
|
int err; |
|
int buff_step; |
|
|
|
snd_hda_codec_pcm_get(apcm->info); |
|
mutex_lock(&chip->open_mutex); |
|
azx_dev = azx_assign_device(chip, substream); |
|
trace_azx_pcm_open(chip, azx_dev); |
|
if (azx_dev == NULL) { |
|
err = -EBUSY; |
|
goto unlock; |
|
} |
|
runtime->private_data = azx_dev; |
|
|
|
runtime->hw = azx_pcm_hw; |
|
if (chip->gts_present) |
|
runtime->hw.info |= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME; |
|
runtime->hw.channels_min = hinfo->channels_min; |
|
runtime->hw.channels_max = hinfo->channels_max; |
|
runtime->hw.formats = hinfo->formats; |
|
runtime->hw.rates = hinfo->rates; |
|
snd_pcm_limit_hw_rates(runtime); |
|
snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); |
|
|
|
/* avoid wrap-around with wall-clock */ |
|
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, |
|
20, |
|
178000000); |
|
|
|
if (chip->align_buffer_size) |
|
/* constrain buffer sizes to be multiple of 128 |
|
bytes. This is more efficient in terms of memory |
|
access but isn't required by the HDA spec and |
|
prevents users from specifying exact period/buffer |
|
sizes. For example for 44.1kHz, a period size set |
|
to 20ms will be rounded to 19.59ms. */ |
|
buff_step = 128; |
|
else |
|
/* Don't enforce steps on buffer sizes, still need to |
|
be multiple of 4 bytes (HDA spec). Tested on Intel |
|
HDA controllers, may not work on all devices where |
|
option needs to be disabled */ |
|
buff_step = 4; |
|
|
|
snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, |
|
buff_step); |
|
snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, |
|
buff_step); |
|
snd_hda_power_up(apcm->codec); |
|
if (hinfo->ops.open) |
|
err = hinfo->ops.open(hinfo, apcm->codec, substream); |
|
else |
|
err = -ENODEV; |
|
if (err < 0) { |
|
azx_release_device(azx_dev); |
|
goto powerdown; |
|
} |
|
snd_pcm_limit_hw_rates(runtime); |
|
/* sanity check */ |
|
if (snd_BUG_ON(!runtime->hw.channels_min) || |
|
snd_BUG_ON(!runtime->hw.channels_max) || |
|
snd_BUG_ON(!runtime->hw.formats) || |
|
snd_BUG_ON(!runtime->hw.rates)) { |
|
azx_release_device(azx_dev); |
|
if (hinfo->ops.close) |
|
hinfo->ops.close(hinfo, apcm->codec, substream); |
|
err = -EINVAL; |
|
goto powerdown; |
|
} |
|
|
|
/* disable LINK_ATIME timestamps for capture streams |
|
until we figure out how to handle digital inputs */ |
|
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
|
runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */ |
|
runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME; |
|
} |
|
|
|
snd_pcm_set_sync(substream); |
|
mutex_unlock(&chip->open_mutex); |
|
return 0; |
|
|
|
powerdown: |
|
snd_hda_power_down(apcm->codec); |
|
unlock: |
|
mutex_unlock(&chip->open_mutex); |
|
snd_hda_codec_pcm_put(apcm->info); |
|
return err; |
|
} |
|
|
|
static int azx_pcm_mmap(struct snd_pcm_substream *substream, |
|
struct vm_area_struct *area) |
|
{ |
|
struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
|
struct azx *chip = apcm->chip; |
|
if (chip->ops->pcm_mmap_prepare) |
|
chip->ops->pcm_mmap_prepare(substream, area); |
|
return snd_pcm_lib_default_mmap(substream, area); |
|
} |
|
|
|
static const struct snd_pcm_ops azx_pcm_ops = { |
|
.open = azx_pcm_open, |
|
.close = azx_pcm_close, |
|
.hw_params = azx_pcm_hw_params, |
|
.hw_free = azx_pcm_hw_free, |
|
.prepare = azx_pcm_prepare, |
|
.trigger = azx_pcm_trigger, |
|
.pointer = azx_pcm_pointer, |
|
.get_time_info = azx_get_time_info, |
|
.mmap = azx_pcm_mmap, |
|
}; |
|
|
|
static void azx_pcm_free(struct snd_pcm *pcm) |
|
{ |
|
struct azx_pcm *apcm = pcm->private_data; |
|
if (apcm) { |
|
list_del(&apcm->list); |
|
apcm->info->pcm = NULL; |
|
kfree(apcm); |
|
} |
|
} |
|
|
|
#define MAX_PREALLOC_SIZE (32 * 1024 * 1024) |
|
|
|
int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec, |
|
struct hda_pcm *cpcm) |
|
{ |
|
struct hdac_bus *bus = &_bus->core; |
|
struct azx *chip = bus_to_azx(bus); |
|
struct snd_pcm *pcm; |
|
struct azx_pcm *apcm; |
|
int pcm_dev = cpcm->device; |
|
unsigned int size; |
|
int s, err; |
|
int type = SNDRV_DMA_TYPE_DEV_SG; |
|
|
|
list_for_each_entry(apcm, &chip->pcm_list, list) { |
|
if (apcm->pcm->device == pcm_dev) { |
|
dev_err(chip->card->dev, "PCM %d already exists\n", |
|
pcm_dev); |
|
return -EBUSY; |
|
} |
|
} |
|
err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, |
|
cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, |
|
cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, |
|
&pcm); |
|
if (err < 0) |
|
return err; |
|
strscpy(pcm->name, cpcm->name, sizeof(pcm->name)); |
|
apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); |
|
if (apcm == NULL) { |
|
snd_device_free(chip->card, pcm); |
|
return -ENOMEM; |
|
} |
|
apcm->chip = chip; |
|
apcm->pcm = pcm; |
|
apcm->codec = codec; |
|
apcm->info = cpcm; |
|
pcm->private_data = apcm; |
|
pcm->private_free = azx_pcm_free; |
|
if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) |
|
pcm->dev_class = SNDRV_PCM_CLASS_MODEM; |
|
list_add_tail(&apcm->list, &chip->pcm_list); |
|
cpcm->pcm = pcm; |
|
for (s = 0; s < 2; s++) { |
|
if (cpcm->stream[s].substreams) |
|
snd_pcm_set_ops(pcm, s, &azx_pcm_ops); |
|
} |
|
/* buffer pre-allocation */ |
|
size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; |
|
if (size > MAX_PREALLOC_SIZE) |
|
size = MAX_PREALLOC_SIZE; |
|
if (chip->uc_buffer) |
|
type = SNDRV_DMA_TYPE_DEV_UC_SG; |
|
snd_pcm_set_managed_buffer_all(pcm, type, chip->card->dev, |
|
size, MAX_PREALLOC_SIZE); |
|
return 0; |
|
} |
|
|
|
static unsigned int azx_command_addr(u32 cmd) |
|
{ |
|
unsigned int addr = cmd >> 28; |
|
|
|
if (addr >= AZX_MAX_CODECS) { |
|
snd_BUG(); |
|
addr = 0; |
|
} |
|
|
|
return addr; |
|
} |
|
|
|
/* receive a response */ |
|
static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr, |
|
unsigned int *res) |
|
{ |
|
struct azx *chip = bus_to_azx(bus); |
|
struct hda_bus *hbus = &chip->bus; |
|
int err; |
|
|
|
again: |
|
err = snd_hdac_bus_get_response(bus, addr, res); |
|
if (!err) |
|
return 0; |
|
|
|
if (hbus->no_response_fallback) |
|
return -EIO; |
|
|
|
if (!bus->polling_mode) { |
|
dev_warn(chip->card->dev, |
|
"azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n", |
|
bus->last_cmd[addr]); |
|
bus->polling_mode = 1; |
|
goto again; |
|
} |
|
|
|
if (chip->msi) { |
|
dev_warn(chip->card->dev, |
|
"No response from codec, disabling MSI: last cmd=0x%08x\n", |
|
bus->last_cmd[addr]); |
|
if (chip->ops->disable_msi_reset_irq && |
|
chip->ops->disable_msi_reset_irq(chip) < 0) |
|
return -EIO; |
|
goto again; |
|
} |
|
|
|
if (chip->probing) { |
|
/* If this critical timeout happens during the codec probing |
|
* phase, this is likely an access to a non-existing codec |
|
* slot. Better to return an error and reset the system. |
|
*/ |
|
return -EIO; |
|
} |
|
|
|
/* no fallback mechanism? */ |
|
if (!chip->fallback_to_single_cmd) |
|
return -EIO; |
|
|
|
/* a fatal communication error; need either to reset or to fallback |
|
* to the single_cmd mode |
|
*/ |
|
if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) { |
|
hbus->response_reset = 1; |
|
dev_err(chip->card->dev, |
|
"No response from codec, resetting bus: last cmd=0x%08x\n", |
|
bus->last_cmd[addr]); |
|
return -EAGAIN; /* give a chance to retry */ |
|
} |
|
|
|
dev_err(chip->card->dev, |
|
"azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n", |
|
bus->last_cmd[addr]); |
|
chip->single_cmd = 1; |
|
hbus->response_reset = 0; |
|
snd_hdac_bus_stop_cmd_io(bus); |
|
return -EIO; |
|
} |
|
|
|
/* |
|
* Use the single immediate command instead of CORB/RIRB for simplicity |
|
* |
|
* Note: according to Intel, this is not preferred use. The command was |
|
* intended for the BIOS only, and may get confused with unsolicited |
|
* responses. So, we shouldn't use it for normal operation from the |
|
* driver. |
|
* I left the codes, however, for debugging/testing purposes. |
|
*/ |
|
|
|
/* receive a response */ |
|
static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) |
|
{ |
|
int timeout = 50; |
|
|
|
while (timeout--) { |
|
/* check IRV busy bit */ |
|
if (azx_readw(chip, IRS) & AZX_IRS_VALID) { |
|
/* reuse rirb.res as the response return value */ |
|
azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR); |
|
return 0; |
|
} |
|
udelay(1); |
|
} |
|
if (printk_ratelimit()) |
|
dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n", |
|
azx_readw(chip, IRS)); |
|
azx_bus(chip)->rirb.res[addr] = -1; |
|
return -EIO; |
|
} |
|
|
|
/* send a command */ |
|
static int azx_single_send_cmd(struct hdac_bus *bus, u32 val) |
|
{ |
|
struct azx *chip = bus_to_azx(bus); |
|
unsigned int addr = azx_command_addr(val); |
|
int timeout = 50; |
|
|
|
bus->last_cmd[azx_command_addr(val)] = val; |
|
while (timeout--) { |
|
/* check ICB busy bit */ |
|
if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) { |
|
/* Clear IRV valid bit */ |
|
azx_writew(chip, IRS, azx_readw(chip, IRS) | |
|
AZX_IRS_VALID); |
|
azx_writel(chip, IC, val); |
|
azx_writew(chip, IRS, azx_readw(chip, IRS) | |
|
AZX_IRS_BUSY); |
|
return azx_single_wait_for_response(chip, addr); |
|
} |
|
udelay(1); |
|
} |
|
if (printk_ratelimit()) |
|
dev_dbg(chip->card->dev, |
|
"send_cmd timeout: IRS=0x%x, val=0x%x\n", |
|
azx_readw(chip, IRS), val); |
|
return -EIO; |
|
} |
|
|
|
/* receive a response */ |
|
static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr, |
|
unsigned int *res) |
|
{ |
|
if (res) |
|
*res = bus->rirb.res[addr]; |
|
return 0; |
|
} |
|
|
|
/* |
|
* The below are the main callbacks from hda_codec. |
|
* |
|
* They are just the skeleton to call sub-callbacks according to the |
|
* current setting of chip->single_cmd. |
|
*/ |
|
|
|
/* send a command */ |
|
static int azx_send_cmd(struct hdac_bus *bus, unsigned int val) |
|
{ |
|
struct azx *chip = bus_to_azx(bus); |
|
|
|
if (chip->disabled) |
|
return 0; |
|
if (chip->single_cmd) |
|
return azx_single_send_cmd(bus, val); |
|
else |
|
return snd_hdac_bus_send_cmd(bus, val); |
|
} |
|
|
|
/* get a response */ |
|
static int azx_get_response(struct hdac_bus *bus, unsigned int addr, |
|
unsigned int *res) |
|
{ |
|
struct azx *chip = bus_to_azx(bus); |
|
|
|
if (chip->disabled) |
|
return 0; |
|
if (chip->single_cmd) |
|
return azx_single_get_response(bus, addr, res); |
|
else |
|
return azx_rirb_get_response(bus, addr, res); |
|
} |
|
|
|
static const struct hdac_bus_ops bus_core_ops = { |
|
.command = azx_send_cmd, |
|
.get_response = azx_get_response, |
|
}; |
|
|
|
#ifdef CONFIG_SND_HDA_DSP_LOADER |
|
/* |
|
* DSP loading code (e.g. for CA0132) |
|
*/ |
|
|
|
/* use the first stream for loading DSP */ |
|
static struct azx_dev * |
|
azx_get_dsp_loader_dev(struct azx *chip) |
|
{ |
|
struct hdac_bus *bus = azx_bus(chip); |
|
struct hdac_stream *s; |
|
|
|
list_for_each_entry(s, &bus->stream_list, list) |
|
if (s->index == chip->playback_index_offset) |
|
return stream_to_azx_dev(s); |
|
|
|
return NULL; |
|
} |
|
|
|
int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format, |
|
unsigned int byte_size, |
|
struct snd_dma_buffer *bufp) |
|
{ |
|
struct hdac_bus *bus = &codec->bus->core; |
|
struct azx *chip = bus_to_azx(bus); |
|
struct azx_dev *azx_dev; |
|
struct hdac_stream *hstr; |
|
bool saved = false; |
|
int err; |
|
|
|
azx_dev = azx_get_dsp_loader_dev(chip); |
|
hstr = azx_stream(azx_dev); |
|
spin_lock_irq(&bus->reg_lock); |
|
if (hstr->opened) { |
|
chip->saved_azx_dev = *azx_dev; |
|
saved = true; |
|
} |
|
spin_unlock_irq(&bus->reg_lock); |
|
|
|
err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp); |
|
if (err < 0) { |
|
spin_lock_irq(&bus->reg_lock); |
|
if (saved) |
|
*azx_dev = chip->saved_azx_dev; |
|
spin_unlock_irq(&bus->reg_lock); |
|
return err; |
|
} |
|
|
|
hstr->prepared = 0; |
|
return err; |
|
} |
|
EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare); |
|
|
|
void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start) |
|
{ |
|
struct hdac_bus *bus = &codec->bus->core; |
|
struct azx *chip = bus_to_azx(bus); |
|
struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); |
|
|
|
snd_hdac_dsp_trigger(azx_stream(azx_dev), start); |
|
} |
|
EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger); |
|
|
|
void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec, |
|
struct snd_dma_buffer *dmab) |
|
{ |
|
struct hdac_bus *bus = &codec->bus->core; |
|
struct azx *chip = bus_to_azx(bus); |
|
struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); |
|
struct hdac_stream *hstr = azx_stream(azx_dev); |
|
|
|
if (!dmab->area || !hstr->locked) |
|
return; |
|
|
|
snd_hdac_dsp_cleanup(hstr, dmab); |
|
spin_lock_irq(&bus->reg_lock); |
|
if (hstr->opened) |
|
*azx_dev = chip->saved_azx_dev; |
|
hstr->locked = false; |
|
spin_unlock_irq(&bus->reg_lock); |
|
} |
|
EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup); |
|
#endif /* CONFIG_SND_HDA_DSP_LOADER */ |
|
|
|
/* |
|
* reset and start the controller registers |
|
*/ |
|
void azx_init_chip(struct azx *chip, bool full_reset) |
|
{ |
|
if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) { |
|
/* correct RINTCNT for CXT */ |
|
if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) |
|
azx_writew(chip, RINTCNT, 0xc0); |
|
} |
|
} |
|
EXPORT_SYMBOL_GPL(azx_init_chip); |
|
|
|
void azx_stop_all_streams(struct azx *chip) |
|
{ |
|
struct hdac_bus *bus = azx_bus(chip); |
|
struct hdac_stream *s; |
|
|
|
list_for_each_entry(s, &bus->stream_list, list) |
|
snd_hdac_stream_stop(s); |
|
} |
|
EXPORT_SYMBOL_GPL(azx_stop_all_streams); |
|
|
|
void azx_stop_chip(struct azx *chip) |
|
{ |
|
snd_hdac_bus_stop_chip(azx_bus(chip)); |
|
} |
|
EXPORT_SYMBOL_GPL(azx_stop_chip); |
|
|
|
/* |
|
* interrupt handler |
|
*/ |
|
static void stream_update(struct hdac_bus *bus, struct hdac_stream *s) |
|
{ |
|
struct azx *chip = bus_to_azx(bus); |
|
struct azx_dev *azx_dev = stream_to_azx_dev(s); |
|
|
|
/* check whether this IRQ is really acceptable */ |
|
if (!chip->ops->position_check || |
|
chip->ops->position_check(chip, azx_dev)) { |
|
spin_unlock(&bus->reg_lock); |
|
snd_pcm_period_elapsed(azx_stream(azx_dev)->substream); |
|
spin_lock(&bus->reg_lock); |
|
} |
|
} |
|
|
|
irqreturn_t azx_interrupt(int irq, void *dev_id) |
|
{ |
|
struct azx *chip = dev_id; |
|
struct hdac_bus *bus = azx_bus(chip); |
|
u32 status; |
|
bool active, handled = false; |
|
int repeat = 0; /* count for avoiding endless loop */ |
|
|
|
#ifdef CONFIG_PM |
|
if (azx_has_pm_runtime(chip)) |
|
if (!pm_runtime_active(chip->card->dev)) |
|
return IRQ_NONE; |
|
#endif |
|
|
|
spin_lock(&bus->reg_lock); |
|
|
|
if (chip->disabled) |
|
goto unlock; |
|
|
|
do { |
|
status = azx_readl(chip, INTSTS); |
|
if (status == 0 || status == 0xffffffff) |
|
break; |
|
|
|
handled = true; |
|
active = false; |
|
if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update)) |
|
active = true; |
|
|
|
status = azx_readb(chip, RIRBSTS); |
|
if (status & RIRB_INT_MASK) { |
|
/* |
|
* Clearing the interrupt status here ensures that no |
|
* interrupt gets masked after the RIRB wp is read in |
|
* snd_hdac_bus_update_rirb. This avoids a possible |
|
* race condition where codec response in RIRB may |
|
* remain unserviced by IRQ, eventually falling back |
|
* to polling mode in azx_rirb_get_response. |
|
*/ |
|
azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); |
|
active = true; |
|
if (status & RIRB_INT_RESPONSE) { |
|
if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) |
|
udelay(80); |
|
snd_hdac_bus_update_rirb(bus); |
|
} |
|
} |
|
} while (active && ++repeat < 10); |
|
|
|
unlock: |
|
spin_unlock(&bus->reg_lock); |
|
|
|
return IRQ_RETVAL(handled); |
|
} |
|
EXPORT_SYMBOL_GPL(azx_interrupt); |
|
|
|
/* |
|
* Codec initerface |
|
*/ |
|
|
|
/* |
|
* Probe the given codec address |
|
*/ |
|
static int probe_codec(struct azx *chip, int addr) |
|
{ |
|
unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | |
|
(AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; |
|
struct hdac_bus *bus = azx_bus(chip); |
|
int err; |
|
unsigned int res = -1; |
|
|
|
mutex_lock(&bus->cmd_mutex); |
|
chip->probing = 1; |
|
azx_send_cmd(bus, cmd); |
|
err = azx_get_response(bus, addr, &res); |
|
chip->probing = 0; |
|
mutex_unlock(&bus->cmd_mutex); |
|
if (err < 0 || res == -1) |
|
return -EIO; |
|
dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr); |
|
return 0; |
|
} |
|
|
|
void snd_hda_bus_reset(struct hda_bus *bus) |
|
{ |
|
struct azx *chip = bus_to_azx(&bus->core); |
|
|
|
bus->in_reset = 1; |
|
azx_stop_chip(chip); |
|
azx_init_chip(chip, true); |
|
if (bus->core.chip_init) |
|
snd_hda_bus_reset_codecs(bus); |
|
bus->in_reset = 0; |
|
} |
|
|
|
/* HD-audio bus initialization */ |
|
int azx_bus_init(struct azx *chip, const char *model) |
|
{ |
|
struct hda_bus *bus = &chip->bus; |
|
int err; |
|
|
|
err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops); |
|
if (err < 0) |
|
return err; |
|
|
|
bus->card = chip->card; |
|
mutex_init(&bus->prepare_mutex); |
|
bus->pci = chip->pci; |
|
bus->modelname = model; |
|
bus->mixer_assigned = -1; |
|
bus->core.snoop = azx_snoop(chip); |
|
if (chip->get_position[0] != azx_get_pos_lpib || |
|
chip->get_position[1] != azx_get_pos_lpib) |
|
bus->core.use_posbuf = true; |
|
bus->core.bdl_pos_adj = chip->bdl_pos_adj; |
|
if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR) |
|
bus->core.corbrp_self_clear = true; |
|
|
|
if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) |
|
bus->core.align_bdle_4k = true; |
|
|
|
/* enable sync_write flag for stable communication as default */ |
|
bus->core.sync_write = 1; |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(azx_bus_init); |
|
|
|
/* Probe codecs */ |
|
int azx_probe_codecs(struct azx *chip, unsigned int max_slots) |
|
{ |
|
struct hdac_bus *bus = azx_bus(chip); |
|
int c, codecs, err; |
|
|
|
codecs = 0; |
|
if (!max_slots) |
|
max_slots = AZX_DEFAULT_CODECS; |
|
|
|
/* First try to probe all given codec slots */ |
|
for (c = 0; c < max_slots; c++) { |
|
if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
|
if (probe_codec(chip, c) < 0) { |
|
/* Some BIOSen give you wrong codec addresses |
|
* that don't exist |
|
*/ |
|
dev_warn(chip->card->dev, |
|
"Codec #%d probe error; disabling it...\n", c); |
|
bus->codec_mask &= ~(1 << c); |
|
/* More badly, accessing to a non-existing |
|
* codec often screws up the controller chip, |
|
* and disturbs the further communications. |
|
* Thus if an error occurs during probing, |
|
* better to reset the controller chip to |
|
* get back to the sanity state. |
|
*/ |
|
azx_stop_chip(chip); |
|
azx_init_chip(chip, true); |
|
} |
|
} |
|
} |
|
|
|
/* Then create codec instances */ |
|
for (c = 0; c < max_slots; c++) { |
|
if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
|
struct hda_codec *codec; |
|
err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec); |
|
if (err < 0) |
|
continue; |
|
codec->jackpoll_interval = chip->jackpoll_interval; |
|
codec->beep_mode = chip->beep_mode; |
|
codecs++; |
|
} |
|
} |
|
if (!codecs) { |
|
dev_err(chip->card->dev, "no codecs initialized\n"); |
|
return -ENXIO; |
|
} |
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(azx_probe_codecs); |
|
|
|
/* configure each codec instance */ |
|
int azx_codec_configure(struct azx *chip) |
|
{ |
|
struct hda_codec *codec, *next; |
|
|
|
/* use _safe version here since snd_hda_codec_configure() deregisters |
|
* the device upon error and deletes itself from the bus list. |
|
*/ |
|
list_for_each_codec_safe(codec, next, &chip->bus) { |
|
snd_hda_codec_configure(codec); |
|
} |
|
|
|
if (!azx_bus(chip)->num_codecs) |
|
return -ENODEV; |
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(azx_codec_configure); |
|
|
|
static int stream_direction(struct azx *chip, unsigned char index) |
|
{ |
|
if (index >= chip->capture_index_offset && |
|
index < chip->capture_index_offset + chip->capture_streams) |
|
return SNDRV_PCM_STREAM_CAPTURE; |
|
return SNDRV_PCM_STREAM_PLAYBACK; |
|
} |
|
|
|
/* initialize SD streams */ |
|
int azx_init_streams(struct azx *chip) |
|
{ |
|
int i; |
|
int stream_tags[2] = { 0, 0 }; |
|
|
|
/* initialize each stream (aka device) |
|
* assign the starting bdl address to each stream (device) |
|
* and initialize |
|
*/ |
|
for (i = 0; i < chip->num_streams; i++) { |
|
struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL); |
|
int dir, tag; |
|
|
|
if (!azx_dev) |
|
return -ENOMEM; |
|
|
|
dir = stream_direction(chip, i); |
|
/* stream tag must be unique throughout |
|
* the stream direction group, |
|
* valid values 1...15 |
|
* use separate stream tag if the flag |
|
* AZX_DCAPS_SEPARATE_STREAM_TAG is used |
|
*/ |
|
if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) |
|
tag = ++stream_tags[dir]; |
|
else |
|
tag = i + 1; |
|
snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev), |
|
i, dir, tag); |
|
} |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(azx_init_streams); |
|
|
|
void azx_free_streams(struct azx *chip) |
|
{ |
|
struct hdac_bus *bus = azx_bus(chip); |
|
struct hdac_stream *s; |
|
|
|
while (!list_empty(&bus->stream_list)) { |
|
s = list_first_entry(&bus->stream_list, struct hdac_stream, list); |
|
list_del(&s->list); |
|
kfree(stream_to_azx_dev(s)); |
|
} |
|
} |
|
EXPORT_SYMBOL_GPL(azx_free_streams);
|
|
|