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1580 lines
41 KiB
1580 lines
41 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd |
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* Caesar Wang <[email protected]> |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/reset.h> |
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#include <linux/thermal.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/pinctrl/consumer.h> |
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|
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/* |
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* If the temperature over a period of time High, |
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* the resulting TSHUT gave CRU module,let it reset the entire chip, |
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* or via GPIO give PMIC. |
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*/ |
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enum tshut_mode { |
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TSHUT_MODE_CRU = 0, |
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TSHUT_MODE_GPIO, |
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}; |
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|
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/* |
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* The system Temperature Sensors tshut(tshut) polarity |
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* the bit 8 is tshut polarity. |
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* 0: low active, 1: high active |
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*/ |
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enum tshut_polarity { |
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TSHUT_LOW_ACTIVE = 0, |
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TSHUT_HIGH_ACTIVE, |
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}; |
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|
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/* |
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* The system has two Temperature Sensors. |
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* sensor0 is for CPU, and sensor1 is for GPU. |
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*/ |
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enum sensor_id { |
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SENSOR_CPU = 0, |
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SENSOR_GPU, |
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}; |
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|
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/* |
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* The conversion table has the adc value and temperature. |
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* ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) |
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* ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) |
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*/ |
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enum adc_sort_mode { |
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ADC_DECREMENT = 0, |
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ADC_INCREMENT, |
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}; |
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|
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#include "thermal_hwmon.h" |
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|
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/** |
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* The max sensors is two in rockchip SoCs. |
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* Two sensors: CPU and GPU sensor. |
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*/ |
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#define SOC_MAX_SENSORS 2 |
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|
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/** |
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* struct chip_tsadc_table - hold information about chip-specific differences |
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* @id: conversion table |
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* @length: size of conversion table |
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* @data_mask: mask to apply on data inputs |
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* @mode: sort mode of this adc variant (incrementing or decrementing) |
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*/ |
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struct chip_tsadc_table { |
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const struct tsadc_table *id; |
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unsigned int length; |
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u32 data_mask; |
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enum adc_sort_mode mode; |
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}; |
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|
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/** |
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* struct rockchip_tsadc_chip - hold the private data of tsadc chip |
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* @chn_id: array of sensor ids of chip corresponding to the channel |
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* @chn_num: the channel number of tsadc chip |
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* @tshut_temp: the hardware-controlled shutdown temperature value |
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* @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) |
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* @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) |
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* @initialize: SoC special initialize tsadc controller method |
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* @irq_ack: clear the interrupt |
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* @control: enable/disable method for the tsadc controller |
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* @get_temp: get the temperature |
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* @set_alarm_temp: set the high temperature interrupt |
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* @set_tshut_temp: set the hardware-controlled shutdown temperature |
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* @set_tshut_mode: set the hardware-controlled shutdown mode |
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* @table: the chip-specific conversion table |
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*/ |
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struct rockchip_tsadc_chip { |
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/* The sensor id of chip correspond to the ADC channel */ |
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int chn_id[SOC_MAX_SENSORS]; |
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int chn_num; |
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|
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/* The hardware-controlled tshut property */ |
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int tshut_temp; |
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enum tshut_mode tshut_mode; |
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enum tshut_polarity tshut_polarity; |
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|
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/* Chip-wide methods */ |
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void (*initialize)(struct regmap *grf, |
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void __iomem *reg, enum tshut_polarity p); |
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void (*irq_ack)(void __iomem *reg); |
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void (*control)(void __iomem *reg, bool on); |
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|
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/* Per-sensor methods */ |
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int (*get_temp)(const struct chip_tsadc_table *table, |
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int chn, void __iomem *reg, int *temp); |
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int (*set_alarm_temp)(const struct chip_tsadc_table *table, |
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int chn, void __iomem *reg, int temp); |
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int (*set_tshut_temp)(const struct chip_tsadc_table *table, |
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int chn, void __iomem *reg, int temp); |
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void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); |
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|
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/* Per-table methods */ |
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struct chip_tsadc_table table; |
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}; |
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|
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/** |
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* struct rockchip_thermal_sensor - hold the information of thermal sensor |
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* @thermal: pointer to the platform/configuration data |
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* @tzd: pointer to a thermal zone |
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* @id: identifier of the thermal sensor |
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*/ |
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struct rockchip_thermal_sensor { |
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struct rockchip_thermal_data *thermal; |
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struct thermal_zone_device *tzd; |
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int id; |
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}; |
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|
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/** |
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* struct rockchip_thermal_data - hold the private data of thermal driver |
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* @chip: pointer to the platform/configuration data |
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* @pdev: platform device of thermal |
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* @reset: the reset controller of tsadc |
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* @sensors: array of thermal sensors |
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* @clk: the controller clock is divided by the exteral 24MHz |
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* @pclk: the advanced peripherals bus clock |
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* @grf: the general register file will be used to do static set by software |
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* @regs: the base address of tsadc controller |
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* @tshut_temp: the hardware-controlled shutdown temperature value |
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* @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) |
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* @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) |
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*/ |
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struct rockchip_thermal_data { |
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const struct rockchip_tsadc_chip *chip; |
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struct platform_device *pdev; |
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struct reset_control *reset; |
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|
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struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS]; |
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|
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struct clk *clk; |
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struct clk *pclk; |
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|
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struct regmap *grf; |
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void __iomem *regs; |
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|
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int tshut_temp; |
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enum tshut_mode tshut_mode; |
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enum tshut_polarity tshut_polarity; |
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}; |
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|
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/** |
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* TSADC Sensor Register description: |
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* |
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* TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it. |
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* TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399) |
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* |
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*/ |
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#define TSADCV2_USER_CON 0x00 |
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#define TSADCV2_AUTO_CON 0x04 |
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#define TSADCV2_INT_EN 0x08 |
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#define TSADCV2_INT_PD 0x0c |
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#define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) |
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#define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) |
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#define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) |
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#define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 |
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#define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 |
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#define TSADCV2_AUTO_PERIOD 0x68 |
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#define TSADCV2_AUTO_PERIOD_HT 0x6c |
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|
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#define TSADCV2_AUTO_EN BIT(0) |
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#define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) |
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#define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) |
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|
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#define TSADCV3_AUTO_Q_SEL_EN BIT(1) |
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|
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#define TSADCV2_INT_SRC_EN(chn) BIT(chn) |
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#define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) |
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#define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) |
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#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) |
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#define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) |
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#define TSADCV2_DATA_MASK 0xfff |
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#define TSADCV3_DATA_MASK 0x3ff |
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#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 |
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#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 |
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#define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */ |
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#define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */ |
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#define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */ |
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#define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */ |
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|
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#define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */ |
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#define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ |
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|
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#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ |
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#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ |
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|
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#define GRF_SARADC_TESTBIT 0x0e644 |
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#define GRF_TSADC_TESTBIT_L 0x0e648 |
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#define GRF_TSADC_TESTBIT_H 0x0e64c |
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#define PX30_GRF_SOC_CON2 0x0408 |
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#define RK3568_GRF_TSADC_CON 0x0600 |
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#define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) |
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#define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) |
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#define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2) |
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#define RK3568_GRF_TSADC_TSEN (0x10001 << 8) |
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#define GRF_SARADC_TESTBIT_ON (0x10001 << 2) |
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#define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) |
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#define GRF_TSADC_VCM_EN_L (0x10001 << 7) |
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#define GRF_TSADC_VCM_EN_H (0x10001 << 7) |
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#define GRF_CON_TSADC_CH_INV (0x10001 << 1) |
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/** |
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* struct tsadc_table - code to temperature conversion table |
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* @code: the value of adc channel |
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* @temp: the temperature |
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* Note: |
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* code to temperature mapping of the temperature sensor is a piece wise linear |
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* curve.Any temperature, code faling between to 2 give temperatures can be |
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* linearly interpolated. |
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* Code to Temperature mapping should be updated based on manufacturer results. |
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*/ |
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struct tsadc_table { |
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u32 code; |
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int temp; |
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}; |
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|
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static const struct tsadc_table rv1108_table[] = { |
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{0, -40000}, |
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{374, -40000}, |
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{382, -35000}, |
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{389, -30000}, |
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{397, -25000}, |
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{405, -20000}, |
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{413, -15000}, |
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{421, -10000}, |
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{429, -5000}, |
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{436, 0}, |
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{444, 5000}, |
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{452, 10000}, |
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{460, 15000}, |
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{468, 20000}, |
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{476, 25000}, |
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{483, 30000}, |
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{491, 35000}, |
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{499, 40000}, |
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{507, 45000}, |
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{515, 50000}, |
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{523, 55000}, |
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{531, 60000}, |
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{539, 65000}, |
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{547, 70000}, |
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{555, 75000}, |
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{562, 80000}, |
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{570, 85000}, |
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{578, 90000}, |
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{586, 95000}, |
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{594, 100000}, |
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{602, 105000}, |
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{610, 110000}, |
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{618, 115000}, |
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{626, 120000}, |
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{634, 125000}, |
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{TSADCV2_DATA_MASK, 125000}, |
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}; |
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static const struct tsadc_table rk3228_code_table[] = { |
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{0, -40000}, |
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{588, -40000}, |
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{593, -35000}, |
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{598, -30000}, |
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{603, -25000}, |
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{608, -20000}, |
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{613, -15000}, |
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{618, -10000}, |
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{623, -5000}, |
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{629, 0}, |
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{634, 5000}, |
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{639, 10000}, |
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{644, 15000}, |
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{649, 20000}, |
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{654, 25000}, |
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{660, 30000}, |
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{665, 35000}, |
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{670, 40000}, |
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{675, 45000}, |
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{681, 50000}, |
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{686, 55000}, |
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{691, 60000}, |
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{696, 65000}, |
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{702, 70000}, |
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{707, 75000}, |
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{712, 80000}, |
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{717, 85000}, |
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{723, 90000}, |
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{728, 95000}, |
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{733, 100000}, |
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{738, 105000}, |
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{744, 110000}, |
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{749, 115000}, |
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{754, 120000}, |
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{760, 125000}, |
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{TSADCV2_DATA_MASK, 125000}, |
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}; |
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|
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static const struct tsadc_table rk3288_code_table[] = { |
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{TSADCV2_DATA_MASK, -40000}, |
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{3800, -40000}, |
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{3792, -35000}, |
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{3783, -30000}, |
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{3774, -25000}, |
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{3765, -20000}, |
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{3756, -15000}, |
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{3747, -10000}, |
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{3737, -5000}, |
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{3728, 0}, |
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{3718, 5000}, |
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{3708, 10000}, |
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{3698, 15000}, |
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{3688, 20000}, |
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{3678, 25000}, |
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{3667, 30000}, |
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{3656, 35000}, |
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{3645, 40000}, |
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{3634, 45000}, |
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{3623, 50000}, |
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{3611, 55000}, |
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{3600, 60000}, |
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{3588, 65000}, |
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{3575, 70000}, |
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{3563, 75000}, |
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{3550, 80000}, |
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{3537, 85000}, |
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{3524, 90000}, |
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{3510, 95000}, |
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{3496, 100000}, |
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{3482, 105000}, |
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{3467, 110000}, |
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{3452, 115000}, |
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{3437, 120000}, |
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{3421, 125000}, |
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{0, 125000}, |
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}; |
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|
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static const struct tsadc_table rk3328_code_table[] = { |
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{0, -40000}, |
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{296, -40000}, |
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{304, -35000}, |
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{313, -30000}, |
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{331, -20000}, |
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{340, -15000}, |
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{349, -10000}, |
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{359, -5000}, |
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{368, 0}, |
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{378, 5000}, |
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{388, 10000}, |
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{398, 15000}, |
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{408, 20000}, |
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{418, 25000}, |
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{429, 30000}, |
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{440, 35000}, |
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{451, 40000}, |
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{462, 45000}, |
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{473, 50000}, |
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{485, 55000}, |
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{496, 60000}, |
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{508, 65000}, |
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{521, 70000}, |
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{533, 75000}, |
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{546, 80000}, |
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{559, 85000}, |
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{572, 90000}, |
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{586, 95000}, |
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{600, 100000}, |
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{614, 105000}, |
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{629, 110000}, |
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{644, 115000}, |
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{659, 120000}, |
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{675, 125000}, |
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{TSADCV2_DATA_MASK, 125000}, |
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}; |
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|
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static const struct tsadc_table rk3368_code_table[] = { |
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{0, -40000}, |
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{106, -40000}, |
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{108, -35000}, |
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{110, -30000}, |
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{112, -25000}, |
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{114, -20000}, |
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{116, -15000}, |
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{118, -10000}, |
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{120, -5000}, |
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{122, 0}, |
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{124, 5000}, |
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{126, 10000}, |
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{128, 15000}, |
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{130, 20000}, |
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{132, 25000}, |
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{134, 30000}, |
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{136, 35000}, |
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{138, 40000}, |
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{140, 45000}, |
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{142, 50000}, |
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{144, 55000}, |
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{146, 60000}, |
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{148, 65000}, |
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{150, 70000}, |
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{152, 75000}, |
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{154, 80000}, |
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{156, 85000}, |
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{158, 90000}, |
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{160, 95000}, |
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{162, 100000}, |
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{163, 105000}, |
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{165, 110000}, |
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{167, 115000}, |
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{169, 120000}, |
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{171, 125000}, |
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{TSADCV3_DATA_MASK, 125000}, |
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}; |
|
|
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static const struct tsadc_table rk3399_code_table[] = { |
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{0, -40000}, |
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{402, -40000}, |
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{410, -35000}, |
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{419, -30000}, |
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{427, -25000}, |
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{436, -20000}, |
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{444, -15000}, |
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{453, -10000}, |
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{461, -5000}, |
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{470, 0}, |
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{478, 5000}, |
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{487, 10000}, |
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{496, 15000}, |
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{504, 20000}, |
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{513, 25000}, |
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{521, 30000}, |
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{530, 35000}, |
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{538, 40000}, |
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{547, 45000}, |
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{555, 50000}, |
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{564, 55000}, |
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{573, 60000}, |
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{581, 65000}, |
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{590, 70000}, |
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{599, 75000}, |
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{607, 80000}, |
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{616, 85000}, |
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{624, 90000}, |
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{633, 95000}, |
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{642, 100000}, |
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{650, 105000}, |
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{659, 110000}, |
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{668, 115000}, |
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{677, 120000}, |
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{685, 125000}, |
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{TSADCV3_DATA_MASK, 125000}, |
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}; |
|
|
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static const struct tsadc_table rk3568_code_table[] = { |
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{0, -40000}, |
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{1584, -40000}, |
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{1620, -35000}, |
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{1652, -30000}, |
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{1688, -25000}, |
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{1720, -20000}, |
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{1756, -15000}, |
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{1788, -10000}, |
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{1824, -5000}, |
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{1856, 0}, |
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{1892, 5000}, |
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{1924, 10000}, |
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{1956, 15000}, |
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{1992, 20000}, |
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{2024, 25000}, |
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{2060, 30000}, |
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{2092, 35000}, |
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{2128, 40000}, |
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{2160, 45000}, |
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{2196, 50000}, |
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{2228, 55000}, |
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{2264, 60000}, |
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{2300, 65000}, |
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{2332, 70000}, |
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{2368, 75000}, |
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{2400, 80000}, |
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{2436, 85000}, |
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{2468, 90000}, |
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{2500, 95000}, |
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{2536, 100000}, |
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{2572, 105000}, |
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{2604, 110000}, |
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{2636, 115000}, |
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{2672, 120000}, |
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{2704, 125000}, |
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{TSADCV2_DATA_MASK, 125000}, |
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}; |
|
|
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static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table, |
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int temp) |
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{ |
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int high, low, mid; |
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unsigned long num; |
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unsigned int denom; |
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u32 error = table->data_mask; |
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|
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low = 0; |
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high = (table->length - 1) - 1; /* ignore the last check for table */ |
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mid = (high + low) / 2; |
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|
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/* Return mask code data when the temp is over table range */ |
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if (temp < table->id[low].temp || temp > table->id[high].temp) |
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goto exit; |
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|
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while (low <= high) { |
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if (temp == table->id[mid].temp) |
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return table->id[mid].code; |
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else if (temp < table->id[mid].temp) |
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high = mid - 1; |
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else |
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low = mid + 1; |
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mid = (low + high) / 2; |
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} |
|
|
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/* |
|
* The conversion code granularity provided by the table. Let's |
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* assume that the relationship between temperature and |
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* analog value between 2 table entries is linear and interpolate |
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* to produce less granular result. |
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*/ |
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num = abs(table->id[mid + 1].code - table->id[mid].code); |
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num *= temp - table->id[mid].temp; |
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denom = table->id[mid + 1].temp - table->id[mid].temp; |
|
|
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switch (table->mode) { |
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case ADC_DECREMENT: |
|
return table->id[mid].code - (num / denom); |
|
case ADC_INCREMENT: |
|
return table->id[mid].code + (num / denom); |
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default: |
|
pr_err("%s: unknown table mode: %d\n", __func__, table->mode); |
|
return error; |
|
} |
|
|
|
exit: |
|
pr_err("%s: invalid temperature, temp=%d error=%d\n", |
|
__func__, temp, error); |
|
return error; |
|
} |
|
|
|
static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table, |
|
u32 code, int *temp) |
|
{ |
|
unsigned int low = 1; |
|
unsigned int high = table->length - 1; |
|
unsigned int mid = (low + high) / 2; |
|
unsigned int num; |
|
unsigned long denom; |
|
|
|
WARN_ON(table->length < 2); |
|
|
|
switch (table->mode) { |
|
case ADC_DECREMENT: |
|
code &= table->data_mask; |
|
if (code <= table->id[high].code) |
|
return -EAGAIN; /* Incorrect reading */ |
|
|
|
while (low <= high) { |
|
if (code >= table->id[mid].code && |
|
code < table->id[mid - 1].code) |
|
break; |
|
else if (code < table->id[mid].code) |
|
low = mid + 1; |
|
else |
|
high = mid - 1; |
|
|
|
mid = (low + high) / 2; |
|
} |
|
break; |
|
case ADC_INCREMENT: |
|
code &= table->data_mask; |
|
if (code < table->id[low].code) |
|
return -EAGAIN; /* Incorrect reading */ |
|
|
|
while (low <= high) { |
|
if (code <= table->id[mid].code && |
|
code > table->id[mid - 1].code) |
|
break; |
|
else if (code > table->id[mid].code) |
|
low = mid + 1; |
|
else |
|
high = mid - 1; |
|
|
|
mid = (low + high) / 2; |
|
} |
|
break; |
|
default: |
|
pr_err("%s: unknown table mode: %d\n", __func__, table->mode); |
|
return -EINVAL; |
|
} |
|
|
|
/* |
|
* The 5C granularity provided by the table is too much. Let's |
|
* assume that the relationship between sensor readings and |
|
* temperature between 2 table entries is linear and interpolate |
|
* to produce less granular result. |
|
*/ |
|
num = table->id[mid].temp - table->id[mid - 1].temp; |
|
num *= abs(table->id[mid - 1].code - code); |
|
denom = abs(table->id[mid - 1].code - table->id[mid].code); |
|
*temp = table->id[mid - 1].temp + (num / denom); |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* rk_tsadcv2_initialize - initialize TASDC Controller. |
|
* @grf: the general register file will be used to do static set by software |
|
* @regs: the base address of tsadc controller |
|
* @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) |
|
* |
|
* (1) Set TSADC_V2_AUTO_PERIOD: |
|
* Configure the interleave between every two accessing of |
|
* TSADC in normal operation. |
|
* |
|
* (2) Set TSADCV2_AUTO_PERIOD_HT: |
|
* Configure the interleave between every two accessing of |
|
* TSADC after the temperature is higher than COM_SHUT or COM_INT. |
|
* |
|
* (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: |
|
* If the temperature is higher than COMP_INT or COMP_SHUT for |
|
* "debounce" times, TSADC controller will generate interrupt or TSHUT. |
|
*/ |
|
static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs, |
|
enum tshut_polarity tshut_polarity) |
|
{ |
|
if (tshut_polarity == TSHUT_HIGH_ACTIVE) |
|
writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
|
regs + TSADCV2_AUTO_CON); |
|
else |
|
writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
|
regs + TSADCV2_AUTO_CON); |
|
|
|
writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); |
|
writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, |
|
regs + TSADCV2_HIGHT_INT_DEBOUNCE); |
|
writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, |
|
regs + TSADCV2_AUTO_PERIOD_HT); |
|
writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, |
|
regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); |
|
} |
|
|
|
/** |
|
* rk_tsadcv3_initialize - initialize TASDC Controller. |
|
* @grf: the general register file will be used to do static set by software |
|
* @regs: the base address of tsadc controller |
|
* @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) |
|
* |
|
* (1) The tsadc control power sequence. |
|
* |
|
* (2) Set TSADC_V2_AUTO_PERIOD: |
|
* Configure the interleave between every two accessing of |
|
* TSADC in normal operation. |
|
* |
|
* (2) Set TSADCV2_AUTO_PERIOD_HT: |
|
* Configure the interleave between every two accessing of |
|
* TSADC after the temperature is higher than COM_SHUT or COM_INT. |
|
* |
|
* (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: |
|
* If the temperature is higher than COMP_INT or COMP_SHUT for |
|
* "debounce" times, TSADC controller will generate interrupt or TSHUT. |
|
*/ |
|
static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs, |
|
enum tshut_polarity tshut_polarity) |
|
{ |
|
/* The tsadc control power sequence */ |
|
if (IS_ERR(grf)) { |
|
/* Set interleave value to workround ic time sync issue */ |
|
writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs + |
|
TSADCV2_USER_CON); |
|
|
|
writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, |
|
regs + TSADCV2_AUTO_PERIOD); |
|
writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, |
|
regs + TSADCV2_HIGHT_INT_DEBOUNCE); |
|
writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, |
|
regs + TSADCV2_AUTO_PERIOD_HT); |
|
writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, |
|
regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); |
|
|
|
} else { |
|
/* Enable the voltage common mode feature */ |
|
regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L); |
|
regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H); |
|
|
|
usleep_range(15, 100); /* The spec note says at least 15 us */ |
|
regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON); |
|
regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON); |
|
usleep_range(90, 200); /* The spec note says at least 90 us */ |
|
|
|
writel_relaxed(TSADCV3_AUTO_PERIOD_TIME, |
|
regs + TSADCV2_AUTO_PERIOD); |
|
writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, |
|
regs + TSADCV2_HIGHT_INT_DEBOUNCE); |
|
writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME, |
|
regs + TSADCV2_AUTO_PERIOD_HT); |
|
writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, |
|
regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); |
|
} |
|
|
|
if (tshut_polarity == TSHUT_HIGH_ACTIVE) |
|
writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
|
regs + TSADCV2_AUTO_CON); |
|
else |
|
writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
|
regs + TSADCV2_AUTO_CON); |
|
} |
|
|
|
static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs, |
|
enum tshut_polarity tshut_polarity) |
|
{ |
|
rk_tsadcv2_initialize(grf, regs, tshut_polarity); |
|
regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV); |
|
} |
|
|
|
static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs, |
|
enum tshut_polarity tshut_polarity) |
|
{ |
|
writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON); |
|
writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); |
|
writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, |
|
regs + TSADCV2_HIGHT_INT_DEBOUNCE); |
|
writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME, |
|
regs + TSADCV2_AUTO_PERIOD_HT); |
|
writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, |
|
regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); |
|
|
|
if (tshut_polarity == TSHUT_HIGH_ACTIVE) |
|
writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
|
regs + TSADCV2_AUTO_CON); |
|
else |
|
writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
|
regs + TSADCV2_AUTO_CON); |
|
|
|
/* |
|
* The general register file will is optional |
|
* and might not be available. |
|
*/ |
|
if (!IS_ERR(grf)) { |
|
regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN); |
|
/* |
|
* RK3568 TRM, section 18.5. requires a delay no less |
|
* than 10us between the rising edge of tsadc_tsen_en |
|
* and the rising edge of tsadc_ana_reg_0/1/2. |
|
*/ |
|
udelay(15); |
|
regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0); |
|
regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1); |
|
regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2); |
|
|
|
/* |
|
* RK3568 TRM, section 18.5. requires a delay no less |
|
* than 90us after the rising edge of tsadc_ana_reg_0/1/2. |
|
*/ |
|
usleep_range(100, 200); |
|
} |
|
} |
|
|
|
static void rk_tsadcv2_irq_ack(void __iomem *regs) |
|
{ |
|
u32 val; |
|
|
|
val = readl_relaxed(regs + TSADCV2_INT_PD); |
|
writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); |
|
} |
|
|
|
static void rk_tsadcv3_irq_ack(void __iomem *regs) |
|
{ |
|
u32 val; |
|
|
|
val = readl_relaxed(regs + TSADCV2_INT_PD); |
|
writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); |
|
} |
|
|
|
static void rk_tsadcv2_control(void __iomem *regs, bool enable) |
|
{ |
|
u32 val; |
|
|
|
val = readl_relaxed(regs + TSADCV2_AUTO_CON); |
|
if (enable) |
|
val |= TSADCV2_AUTO_EN; |
|
else |
|
val &= ~TSADCV2_AUTO_EN; |
|
|
|
writel_relaxed(val, regs + TSADCV2_AUTO_CON); |
|
} |
|
|
|
/** |
|
* rk_tsadcv3_control - the tsadc controller is enabled or disabled. |
|
* @regs: the base address of tsadc controller |
|
* @enable: boolean flag to enable the controller |
|
* |
|
* NOTE: TSADC controller works at auto mode, and some SoCs need set the |
|
* tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output |
|
* adc value if setting this bit to enable. |
|
*/ |
|
static void rk_tsadcv3_control(void __iomem *regs, bool enable) |
|
{ |
|
u32 val; |
|
|
|
val = readl_relaxed(regs + TSADCV2_AUTO_CON); |
|
if (enable) |
|
val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; |
|
else |
|
val &= ~TSADCV2_AUTO_EN; |
|
|
|
writel_relaxed(val, regs + TSADCV2_AUTO_CON); |
|
} |
|
|
|
static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table, |
|
int chn, void __iomem *regs, int *temp) |
|
{ |
|
u32 val; |
|
|
|
val = readl_relaxed(regs + TSADCV2_DATA(chn)); |
|
|
|
return rk_tsadcv2_code_to_temp(table, val, temp); |
|
} |
|
|
|
static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table, |
|
int chn, void __iomem *regs, int temp) |
|
{ |
|
u32 alarm_value; |
|
u32 int_en, int_clr; |
|
|
|
/* |
|
* In some cases, some sensors didn't need the trip points, the |
|
* set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm |
|
* in the end, ignore this case and disable the high temperature |
|
* interrupt. |
|
*/ |
|
if (temp == INT_MAX) { |
|
int_clr = readl_relaxed(regs + TSADCV2_INT_EN); |
|
int_clr &= ~TSADCV2_INT_SRC_EN(chn); |
|
writel_relaxed(int_clr, regs + TSADCV2_INT_EN); |
|
return 0; |
|
} |
|
|
|
/* Make sure the value is valid */ |
|
alarm_value = rk_tsadcv2_temp_to_code(table, temp); |
|
if (alarm_value == table->data_mask) |
|
return -ERANGE; |
|
|
|
writel_relaxed(alarm_value & table->data_mask, |
|
regs + TSADCV2_COMP_INT(chn)); |
|
|
|
int_en = readl_relaxed(regs + TSADCV2_INT_EN); |
|
int_en |= TSADCV2_INT_SRC_EN(chn); |
|
writel_relaxed(int_en, regs + TSADCV2_INT_EN); |
|
|
|
return 0; |
|
} |
|
|
|
static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table, |
|
int chn, void __iomem *regs, int temp) |
|
{ |
|
u32 tshut_value, val; |
|
|
|
/* Make sure the value is valid */ |
|
tshut_value = rk_tsadcv2_temp_to_code(table, temp); |
|
if (tshut_value == table->data_mask) |
|
return -ERANGE; |
|
|
|
writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn)); |
|
|
|
/* TSHUT will be valid */ |
|
val = readl_relaxed(regs + TSADCV2_AUTO_CON); |
|
writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON); |
|
|
|
return 0; |
|
} |
|
|
|
static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, |
|
enum tshut_mode mode) |
|
{ |
|
u32 val; |
|
|
|
val = readl_relaxed(regs + TSADCV2_INT_EN); |
|
if (mode == TSHUT_MODE_GPIO) { |
|
val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); |
|
val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); |
|
} else { |
|
val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); |
|
val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); |
|
} |
|
|
|
writel_relaxed(val, regs + TSADCV2_INT_EN); |
|
} |
|
|
|
static const struct rockchip_tsadc_chip px30_tsadc_data = { |
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
|
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ |
|
.chn_num = 2, /* 2 channels for tsadc */ |
|
|
|
.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ |
|
.tshut_temp = 95000, |
|
|
|
.initialize = rk_tsadcv4_initialize, |
|
.irq_ack = rk_tsadcv3_irq_ack, |
|
.control = rk_tsadcv3_control, |
|
.get_temp = rk_tsadcv2_get_temp, |
|
.set_alarm_temp = rk_tsadcv2_alarm_temp, |
|
.set_tshut_temp = rk_tsadcv2_tshut_temp, |
|
.set_tshut_mode = rk_tsadcv2_tshut_mode, |
|
|
|
.table = { |
|
.id = rk3328_code_table, |
|
.length = ARRAY_SIZE(rk3328_code_table), |
|
.data_mask = TSADCV2_DATA_MASK, |
|
.mode = ADC_INCREMENT, |
|
}, |
|
}; |
|
|
|
static const struct rockchip_tsadc_chip rv1108_tsadc_data = { |
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
|
.chn_num = 1, /* one channel for tsadc */ |
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ |
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ |
|
.tshut_temp = 95000, |
|
|
|
.initialize = rk_tsadcv2_initialize, |
|
.irq_ack = rk_tsadcv3_irq_ack, |
|
.control = rk_tsadcv3_control, |
|
.get_temp = rk_tsadcv2_get_temp, |
|
.set_alarm_temp = rk_tsadcv2_alarm_temp, |
|
.set_tshut_temp = rk_tsadcv2_tshut_temp, |
|
.set_tshut_mode = rk_tsadcv2_tshut_mode, |
|
|
|
.table = { |
|
.id = rv1108_table, |
|
.length = ARRAY_SIZE(rv1108_table), |
|
.data_mask = TSADCV2_DATA_MASK, |
|
.mode = ADC_INCREMENT, |
|
}, |
|
}; |
|
|
|
static const struct rockchip_tsadc_chip rk3228_tsadc_data = { |
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
|
.chn_num = 1, /* one channel for tsadc */ |
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ |
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ |
|
.tshut_temp = 95000, |
|
|
|
.initialize = rk_tsadcv2_initialize, |
|
.irq_ack = rk_tsadcv3_irq_ack, |
|
.control = rk_tsadcv3_control, |
|
.get_temp = rk_tsadcv2_get_temp, |
|
.set_alarm_temp = rk_tsadcv2_alarm_temp, |
|
.set_tshut_temp = rk_tsadcv2_tshut_temp, |
|
.set_tshut_mode = rk_tsadcv2_tshut_mode, |
|
|
|
.table = { |
|
.id = rk3228_code_table, |
|
.length = ARRAY_SIZE(rk3228_code_table), |
|
.data_mask = TSADCV3_DATA_MASK, |
|
.mode = ADC_INCREMENT, |
|
}, |
|
}; |
|
|
|
static const struct rockchip_tsadc_chip rk3288_tsadc_data = { |
|
.chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ |
|
.chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ |
|
.chn_num = 2, /* two channels for tsadc */ |
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ |
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ |
|
.tshut_temp = 95000, |
|
|
|
.initialize = rk_tsadcv2_initialize, |
|
.irq_ack = rk_tsadcv2_irq_ack, |
|
.control = rk_tsadcv2_control, |
|
.get_temp = rk_tsadcv2_get_temp, |
|
.set_alarm_temp = rk_tsadcv2_alarm_temp, |
|
.set_tshut_temp = rk_tsadcv2_tshut_temp, |
|
.set_tshut_mode = rk_tsadcv2_tshut_mode, |
|
|
|
.table = { |
|
.id = rk3288_code_table, |
|
.length = ARRAY_SIZE(rk3288_code_table), |
|
.data_mask = TSADCV2_DATA_MASK, |
|
.mode = ADC_DECREMENT, |
|
}, |
|
}; |
|
|
|
static const struct rockchip_tsadc_chip rk3328_tsadc_data = { |
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
|
.chn_num = 1, /* one channels for tsadc */ |
|
|
|
.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ |
|
.tshut_temp = 95000, |
|
|
|
.initialize = rk_tsadcv2_initialize, |
|
.irq_ack = rk_tsadcv3_irq_ack, |
|
.control = rk_tsadcv3_control, |
|
.get_temp = rk_tsadcv2_get_temp, |
|
.set_alarm_temp = rk_tsadcv2_alarm_temp, |
|
.set_tshut_temp = rk_tsadcv2_tshut_temp, |
|
.set_tshut_mode = rk_tsadcv2_tshut_mode, |
|
|
|
.table = { |
|
.id = rk3328_code_table, |
|
.length = ARRAY_SIZE(rk3328_code_table), |
|
.data_mask = TSADCV2_DATA_MASK, |
|
.mode = ADC_INCREMENT, |
|
}, |
|
}; |
|
|
|
static const struct rockchip_tsadc_chip rk3366_tsadc_data = { |
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
|
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ |
|
.chn_num = 2, /* two channels for tsadc */ |
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ |
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ |
|
.tshut_temp = 95000, |
|
|
|
.initialize = rk_tsadcv3_initialize, |
|
.irq_ack = rk_tsadcv3_irq_ack, |
|
.control = rk_tsadcv3_control, |
|
.get_temp = rk_tsadcv2_get_temp, |
|
.set_alarm_temp = rk_tsadcv2_alarm_temp, |
|
.set_tshut_temp = rk_tsadcv2_tshut_temp, |
|
.set_tshut_mode = rk_tsadcv2_tshut_mode, |
|
|
|
.table = { |
|
.id = rk3228_code_table, |
|
.length = ARRAY_SIZE(rk3228_code_table), |
|
.data_mask = TSADCV3_DATA_MASK, |
|
.mode = ADC_INCREMENT, |
|
}, |
|
}; |
|
|
|
static const struct rockchip_tsadc_chip rk3368_tsadc_data = { |
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
|
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ |
|
.chn_num = 2, /* two channels for tsadc */ |
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ |
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ |
|
.tshut_temp = 95000, |
|
|
|
.initialize = rk_tsadcv2_initialize, |
|
.irq_ack = rk_tsadcv2_irq_ack, |
|
.control = rk_tsadcv2_control, |
|
.get_temp = rk_tsadcv2_get_temp, |
|
.set_alarm_temp = rk_tsadcv2_alarm_temp, |
|
.set_tshut_temp = rk_tsadcv2_tshut_temp, |
|
.set_tshut_mode = rk_tsadcv2_tshut_mode, |
|
|
|
.table = { |
|
.id = rk3368_code_table, |
|
.length = ARRAY_SIZE(rk3368_code_table), |
|
.data_mask = TSADCV3_DATA_MASK, |
|
.mode = ADC_INCREMENT, |
|
}, |
|
}; |
|
|
|
static const struct rockchip_tsadc_chip rk3399_tsadc_data = { |
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
|
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ |
|
.chn_num = 2, /* two channels for tsadc */ |
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ |
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ |
|
.tshut_temp = 95000, |
|
|
|
.initialize = rk_tsadcv3_initialize, |
|
.irq_ack = rk_tsadcv3_irq_ack, |
|
.control = rk_tsadcv3_control, |
|
.get_temp = rk_tsadcv2_get_temp, |
|
.set_alarm_temp = rk_tsadcv2_alarm_temp, |
|
.set_tshut_temp = rk_tsadcv2_tshut_temp, |
|
.set_tshut_mode = rk_tsadcv2_tshut_mode, |
|
|
|
.table = { |
|
.id = rk3399_code_table, |
|
.length = ARRAY_SIZE(rk3399_code_table), |
|
.data_mask = TSADCV3_DATA_MASK, |
|
.mode = ADC_INCREMENT, |
|
}, |
|
}; |
|
|
|
static const struct rockchip_tsadc_chip rk3568_tsadc_data = { |
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
|
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ |
|
.chn_num = 2, /* two channels for tsadc */ |
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ |
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ |
|
.tshut_temp = 95000, |
|
|
|
.initialize = rk_tsadcv7_initialize, |
|
.irq_ack = rk_tsadcv3_irq_ack, |
|
.control = rk_tsadcv3_control, |
|
.get_temp = rk_tsadcv2_get_temp, |
|
.set_alarm_temp = rk_tsadcv2_alarm_temp, |
|
.set_tshut_temp = rk_tsadcv2_tshut_temp, |
|
.set_tshut_mode = rk_tsadcv2_tshut_mode, |
|
|
|
.table = { |
|
.id = rk3568_code_table, |
|
.length = ARRAY_SIZE(rk3568_code_table), |
|
.data_mask = TSADCV2_DATA_MASK, |
|
.mode = ADC_INCREMENT, |
|
}, |
|
}; |
|
|
|
static const struct of_device_id of_rockchip_thermal_match[] = { |
|
{ .compatible = "rockchip,px30-tsadc", |
|
.data = (void *)&px30_tsadc_data, |
|
}, |
|
{ |
|
.compatible = "rockchip,rv1108-tsadc", |
|
.data = (void *)&rv1108_tsadc_data, |
|
}, |
|
{ |
|
.compatible = "rockchip,rk3228-tsadc", |
|
.data = (void *)&rk3228_tsadc_data, |
|
}, |
|
{ |
|
.compatible = "rockchip,rk3288-tsadc", |
|
.data = (void *)&rk3288_tsadc_data, |
|
}, |
|
{ |
|
.compatible = "rockchip,rk3328-tsadc", |
|
.data = (void *)&rk3328_tsadc_data, |
|
}, |
|
{ |
|
.compatible = "rockchip,rk3366-tsadc", |
|
.data = (void *)&rk3366_tsadc_data, |
|
}, |
|
{ |
|
.compatible = "rockchip,rk3368-tsadc", |
|
.data = (void *)&rk3368_tsadc_data, |
|
}, |
|
{ |
|
.compatible = "rockchip,rk3399-tsadc", |
|
.data = (void *)&rk3399_tsadc_data, |
|
}, |
|
{ |
|
.compatible = "rockchip,rk3568-tsadc", |
|
.data = (void *)&rk3568_tsadc_data, |
|
}, |
|
{ /* end */ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); |
|
|
|
static void |
|
rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on) |
|
{ |
|
struct thermal_zone_device *tzd = sensor->tzd; |
|
|
|
if (on) |
|
thermal_zone_device_enable(tzd); |
|
else |
|
thermal_zone_device_disable(tzd); |
|
} |
|
|
|
static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev) |
|
{ |
|
struct rockchip_thermal_data *thermal = dev; |
|
int i; |
|
|
|
dev_dbg(&thermal->pdev->dev, "thermal alarm\n"); |
|
|
|
thermal->chip->irq_ack(thermal->regs); |
|
|
|
for (i = 0; i < thermal->chip->chn_num; i++) |
|
thermal_zone_device_update(thermal->sensors[i].tzd, |
|
THERMAL_EVENT_UNSPECIFIED); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static int rockchip_thermal_set_trips(void *_sensor, int low, int high) |
|
{ |
|
struct rockchip_thermal_sensor *sensor = _sensor; |
|
struct rockchip_thermal_data *thermal = sensor->thermal; |
|
const struct rockchip_tsadc_chip *tsadc = thermal->chip; |
|
|
|
dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n", |
|
__func__, sensor->id, low, high); |
|
|
|
return tsadc->set_alarm_temp(&tsadc->table, |
|
sensor->id, thermal->regs, high); |
|
} |
|
|
|
static int rockchip_thermal_get_temp(void *_sensor, int *out_temp) |
|
{ |
|
struct rockchip_thermal_sensor *sensor = _sensor; |
|
struct rockchip_thermal_data *thermal = sensor->thermal; |
|
const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip; |
|
int retval; |
|
|
|
retval = tsadc->get_temp(&tsadc->table, |
|
sensor->id, thermal->regs, out_temp); |
|
dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n", |
|
sensor->id, *out_temp, retval); |
|
|
|
return retval; |
|
} |
|
|
|
static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = { |
|
.get_temp = rockchip_thermal_get_temp, |
|
.set_trips = rockchip_thermal_set_trips, |
|
}; |
|
|
|
static int rockchip_configure_from_dt(struct device *dev, |
|
struct device_node *np, |
|
struct rockchip_thermal_data *thermal) |
|
{ |
|
u32 shut_temp, tshut_mode, tshut_polarity; |
|
|
|
if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) { |
|
dev_warn(dev, |
|
"Missing tshut temp property, using default %d\n", |
|
thermal->chip->tshut_temp); |
|
thermal->tshut_temp = thermal->chip->tshut_temp; |
|
} else { |
|
if (shut_temp > INT_MAX) { |
|
dev_err(dev, "Invalid tshut temperature specified: %d\n", |
|
shut_temp); |
|
return -ERANGE; |
|
} |
|
thermal->tshut_temp = shut_temp; |
|
} |
|
|
|
if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) { |
|
dev_warn(dev, |
|
"Missing tshut mode property, using default (%s)\n", |
|
thermal->chip->tshut_mode == TSHUT_MODE_GPIO ? |
|
"gpio" : "cru"); |
|
thermal->tshut_mode = thermal->chip->tshut_mode; |
|
} else { |
|
thermal->tshut_mode = tshut_mode; |
|
} |
|
|
|
if (thermal->tshut_mode > 1) { |
|
dev_err(dev, "Invalid tshut mode specified: %d\n", |
|
thermal->tshut_mode); |
|
return -EINVAL; |
|
} |
|
|
|
if (of_property_read_u32(np, "rockchip,hw-tshut-polarity", |
|
&tshut_polarity)) { |
|
dev_warn(dev, |
|
"Missing tshut-polarity property, using default (%s)\n", |
|
thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ? |
|
"low" : "high"); |
|
thermal->tshut_polarity = thermal->chip->tshut_polarity; |
|
} else { |
|
thermal->tshut_polarity = tshut_polarity; |
|
} |
|
|
|
if (thermal->tshut_polarity > 1) { |
|
dev_err(dev, "Invalid tshut-polarity specified: %d\n", |
|
thermal->tshut_polarity); |
|
return -EINVAL; |
|
} |
|
|
|
/* The tsadc wont to handle the error in here since some SoCs didn't |
|
* need this property. |
|
*/ |
|
thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); |
|
if (IS_ERR(thermal->grf)) |
|
dev_warn(dev, "Missing rockchip,grf property\n"); |
|
|
|
return 0; |
|
} |
|
|
|
static int |
|
rockchip_thermal_register_sensor(struct platform_device *pdev, |
|
struct rockchip_thermal_data *thermal, |
|
struct rockchip_thermal_sensor *sensor, |
|
int id) |
|
{ |
|
const struct rockchip_tsadc_chip *tsadc = thermal->chip; |
|
int error; |
|
|
|
tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); |
|
|
|
error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, |
|
thermal->tshut_temp); |
|
if (error) |
|
dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n", |
|
__func__, thermal->tshut_temp, error); |
|
|
|
sensor->thermal = thermal; |
|
sensor->id = id; |
|
sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id, |
|
sensor, &rockchip_of_thermal_ops); |
|
if (IS_ERR(sensor->tzd)) { |
|
error = PTR_ERR(sensor->tzd); |
|
dev_err(&pdev->dev, "failed to register sensor %d: %d\n", |
|
id, error); |
|
return error; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* Reset TSADC Controller, reset all tsadc registers. |
|
* @reset: the reset controller of tsadc |
|
*/ |
|
static void rockchip_thermal_reset_controller(struct reset_control *reset) |
|
{ |
|
reset_control_assert(reset); |
|
usleep_range(10, 20); |
|
reset_control_deassert(reset); |
|
} |
|
|
|
static int rockchip_thermal_probe(struct platform_device *pdev) |
|
{ |
|
struct device_node *np = pdev->dev.of_node; |
|
struct rockchip_thermal_data *thermal; |
|
const struct of_device_id *match; |
|
struct resource *res; |
|
int irq; |
|
int i; |
|
int error; |
|
|
|
match = of_match_node(of_rockchip_thermal_match, np); |
|
if (!match) |
|
return -ENXIO; |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) |
|
return -EINVAL; |
|
|
|
thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data), |
|
GFP_KERNEL); |
|
if (!thermal) |
|
return -ENOMEM; |
|
|
|
thermal->pdev = pdev; |
|
|
|
thermal->chip = (const struct rockchip_tsadc_chip *)match->data; |
|
if (!thermal->chip) |
|
return -EINVAL; |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
thermal->regs = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(thermal->regs)) |
|
return PTR_ERR(thermal->regs); |
|
|
|
thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb"); |
|
if (IS_ERR(thermal->reset)) { |
|
error = PTR_ERR(thermal->reset); |
|
dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); |
|
return error; |
|
} |
|
|
|
thermal->clk = devm_clk_get(&pdev->dev, "tsadc"); |
|
if (IS_ERR(thermal->clk)) { |
|
error = PTR_ERR(thermal->clk); |
|
dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); |
|
return error; |
|
} |
|
|
|
thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); |
|
if (IS_ERR(thermal->pclk)) { |
|
error = PTR_ERR(thermal->pclk); |
|
dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", |
|
error); |
|
return error; |
|
} |
|
|
|
error = clk_prepare_enable(thermal->clk); |
|
if (error) { |
|
dev_err(&pdev->dev, "failed to enable converter clock: %d\n", |
|
error); |
|
return error; |
|
} |
|
|
|
error = clk_prepare_enable(thermal->pclk); |
|
if (error) { |
|
dev_err(&pdev->dev, "failed to enable pclk: %d\n", error); |
|
goto err_disable_clk; |
|
} |
|
|
|
rockchip_thermal_reset_controller(thermal->reset); |
|
|
|
error = rockchip_configure_from_dt(&pdev->dev, np, thermal); |
|
if (error) { |
|
dev_err(&pdev->dev, "failed to parse device tree data: %d\n", |
|
error); |
|
goto err_disable_pclk; |
|
} |
|
|
|
thermal->chip->initialize(thermal->grf, thermal->regs, |
|
thermal->tshut_polarity); |
|
|
|
for (i = 0; i < thermal->chip->chn_num; i++) { |
|
error = rockchip_thermal_register_sensor(pdev, thermal, |
|
&thermal->sensors[i], |
|
thermal->chip->chn_id[i]); |
|
if (error) { |
|
dev_err(&pdev->dev, |
|
"failed to register sensor[%d] : error = %d\n", |
|
i, error); |
|
goto err_disable_pclk; |
|
} |
|
} |
|
|
|
error = devm_request_threaded_irq(&pdev->dev, irq, NULL, |
|
&rockchip_thermal_alarm_irq_thread, |
|
IRQF_ONESHOT, |
|
"rockchip_thermal", thermal); |
|
if (error) { |
|
dev_err(&pdev->dev, |
|
"failed to request tsadc irq: %d\n", error); |
|
goto err_disable_pclk; |
|
} |
|
|
|
thermal->chip->control(thermal->regs, true); |
|
|
|
for (i = 0; i < thermal->chip->chn_num; i++) { |
|
rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); |
|
thermal->sensors[i].tzd->tzp->no_hwmon = false; |
|
error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd); |
|
if (error) |
|
dev_warn(&pdev->dev, |
|
"failed to register sensor %d with hwmon: %d\n", |
|
i, error); |
|
} |
|
|
|
platform_set_drvdata(pdev, thermal); |
|
|
|
return 0; |
|
|
|
err_disable_pclk: |
|
clk_disable_unprepare(thermal->pclk); |
|
err_disable_clk: |
|
clk_disable_unprepare(thermal->clk); |
|
|
|
return error; |
|
} |
|
|
|
static int rockchip_thermal_remove(struct platform_device *pdev) |
|
{ |
|
struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); |
|
int i; |
|
|
|
for (i = 0; i < thermal->chip->chn_num; i++) { |
|
struct rockchip_thermal_sensor *sensor = &thermal->sensors[i]; |
|
|
|
thermal_remove_hwmon_sysfs(sensor->tzd); |
|
rockchip_thermal_toggle_sensor(sensor, false); |
|
} |
|
|
|
thermal->chip->control(thermal->regs, false); |
|
|
|
clk_disable_unprepare(thermal->pclk); |
|
clk_disable_unprepare(thermal->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused rockchip_thermal_suspend(struct device *dev) |
|
{ |
|
struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); |
|
int i; |
|
|
|
for (i = 0; i < thermal->chip->chn_num; i++) |
|
rockchip_thermal_toggle_sensor(&thermal->sensors[i], false); |
|
|
|
thermal->chip->control(thermal->regs, false); |
|
|
|
clk_disable(thermal->pclk); |
|
clk_disable(thermal->clk); |
|
|
|
pinctrl_pm_select_sleep_state(dev); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused rockchip_thermal_resume(struct device *dev) |
|
{ |
|
struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); |
|
int i; |
|
int error; |
|
|
|
error = clk_enable(thermal->clk); |
|
if (error) |
|
return error; |
|
|
|
error = clk_enable(thermal->pclk); |
|
if (error) { |
|
clk_disable(thermal->clk); |
|
return error; |
|
} |
|
|
|
rockchip_thermal_reset_controller(thermal->reset); |
|
|
|
thermal->chip->initialize(thermal->grf, thermal->regs, |
|
thermal->tshut_polarity); |
|
|
|
for (i = 0; i < thermal->chip->chn_num; i++) { |
|
int id = thermal->sensors[i].id; |
|
|
|
thermal->chip->set_tshut_mode(id, thermal->regs, |
|
thermal->tshut_mode); |
|
|
|
error = thermal->chip->set_tshut_temp(&thermal->chip->table, |
|
id, thermal->regs, |
|
thermal->tshut_temp); |
|
if (error) |
|
dev_err(dev, "%s: invalid tshut=%d, error=%d\n", |
|
__func__, thermal->tshut_temp, error); |
|
} |
|
|
|
thermal->chip->control(thermal->regs, true); |
|
|
|
for (i = 0; i < thermal->chip->chn_num; i++) |
|
rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); |
|
|
|
pinctrl_pm_select_default_state(dev); |
|
|
|
return 0; |
|
} |
|
|
|
static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops, |
|
rockchip_thermal_suspend, rockchip_thermal_resume); |
|
|
|
static struct platform_driver rockchip_thermal_driver = { |
|
.driver = { |
|
.name = "rockchip-thermal", |
|
.pm = &rockchip_thermal_pm_ops, |
|
.of_match_table = of_rockchip_thermal_match, |
|
}, |
|
.probe = rockchip_thermal_probe, |
|
.remove = rockchip_thermal_remove, |
|
}; |
|
|
|
module_platform_driver(rockchip_thermal_driver); |
|
|
|
MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver"); |
|
MODULE_AUTHOR("Rockchip, Inc."); |
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_ALIAS("platform:rockchip-thermal");
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