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284 lines
6.7 KiB
284 lines
6.7 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* COMBPHY driver for HiSilicon STB SoCs |
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* |
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* Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com |
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* |
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* Authors: Jianguo Sun <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/phy/phy.h> |
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#include <linux/regmap.h> |
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#include <linux/reset.h> |
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#include <dt-bindings/phy/phy.h> |
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#define COMBPHY_MODE_PCIE 0 |
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#define COMBPHY_MODE_USB3 1 |
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#define COMBPHY_MODE_SATA 2 |
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#define COMBPHY_CFG_REG 0x0 |
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#define COMBPHY_BYPASS_CODEC BIT(31) |
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#define COMBPHY_TEST_WRITE BIT(24) |
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#define COMBPHY_TEST_DATA_SHIFT 20 |
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#define COMBPHY_TEST_DATA_MASK GENMASK(23, 20) |
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#define COMBPHY_TEST_ADDR_SHIFT 12 |
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#define COMBPHY_TEST_ADDR_MASK GENMASK(16, 12) |
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#define COMBPHY_CLKREF_OUT_OEN BIT(0) |
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struct histb_combphy_mode { |
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int fixed; |
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int select; |
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u32 reg; |
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u32 shift; |
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u32 mask; |
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}; |
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struct histb_combphy_priv { |
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void __iomem *mmio; |
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struct regmap *syscon; |
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struct reset_control *por_rst; |
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struct clk *ref_clk; |
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struct phy *phy; |
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struct histb_combphy_mode mode; |
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}; |
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static void nano_register_write(struct histb_combphy_priv *priv, |
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u32 addr, u32 data) |
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{ |
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void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; |
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u32 val; |
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/* Set up address and data for the write */ |
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val = readl(reg); |
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val &= ~COMBPHY_TEST_ADDR_MASK; |
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val |= addr << COMBPHY_TEST_ADDR_SHIFT; |
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val &= ~COMBPHY_TEST_DATA_MASK; |
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val |= data << COMBPHY_TEST_DATA_SHIFT; |
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writel(val, reg); |
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/* Flip strobe control to trigger the write */ |
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val &= ~COMBPHY_TEST_WRITE; |
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writel(val, reg); |
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val |= COMBPHY_TEST_WRITE; |
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writel(val, reg); |
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} |
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static int is_mode_fixed(struct histb_combphy_mode *mode) |
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{ |
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return (mode->fixed != PHY_NONE) ? true : false; |
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} |
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static int histb_combphy_set_mode(struct histb_combphy_priv *priv) |
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{ |
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struct histb_combphy_mode *mode = &priv->mode; |
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struct regmap *syscon = priv->syscon; |
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u32 hw_sel; |
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if (is_mode_fixed(mode)) |
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return 0; |
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switch (mode->select) { |
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case PHY_TYPE_SATA: |
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hw_sel = COMBPHY_MODE_SATA; |
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break; |
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case PHY_TYPE_PCIE: |
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hw_sel = COMBPHY_MODE_PCIE; |
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break; |
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case PHY_TYPE_USB3: |
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hw_sel = COMBPHY_MODE_USB3; |
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break; |
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default: |
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return -EINVAL; |
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} |
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return regmap_update_bits(syscon, mode->reg, mode->mask, |
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hw_sel << mode->shift); |
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} |
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static int histb_combphy_init(struct phy *phy) |
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{ |
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struct histb_combphy_priv *priv = phy_get_drvdata(phy); |
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u32 val; |
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int ret; |
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ret = histb_combphy_set_mode(priv); |
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if (ret) |
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return ret; |
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/* Clear bypass bit to enable encoding/decoding */ |
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val = readl(priv->mmio + COMBPHY_CFG_REG); |
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val &= ~COMBPHY_BYPASS_CODEC; |
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writel(val, priv->mmio + COMBPHY_CFG_REG); |
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ret = clk_prepare_enable(priv->ref_clk); |
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if (ret) |
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return ret; |
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reset_control_deassert(priv->por_rst); |
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/* Enable EP clock */ |
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val = readl(priv->mmio + COMBPHY_CFG_REG); |
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val |= COMBPHY_CLKREF_OUT_OEN; |
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writel(val, priv->mmio + COMBPHY_CFG_REG); |
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/* Need to wait for EP clock stable */ |
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mdelay(5); |
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/* Configure nano phy registers as suggested by vendor */ |
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nano_register_write(priv, 0x1, 0x8); |
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nano_register_write(priv, 0xc, 0x9); |
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nano_register_write(priv, 0x1a, 0x4); |
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return 0; |
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} |
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static int histb_combphy_exit(struct phy *phy) |
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{ |
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struct histb_combphy_priv *priv = phy_get_drvdata(phy); |
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u32 val; |
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/* Disable EP clock */ |
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val = readl(priv->mmio + COMBPHY_CFG_REG); |
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val &= ~COMBPHY_CLKREF_OUT_OEN; |
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writel(val, priv->mmio + COMBPHY_CFG_REG); |
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reset_control_assert(priv->por_rst); |
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clk_disable_unprepare(priv->ref_clk); |
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return 0; |
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} |
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static const struct phy_ops histb_combphy_ops = { |
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.init = histb_combphy_init, |
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.exit = histb_combphy_exit, |
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.owner = THIS_MODULE, |
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}; |
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static struct phy *histb_combphy_xlate(struct device *dev, |
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struct of_phandle_args *args) |
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{ |
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struct histb_combphy_priv *priv = dev_get_drvdata(dev); |
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struct histb_combphy_mode *mode = &priv->mode; |
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if (args->args_count < 1) { |
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dev_err(dev, "invalid number of arguments\n"); |
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return ERR_PTR(-EINVAL); |
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} |
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mode->select = args->args[0]; |
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if (mode->select < PHY_TYPE_SATA || mode->select > PHY_TYPE_USB3) { |
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dev_err(dev, "invalid phy mode select argument\n"); |
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return ERR_PTR(-EINVAL); |
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} |
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if (is_mode_fixed(mode) && mode->select != mode->fixed) { |
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dev_err(dev, "mode select %d mismatch fixed phy mode %d\n", |
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mode->select, mode->fixed); |
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return ERR_PTR(-EINVAL); |
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} |
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return priv->phy; |
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} |
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static int histb_combphy_probe(struct platform_device *pdev) |
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{ |
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struct phy_provider *phy_provider; |
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struct device *dev = &pdev->dev; |
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struct histb_combphy_priv *priv; |
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struct device_node *np = dev->of_node; |
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struct histb_combphy_mode *mode; |
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u32 vals[3]; |
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int ret; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->mmio = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(priv->mmio)) { |
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ret = PTR_ERR(priv->mmio); |
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return ret; |
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} |
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priv->syscon = syscon_node_to_regmap(np->parent); |
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if (IS_ERR(priv->syscon)) { |
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dev_err(dev, "failed to find peri_ctrl syscon regmap\n"); |
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return PTR_ERR(priv->syscon); |
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} |
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mode = &priv->mode; |
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mode->fixed = PHY_NONE; |
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ret = of_property_read_u32(np, "hisilicon,fixed-mode", &mode->fixed); |
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if (ret == 0) |
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dev_dbg(dev, "found fixed phy mode %d\n", mode->fixed); |
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ret = of_property_read_u32_array(np, "hisilicon,mode-select-bits", |
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vals, ARRAY_SIZE(vals)); |
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if (ret == 0) { |
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if (is_mode_fixed(mode)) { |
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dev_err(dev, "found select bits for fixed mode phy\n"); |
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return -EINVAL; |
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} |
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mode->reg = vals[0]; |
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mode->shift = vals[1]; |
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mode->mask = vals[2]; |
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dev_dbg(dev, "found mode select bits\n"); |
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} else { |
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if (!is_mode_fixed(mode)) { |
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dev_err(dev, "no valid select bits found for non-fixed phy\n"); |
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return -ENODEV; |
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} |
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} |
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priv->ref_clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(priv->ref_clk)) { |
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dev_err(dev, "failed to find ref clock\n"); |
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return PTR_ERR(priv->ref_clk); |
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} |
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priv->por_rst = devm_reset_control_get(dev, NULL); |
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if (IS_ERR(priv->por_rst)) { |
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dev_err(dev, "failed to get poweron reset\n"); |
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return PTR_ERR(priv->por_rst); |
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} |
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priv->phy = devm_phy_create(dev, NULL, &histb_combphy_ops); |
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if (IS_ERR(priv->phy)) { |
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dev_err(dev, "failed to create combphy\n"); |
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return PTR_ERR(priv->phy); |
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} |
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dev_set_drvdata(dev, priv); |
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phy_set_drvdata(priv->phy, priv); |
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phy_provider = devm_of_phy_provider_register(dev, histb_combphy_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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} |
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static const struct of_device_id histb_combphy_of_match[] = { |
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{ .compatible = "hisilicon,hi3798cv200-combphy" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, histb_combphy_of_match); |
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static struct platform_driver histb_combphy_driver = { |
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.probe = histb_combphy_probe, |
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.driver = { |
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.name = "combphy", |
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.of_match_table = histb_combphy_of_match, |
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}, |
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}; |
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module_platform_driver(histb_combphy_driver); |
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MODULE_DESCRIPTION("HiSilicon STB COMBPHY driver"); |
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MODULE_LICENSE("GPL v2");
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