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225 lines
5.6 KiB
225 lines
5.6 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2020-21 Intel Corporation. |
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*/ |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/io.h> |
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#include <linux/io-64-nonatomic-lo-hi.h> |
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#include <linux/slab.h> |
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#include "iosm_ipc_mmio.h" |
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/* Definition of MMIO offsets |
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* note that MMIO_CI offsets are relative to end of chip info structure |
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*/ |
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/* MMIO chip info size in bytes */ |
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#define MMIO_CHIP_INFO_SIZE 60 |
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/* CP execution stage */ |
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#define MMIO_OFFSET_EXECUTION_STAGE 0x00 |
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/* Boot ROM Chip Info struct */ |
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#define MMIO_OFFSET_CHIP_INFO 0x04 |
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#define MMIO_OFFSET_ROM_EXIT_CODE 0x40 |
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#define MMIO_OFFSET_PSI_ADDRESS 0x54 |
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#define MMIO_OFFSET_PSI_SIZE 0x5C |
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#define MMIO_OFFSET_IPC_STATUS 0x60 |
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#define MMIO_OFFSET_CONTEXT_INFO 0x64 |
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#define MMIO_OFFSET_BASE_ADDR 0x6C |
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#define MMIO_OFFSET_END_ADDR 0x74 |
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#define MMIO_OFFSET_CP_VERSION 0xF0 |
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#define MMIO_OFFSET_CP_CAPABILITIES 0xF4 |
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/* Timeout in 50 msec to wait for the modem boot code to write a valid |
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* execution stage into mmio area |
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*/ |
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#define IPC_MMIO_EXEC_STAGE_TIMEOUT 50 |
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/* check if exec stage has one of the valid values */ |
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static bool ipc_mmio_is_valid_exec_stage(enum ipc_mem_exec_stage stage) |
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{ |
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switch (stage) { |
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case IPC_MEM_EXEC_STAGE_BOOT: |
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case IPC_MEM_EXEC_STAGE_PSI: |
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case IPC_MEM_EXEC_STAGE_EBL: |
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case IPC_MEM_EXEC_STAGE_RUN: |
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case IPC_MEM_EXEC_STAGE_CRASH: |
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case IPC_MEM_EXEC_STAGE_CD_READY: |
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return true; |
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default: |
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return false; |
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} |
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} |
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void ipc_mmio_update_cp_capability(struct iosm_mmio *ipc_mmio) |
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{ |
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u32 cp_cap; |
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unsigned int ver; |
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ver = ipc_mmio_get_cp_version(ipc_mmio); |
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cp_cap = ioread32(ipc_mmio->base + ipc_mmio->offset.cp_capability); |
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ipc_mmio->has_mux_lite = (ver >= IOSM_CP_VERSION) && |
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!(cp_cap & DL_AGGR) && !(cp_cap & UL_AGGR); |
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ipc_mmio->has_ul_flow_credit = |
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(ver >= IOSM_CP_VERSION) && (cp_cap & UL_FLOW_CREDIT); |
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} |
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struct iosm_mmio *ipc_mmio_init(void __iomem *mmio, struct device *dev) |
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{ |
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struct iosm_mmio *ipc_mmio = kzalloc(sizeof(*ipc_mmio), GFP_KERNEL); |
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int retries = IPC_MMIO_EXEC_STAGE_TIMEOUT; |
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enum ipc_mem_exec_stage stage; |
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if (!ipc_mmio) |
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return NULL; |
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ipc_mmio->dev = dev; |
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ipc_mmio->base = mmio; |
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ipc_mmio->offset.exec_stage = MMIO_OFFSET_EXECUTION_STAGE; |
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/* Check for a valid execution stage to make sure that the boot code |
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* has correctly initialized the MMIO area. |
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*/ |
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do { |
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stage = ipc_mmio_get_exec_stage(ipc_mmio); |
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if (ipc_mmio_is_valid_exec_stage(stage)) |
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break; |
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msleep(20); |
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} while (retries-- > 0); |
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if (!retries) { |
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dev_err(ipc_mmio->dev, "invalid exec stage %X", stage); |
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goto init_fail; |
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} |
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ipc_mmio->offset.chip_info = MMIO_OFFSET_CHIP_INFO; |
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/* read chip info size and version from chip info structure */ |
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ipc_mmio->chip_info_version = |
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ioread8(ipc_mmio->base + ipc_mmio->offset.chip_info); |
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/* Increment of 2 is needed as the size value in the chip info |
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* excludes the version and size field, which are always present |
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*/ |
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ipc_mmio->chip_info_size = |
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ioread8(ipc_mmio->base + ipc_mmio->offset.chip_info + 1) + 2; |
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if (ipc_mmio->chip_info_size != MMIO_CHIP_INFO_SIZE) { |
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dev_err(ipc_mmio->dev, "Unexpected Chip Info"); |
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goto init_fail; |
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} |
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ipc_mmio->offset.rom_exit_code = MMIO_OFFSET_ROM_EXIT_CODE; |
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ipc_mmio->offset.psi_address = MMIO_OFFSET_PSI_ADDRESS; |
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ipc_mmio->offset.psi_size = MMIO_OFFSET_PSI_SIZE; |
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ipc_mmio->offset.ipc_status = MMIO_OFFSET_IPC_STATUS; |
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ipc_mmio->offset.context_info = MMIO_OFFSET_CONTEXT_INFO; |
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ipc_mmio->offset.ap_win_base = MMIO_OFFSET_BASE_ADDR; |
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ipc_mmio->offset.ap_win_end = MMIO_OFFSET_END_ADDR; |
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ipc_mmio->offset.cp_version = MMIO_OFFSET_CP_VERSION; |
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ipc_mmio->offset.cp_capability = MMIO_OFFSET_CP_CAPABILITIES; |
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return ipc_mmio; |
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init_fail: |
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kfree(ipc_mmio); |
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return NULL; |
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} |
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enum ipc_mem_exec_stage ipc_mmio_get_exec_stage(struct iosm_mmio *ipc_mmio) |
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{ |
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if (!ipc_mmio) |
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return IPC_MEM_EXEC_STAGE_INVALID; |
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return (enum ipc_mem_exec_stage)ioread32(ipc_mmio->base + |
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ipc_mmio->offset.exec_stage); |
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} |
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void ipc_mmio_copy_chip_info(struct iosm_mmio *ipc_mmio, void *dest, |
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size_t size) |
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{ |
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if (ipc_mmio && dest) |
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memcpy_fromio(dest, ipc_mmio->base + ipc_mmio->offset.chip_info, |
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size); |
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} |
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enum ipc_mem_device_ipc_state ipc_mmio_get_ipc_state(struct iosm_mmio *ipc_mmio) |
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{ |
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if (!ipc_mmio) |
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return IPC_MEM_DEVICE_IPC_INVALID; |
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return (enum ipc_mem_device_ipc_state)ioread32(ipc_mmio->base + |
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ipc_mmio->offset.ipc_status); |
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} |
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enum rom_exit_code ipc_mmio_get_rom_exit_code(struct iosm_mmio *ipc_mmio) |
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{ |
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if (!ipc_mmio) |
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return IMEM_ROM_EXIT_FAIL; |
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return (enum rom_exit_code)ioread32(ipc_mmio->base + |
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ipc_mmio->offset.rom_exit_code); |
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} |
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void ipc_mmio_config(struct iosm_mmio *ipc_mmio) |
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{ |
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if (!ipc_mmio) |
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return; |
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/* AP memory window (full window is open and active so that modem checks |
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* each AP address) 0 means don't check on modem side. |
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*/ |
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iowrite64(0, ipc_mmio->base + ipc_mmio->offset.ap_win_base); |
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iowrite64(0, ipc_mmio->base + ipc_mmio->offset.ap_win_end); |
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iowrite64(ipc_mmio->context_info_addr, |
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ipc_mmio->base + ipc_mmio->offset.context_info); |
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} |
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void ipc_mmio_set_psi_addr_and_size(struct iosm_mmio *ipc_mmio, dma_addr_t addr, |
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u32 size) |
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{ |
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if (!ipc_mmio) |
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return; |
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iowrite64(addr, ipc_mmio->base + ipc_mmio->offset.psi_address); |
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iowrite32(size, ipc_mmio->base + ipc_mmio->offset.psi_size); |
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} |
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void ipc_mmio_set_contex_info_addr(struct iosm_mmio *ipc_mmio, phys_addr_t addr) |
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{ |
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if (!ipc_mmio) |
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return; |
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/* store context_info address. This will be stored in the mmio area |
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* during IPC_MEM_DEVICE_IPC_INIT state via ipc_mmio_config() |
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*/ |
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ipc_mmio->context_info_addr = addr; |
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} |
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int ipc_mmio_get_cp_version(struct iosm_mmio *ipc_mmio) |
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{ |
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if (ipc_mmio) |
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return ioread32(ipc_mmio->base + ipc_mmio->offset.cp_version); |
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return -EFAULT; |
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}
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