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59 lines
1.4 KiB
59 lines
1.4 KiB
/* SPDX-License-Identifier: GPL-2.0-only |
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* |
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* Copyright (C) 2020-21 Intel Corporation |
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*/ |
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#ifndef IOSM_IPC_CHNL_CFG_H |
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#define IOSM_IPC_CHNL_CFG_H |
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#include "iosm_ipc_mux.h" |
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/* Number of TDs on the trace channel */ |
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#define IPC_MEM_TDS_TRC 32 |
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/* Trace channel TD buffer size. */ |
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#define IPC_MEM_MAX_DL_TRC_BUF_SIZE 8192 |
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/* Channel ID */ |
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enum ipc_channel_id { |
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IPC_MEM_IP_CHL_ID_0 = 0, |
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IPC_MEM_CTRL_CHL_ID_1, |
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IPC_MEM_CTRL_CHL_ID_2, |
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IPC_MEM_CTRL_CHL_ID_3, |
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IPC_MEM_CTRL_CHL_ID_4, |
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IPC_MEM_CTRL_CHL_ID_5, |
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IPC_MEM_CTRL_CHL_ID_6, |
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}; |
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/** |
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* struct ipc_chnl_cfg - IPC channel configuration structure |
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* @id: Interface ID |
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* @ul_pipe: Uplink datastream |
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* @dl_pipe: Downlink datastream |
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* @ul_nr_of_entries: Number of Transfer descriptor uplink pipe |
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* @dl_nr_of_entries: Number of Transfer descriptor downlink pipe |
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* @dl_buf_size: Downlink buffer size |
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* @wwan_port_type: Wwan subsystem port type |
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* @accumulation_backoff: Time in usec for data accumalation |
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*/ |
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struct ipc_chnl_cfg { |
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u32 id; |
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u32 ul_pipe; |
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u32 dl_pipe; |
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u32 ul_nr_of_entries; |
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u32 dl_nr_of_entries; |
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u32 dl_buf_size; |
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u32 wwan_port_type; |
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u32 accumulation_backoff; |
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}; |
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/** |
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* ipc_chnl_cfg_get - Get pipe configuration. |
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* @chnl_cfg: Array of ipc_chnl_cfg struct |
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* @index: Channel index (upto MAX_CHANNELS) |
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* |
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* Return: 0 on success and failure value on error |
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*/ |
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int ipc_chnl_cfg_get(struct ipc_chnl_cfg *chnl_cfg, int index); |
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#endif
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