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466 lines
11 KiB
466 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* Applied Micro X-Gene SoC MDIO Driver |
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* |
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* Copyright (c) 2016, Applied Micro Circuits Corporation |
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* Author: Iyappan Subramanian <[email protected]> |
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*/ |
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#include <linux/acpi.h> |
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#include <linux/clk.h> |
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#include <linux/device.h> |
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#include <linux/efi.h> |
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#include <linux/if_vlan.h> |
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#include <linux/io.h> |
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#include <linux/mdio/mdio-xgene.h> |
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#include <linux/module.h> |
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#include <linux/of_platform.h> |
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#include <linux/of_net.h> |
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#include <linux/of_mdio.h> |
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#include <linux/prefetch.h> |
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#include <linux/phy.h> |
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#include <net/ip.h> |
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static bool xgene_mdio_status; |
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u32 xgene_mdio_rd_mac(struct xgene_mdio_pdata *pdata, u32 rd_addr) |
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{ |
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void __iomem *addr, *rd, *cmd, *cmd_done; |
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u32 done, rd_data = BUSY_MASK; |
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u8 wait = 10; |
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addr = pdata->mac_csr_addr + MAC_ADDR_REG_OFFSET; |
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rd = pdata->mac_csr_addr + MAC_READ_REG_OFFSET; |
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cmd = pdata->mac_csr_addr + MAC_COMMAND_REG_OFFSET; |
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cmd_done = pdata->mac_csr_addr + MAC_COMMAND_DONE_REG_OFFSET; |
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spin_lock(&pdata->mac_lock); |
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iowrite32(rd_addr, addr); |
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iowrite32(XGENE_ENET_RD_CMD, cmd); |
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while (!(done = ioread32(cmd_done)) && wait--) |
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udelay(1); |
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if (done) |
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rd_data = ioread32(rd); |
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iowrite32(0, cmd); |
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spin_unlock(&pdata->mac_lock); |
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return rd_data; |
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} |
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EXPORT_SYMBOL(xgene_mdio_rd_mac); |
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void xgene_mdio_wr_mac(struct xgene_mdio_pdata *pdata, u32 wr_addr, u32 data) |
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{ |
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void __iomem *addr, *wr, *cmd, *cmd_done; |
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u8 wait = 10; |
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u32 done; |
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addr = pdata->mac_csr_addr + MAC_ADDR_REG_OFFSET; |
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wr = pdata->mac_csr_addr + MAC_WRITE_REG_OFFSET; |
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cmd = pdata->mac_csr_addr + MAC_COMMAND_REG_OFFSET; |
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cmd_done = pdata->mac_csr_addr + MAC_COMMAND_DONE_REG_OFFSET; |
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spin_lock(&pdata->mac_lock); |
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iowrite32(wr_addr, addr); |
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iowrite32(data, wr); |
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iowrite32(XGENE_ENET_WR_CMD, cmd); |
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while (!(done = ioread32(cmd_done)) && wait--) |
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udelay(1); |
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if (!done) |
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pr_err("MCX mac write failed, addr: 0x%04x\n", wr_addr); |
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iowrite32(0, cmd); |
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spin_unlock(&pdata->mac_lock); |
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} |
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EXPORT_SYMBOL(xgene_mdio_wr_mac); |
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int xgene_mdio_rgmii_read(struct mii_bus *bus, int phy_id, int reg) |
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{ |
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struct xgene_mdio_pdata *pdata = (struct xgene_mdio_pdata *)bus->priv; |
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u32 data, done; |
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u8 wait = 10; |
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data = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg); |
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xgene_mdio_wr_mac(pdata, MII_MGMT_ADDRESS_ADDR, data); |
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xgene_mdio_wr_mac(pdata, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK); |
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do { |
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usleep_range(5, 10); |
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done = xgene_mdio_rd_mac(pdata, MII_MGMT_INDICATORS_ADDR); |
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} while ((done & BUSY_MASK) && wait--); |
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if (done & BUSY_MASK) { |
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dev_err(&bus->dev, "MII_MGMT read failed\n"); |
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return -EBUSY; |
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} |
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data = xgene_mdio_rd_mac(pdata, MII_MGMT_STATUS_ADDR); |
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xgene_mdio_wr_mac(pdata, MII_MGMT_COMMAND_ADDR, 0); |
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return data; |
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} |
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EXPORT_SYMBOL(xgene_mdio_rgmii_read); |
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int xgene_mdio_rgmii_write(struct mii_bus *bus, int phy_id, int reg, u16 data) |
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{ |
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struct xgene_mdio_pdata *pdata = (struct xgene_mdio_pdata *)bus->priv; |
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u32 val, done; |
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u8 wait = 10; |
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val = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg); |
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xgene_mdio_wr_mac(pdata, MII_MGMT_ADDRESS_ADDR, val); |
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xgene_mdio_wr_mac(pdata, MII_MGMT_CONTROL_ADDR, data); |
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do { |
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usleep_range(5, 10); |
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done = xgene_mdio_rd_mac(pdata, MII_MGMT_INDICATORS_ADDR); |
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} while ((done & BUSY_MASK) && wait--); |
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if (done & BUSY_MASK) { |
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dev_err(&bus->dev, "MII_MGMT write failed\n"); |
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return -EBUSY; |
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} |
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return 0; |
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} |
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EXPORT_SYMBOL(xgene_mdio_rgmii_write); |
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static u32 xgene_menet_rd_diag_csr(struct xgene_mdio_pdata *pdata, u32 offset) |
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{ |
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return ioread32(pdata->diag_csr_addr + offset); |
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} |
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static void xgene_menet_wr_diag_csr(struct xgene_mdio_pdata *pdata, |
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u32 offset, u32 val) |
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{ |
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iowrite32(val, pdata->diag_csr_addr + offset); |
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} |
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static int xgene_enet_ecc_init(struct xgene_mdio_pdata *pdata) |
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{ |
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u32 data; |
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u8 wait = 10; |
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xgene_menet_wr_diag_csr(pdata, MENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0); |
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do { |
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usleep_range(100, 110); |
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data = xgene_menet_rd_diag_csr(pdata, MENET_BLOCK_MEM_RDY_ADDR); |
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} while ((data != 0xffffffff) && wait--); |
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if (data != 0xffffffff) { |
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dev_err(pdata->dev, "Failed to release memory from shutdown\n"); |
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return -ENODEV; |
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} |
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return 0; |
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} |
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static void xgene_gmac_reset(struct xgene_mdio_pdata *pdata) |
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{ |
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xgene_mdio_wr_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET); |
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xgene_mdio_wr_mac(pdata, MAC_CONFIG_1_ADDR, 0); |
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} |
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static int xgene_mdio_reset(struct xgene_mdio_pdata *pdata) |
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{ |
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int ret; |
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if (pdata->dev->of_node) { |
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clk_prepare_enable(pdata->clk); |
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udelay(5); |
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clk_disable_unprepare(pdata->clk); |
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udelay(5); |
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clk_prepare_enable(pdata->clk); |
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udelay(5); |
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} else { |
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#ifdef CONFIG_ACPI |
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acpi_evaluate_object(ACPI_HANDLE(pdata->dev), |
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"_RST", NULL, NULL); |
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#endif |
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} |
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ret = xgene_enet_ecc_init(pdata); |
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if (ret) { |
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if (pdata->dev->of_node) |
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clk_disable_unprepare(pdata->clk); |
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return ret; |
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} |
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xgene_gmac_reset(pdata); |
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return 0; |
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} |
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static void xgene_enet_rd_mdio_csr(void __iomem *base_addr, |
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u32 offset, u32 *val) |
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{ |
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void __iomem *addr = base_addr + offset; |
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*val = ioread32(addr); |
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} |
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static void xgene_enet_wr_mdio_csr(void __iomem *base_addr, |
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u32 offset, u32 val) |
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{ |
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void __iomem *addr = base_addr + offset; |
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iowrite32(val, addr); |
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} |
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static int xgene_xfi_mdio_write(struct mii_bus *bus, int phy_id, |
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int reg, u16 data) |
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{ |
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void __iomem *addr = (void __iomem *)bus->priv; |
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int timeout = 100; |
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u32 status, val; |
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val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg) | |
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SET_VAL(HSTMIIMWRDAT, data); |
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xgene_enet_wr_mdio_csr(addr, MIIM_FIELD_ADDR, val); |
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val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_WRITE); |
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xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, val); |
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do { |
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usleep_range(5, 10); |
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xgene_enet_rd_mdio_csr(addr, MIIM_INDICATOR_ADDR, &status); |
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} while ((status & BUSY_MASK) && timeout--); |
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xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, 0); |
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return 0; |
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} |
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static int xgene_xfi_mdio_read(struct mii_bus *bus, int phy_id, int reg) |
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{ |
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void __iomem *addr = (void __iomem *)bus->priv; |
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u32 data, status, val; |
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int timeout = 100; |
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val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg); |
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xgene_enet_wr_mdio_csr(addr, MIIM_FIELD_ADDR, val); |
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val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_READ); |
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xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, val); |
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do { |
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usleep_range(5, 10); |
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xgene_enet_rd_mdio_csr(addr, MIIM_INDICATOR_ADDR, &status); |
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} while ((status & BUSY_MASK) && timeout--); |
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if (status & BUSY_MASK) { |
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pr_err("XGENET_MII_MGMT write failed\n"); |
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return -EBUSY; |
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} |
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xgene_enet_rd_mdio_csr(addr, MIIMRD_FIELD_ADDR, &data); |
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xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, 0); |
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return data; |
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} |
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struct phy_device *xgene_enet_phy_register(struct mii_bus *bus, int phy_addr) |
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{ |
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struct phy_device *phy_dev; |
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phy_dev = get_phy_device(bus, phy_addr, false); |
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if (!phy_dev || IS_ERR(phy_dev)) |
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return NULL; |
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if (phy_device_register(phy_dev)) |
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phy_device_free(phy_dev); |
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return phy_dev; |
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} |
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EXPORT_SYMBOL(xgene_enet_phy_register); |
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#ifdef CONFIG_ACPI |
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static acpi_status acpi_register_phy(acpi_handle handle, u32 lvl, |
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void *context, void **ret) |
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{ |
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struct mii_bus *mdio = context; |
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struct acpi_device *adev; |
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struct phy_device *phy_dev; |
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const union acpi_object *obj; |
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u32 phy_addr; |
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if (acpi_bus_get_device(handle, &adev)) |
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return AE_OK; |
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if (acpi_dev_get_property(adev, "phy-channel", ACPI_TYPE_INTEGER, &obj)) |
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return AE_OK; |
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phy_addr = obj->integer.value; |
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phy_dev = xgene_enet_phy_register(mdio, phy_addr); |
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adev->driver_data = phy_dev; |
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return AE_OK; |
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} |
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#endif |
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static const struct of_device_id xgene_mdio_of_match[] = { |
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{ |
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.compatible = "apm,xgene-mdio-rgmii", |
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.data = (void *)XGENE_MDIO_RGMII |
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}, |
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{ |
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.compatible = "apm,xgene-mdio-xfi", |
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.data = (void *)XGENE_MDIO_XFI |
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}, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, xgene_mdio_of_match); |
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#ifdef CONFIG_ACPI |
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static const struct acpi_device_id xgene_mdio_acpi_match[] = { |
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{ "APMC0D65", XGENE_MDIO_RGMII }, |
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{ "APMC0D66", XGENE_MDIO_XFI }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(acpi, xgene_mdio_acpi_match); |
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#endif |
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static int xgene_mdio_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct mii_bus *mdio_bus; |
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const struct of_device_id *of_id; |
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struct xgene_mdio_pdata *pdata; |
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void __iomem *csr_base; |
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int mdio_id = 0, ret = 0; |
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of_id = of_match_device(xgene_mdio_of_match, &pdev->dev); |
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if (of_id) { |
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mdio_id = (enum xgene_mdio_id)of_id->data; |
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} else { |
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#ifdef CONFIG_ACPI |
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const struct acpi_device_id *acpi_id; |
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acpi_id = acpi_match_device(xgene_mdio_acpi_match, &pdev->dev); |
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if (acpi_id) |
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mdio_id = (enum xgene_mdio_id)acpi_id->driver_data; |
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#endif |
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} |
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if (!mdio_id) |
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return -ENODEV; |
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pdata = devm_kzalloc(dev, sizeof(struct xgene_mdio_pdata), GFP_KERNEL); |
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if (!pdata) |
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return -ENOMEM; |
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pdata->mdio_id = mdio_id; |
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pdata->dev = dev; |
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csr_base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(csr_base)) |
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return PTR_ERR(csr_base); |
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pdata->mac_csr_addr = csr_base; |
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pdata->mdio_csr_addr = csr_base + BLOCK_XG_MDIO_CSR_OFFSET; |
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pdata->diag_csr_addr = csr_base + BLOCK_DIAG_CSR_OFFSET; |
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if (mdio_id == XGENE_MDIO_RGMII) |
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spin_lock_init(&pdata->mac_lock); |
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if (dev->of_node) { |
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pdata->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(pdata->clk)) { |
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dev_err(dev, "Unable to retrieve clk\n"); |
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return PTR_ERR(pdata->clk); |
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} |
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} |
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ret = xgene_mdio_reset(pdata); |
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if (ret) |
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return ret; |
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mdio_bus = mdiobus_alloc(); |
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if (!mdio_bus) { |
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ret = -ENOMEM; |
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goto out_clk; |
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} |
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mdio_bus->name = "APM X-Gene MDIO bus"; |
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if (mdio_id == XGENE_MDIO_RGMII) { |
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mdio_bus->read = xgene_mdio_rgmii_read; |
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mdio_bus->write = xgene_mdio_rgmii_write; |
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mdio_bus->priv = (void __force *)pdata; |
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snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s", |
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"xgene-mii-rgmii"); |
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} else { |
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mdio_bus->read = xgene_xfi_mdio_read; |
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mdio_bus->write = xgene_xfi_mdio_write; |
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mdio_bus->priv = (void __force *)pdata->mdio_csr_addr; |
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snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s", |
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"xgene-mii-xfi"); |
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} |
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mdio_bus->parent = dev; |
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platform_set_drvdata(pdev, pdata); |
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if (dev->of_node) { |
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ret = of_mdiobus_register(mdio_bus, dev->of_node); |
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} else { |
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#ifdef CONFIG_ACPI |
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/* Mask out all PHYs from auto probing. */ |
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mdio_bus->phy_mask = ~0; |
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ret = mdiobus_register(mdio_bus); |
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if (ret) |
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goto out_mdiobus; |
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acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_HANDLE(dev), 1, |
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acpi_register_phy, NULL, mdio_bus, NULL); |
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#endif |
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} |
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if (ret) |
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goto out_mdiobus; |
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pdata->mdio_bus = mdio_bus; |
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xgene_mdio_status = true; |
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return 0; |
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out_mdiobus: |
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mdiobus_free(mdio_bus); |
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out_clk: |
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if (dev->of_node) |
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clk_disable_unprepare(pdata->clk); |
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return ret; |
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} |
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static int xgene_mdio_remove(struct platform_device *pdev) |
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{ |
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struct xgene_mdio_pdata *pdata = platform_get_drvdata(pdev); |
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struct mii_bus *mdio_bus = pdata->mdio_bus; |
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struct device *dev = &pdev->dev; |
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mdiobus_unregister(mdio_bus); |
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mdiobus_free(mdio_bus); |
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if (dev->of_node) |
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clk_disable_unprepare(pdata->clk); |
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return 0; |
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} |
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static struct platform_driver xgene_mdio_driver = { |
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.driver = { |
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.name = "xgene-mdio", |
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.of_match_table = of_match_ptr(xgene_mdio_of_match), |
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.acpi_match_table = ACPI_PTR(xgene_mdio_acpi_match), |
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}, |
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.probe = xgene_mdio_probe, |
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.remove = xgene_mdio_remove, |
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}; |
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module_platform_driver(xgene_mdio_driver); |
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MODULE_DESCRIPTION("APM X-Gene SoC MDIO driver"); |
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MODULE_AUTHOR("Iyappan Subramanian <[email protected]>"); |
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MODULE_LICENSE("GPL");
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