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533 lines
12 KiB
533 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. |
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* Copyright (C) 2019-2021 Linaro Ltd. |
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*/ |
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#include <linux/log2.h> |
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#include "gsi.h" |
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#include "ipa_data.h" |
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#include "ipa_endpoint.h" |
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#include "ipa_mem.h" |
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/** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.1 */ |
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enum ipa_resource_type { |
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/* Source resource types; first must have value 0 */ |
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IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, |
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IPA_RESOURCE_TYPE_SRC_HDR_SECTORS, |
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IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER, |
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IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, |
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IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, |
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IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS, |
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IPA_RESOURCE_TYPE_SRC_HPS_DMARS, |
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IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, |
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/* Destination resource types; first must have value 0 */ |
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IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, |
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IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS, |
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IPA_RESOURCE_TYPE_DST_DPS_DMARS, |
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}; |
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/* Resource groups used for an SoC having IPA v3.1 */ |
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enum ipa_rsrc_group_id { |
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/* Source resource group identifiers */ |
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IPA_RSRC_GROUP_SRC_UL = 0, |
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IPA_RSRC_GROUP_SRC_DL, |
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IPA_RSRC_GROUP_SRC_DIAG, |
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IPA_RSRC_GROUP_SRC_DMA, |
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IPA_RSRC_GROUP_SRC_UNUSED, |
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IPA_RSRC_GROUP_SRC_UC_RX_Q, |
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IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ |
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/* Destination resource group identifiers */ |
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IPA_RSRC_GROUP_DST_UL = 0, |
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IPA_RSRC_GROUP_DST_DL, |
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IPA_RSRC_GROUP_DST_DIAG_DPL, |
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IPA_RSRC_GROUP_DST_DMA, |
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IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL, |
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IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE, |
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IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ |
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}; |
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/* QSB configuration data for an SoC having IPA v3.1 */ |
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static const struct ipa_qsb_data ipa_qsb_data[] = { |
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[IPA_QSB_MASTER_DDR] = { |
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.max_writes = 8, |
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.max_reads = 8, |
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}, |
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[IPA_QSB_MASTER_PCIE] = { |
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.max_writes = 2, |
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.max_reads = 8, |
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}, |
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}; |
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/* Endpoint data for an SoC having IPA v3.1 */ |
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static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { |
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[IPA_ENDPOINT_AP_COMMAND_TX] = { |
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.ee_id = GSI_EE_AP, |
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.channel_id = 6, |
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.endpoint_id = 22, |
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.toward_ipa = true, |
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.channel = { |
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.tre_count = 256, |
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.event_count = 256, |
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.tlv_count = 18, |
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}, |
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.endpoint = { |
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.config = { |
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.resource_group = IPA_RSRC_GROUP_SRC_UL, |
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.dma_mode = true, |
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.dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, |
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.tx = { |
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.seq_type = IPA_SEQ_DMA, |
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}, |
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}, |
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}, |
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}, |
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[IPA_ENDPOINT_AP_LAN_RX] = { |
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.ee_id = GSI_EE_AP, |
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.channel_id = 7, |
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.endpoint_id = 15, |
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.toward_ipa = false, |
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.channel = { |
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.tre_count = 256, |
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.event_count = 256, |
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.tlv_count = 8, |
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}, |
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.endpoint = { |
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.config = { |
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.resource_group = IPA_RSRC_GROUP_SRC_UL, |
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.aggregation = true, |
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.status_enable = true, |
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.rx = { |
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.pad_align = ilog2(sizeof(u32)), |
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}, |
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}, |
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}, |
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}, |
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[IPA_ENDPOINT_AP_MODEM_TX] = { |
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.ee_id = GSI_EE_AP, |
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.channel_id = 5, |
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.endpoint_id = 3, |
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.toward_ipa = true, |
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.channel = { |
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.tre_count = 512, |
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.event_count = 512, |
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.tlv_count = 16, |
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}, |
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.endpoint = { |
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.filter_support = true, |
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.config = { |
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.resource_group = IPA_RSRC_GROUP_SRC_UL, |
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.checksum = true, |
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.qmap = true, |
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.status_enable = true, |
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.tx = { |
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.seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, |
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.status_endpoint = |
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IPA_ENDPOINT_MODEM_AP_RX, |
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}, |
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}, |
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}, |
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}, |
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[IPA_ENDPOINT_AP_MODEM_RX] = { |
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.ee_id = GSI_EE_AP, |
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.channel_id = 8, |
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.endpoint_id = 16, |
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.toward_ipa = false, |
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.channel = { |
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.tre_count = 256, |
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.event_count = 256, |
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.tlv_count = 8, |
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}, |
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.endpoint = { |
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.config = { |
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.resource_group = IPA_RSRC_GROUP_DST_DL, |
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.checksum = true, |
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.qmap = true, |
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.aggregation = true, |
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.rx = { |
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.aggr_close_eof = true, |
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}, |
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}, |
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}, |
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}, |
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[IPA_ENDPOINT_MODEM_LAN_TX] = { |
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.ee_id = GSI_EE_MODEM, |
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.channel_id = 4, |
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.endpoint_id = 9, |
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.toward_ipa = true, |
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.endpoint = { |
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.filter_support = true, |
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}, |
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}, |
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[IPA_ENDPOINT_MODEM_AP_TX] = { |
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.ee_id = GSI_EE_MODEM, |
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.channel_id = 0, |
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.endpoint_id = 5, |
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.toward_ipa = true, |
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.endpoint = { |
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.filter_support = true, |
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}, |
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}, |
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[IPA_ENDPOINT_MODEM_AP_RX] = { |
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.ee_id = GSI_EE_MODEM, |
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.channel_id = 5, |
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.endpoint_id = 18, |
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.toward_ipa = false, |
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}, |
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}; |
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/* Source resource configuration data for an SoC having IPA v3.1 */ |
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static const struct ipa_resource ipa_resource_src[] = { |
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[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { |
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.limits[IPA_RSRC_GROUP_SRC_UL] = { |
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.min = 3, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DL] = { |
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.min = 3, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
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.min = 1, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DMA] = { |
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.min = 1, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
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.min = 2, .max = 255, |
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}, |
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}, |
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[IPA_RESOURCE_TYPE_SRC_HDR_SECTORS] = { |
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.limits[IPA_RSRC_GROUP_SRC_UL] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DL] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DMA] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
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.min = 0, .max = 255, |
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}, |
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}, |
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[IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER] = { |
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.limits[IPA_RSRC_GROUP_SRC_UL] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DL] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DMA] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
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.min = 0, .max = 255, |
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}, |
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}, |
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[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { |
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.limits[IPA_RSRC_GROUP_SRC_UL] = { |
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.min = 14, .max = 14, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DL] = { |
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.min = 16, .max = 16, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
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.min = 5, .max = 5, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DMA] = { |
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.min = 5, .max = 5, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
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.min = 8, .max = 8, |
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}, |
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}, |
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[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { |
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.limits[IPA_RSRC_GROUP_SRC_UL] = { |
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.min = 19, .max = 19, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DL] = { |
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.min = 26, .max = 26, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
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.min = 5, .max = 5, /* 3 downstream */ |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DMA] = { |
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.min = 5, .max = 5, /* 7 downstream */ |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
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.min = 8, .max = 8, |
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}, |
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}, |
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[IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS] = { |
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.limits[IPA_RSRC_GROUP_SRC_UL] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DL] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DMA] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
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.min = 0, .max = 255, |
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}, |
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}, |
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[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { |
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.limits[IPA_RSRC_GROUP_SRC_UL] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DL] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DMA] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
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.min = 0, .max = 255, |
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}, |
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}, |
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[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { |
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.limits[IPA_RSRC_GROUP_SRC_UL] = { |
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.min = 19, .max = 19, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DL] = { |
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.min = 26, .max = 26, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
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.min = 5, .max = 5, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_DMA] = { |
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.min = 5, .max = 5, |
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}, |
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.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
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.min = 8, .max = 8, |
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}, |
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}, |
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}; |
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/* Destination resource configuration data for an SoC having IPA v3.1 */ |
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static const struct ipa_resource ipa_resource_dst[] = { |
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[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { |
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.limits[IPA_RSRC_GROUP_DST_UL] = { |
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.min = 3, .max = 3, /* 2 downstream */ |
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}, |
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.limits[IPA_RSRC_GROUP_DST_DL] = { |
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.min = 3, .max = 3, |
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}, |
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.limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { |
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.min = 1, .max = 1, /* 0 downstream */ |
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}, |
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/* IPA_RSRC_GROUP_DST_DMA uses 2 downstream */ |
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.limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { |
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.min = 3, .max = 3, |
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}, |
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.limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = { |
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.min = 3, .max = 3, |
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}, |
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}, |
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[IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS] = { |
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.limits[IPA_RSRC_GROUP_DST_UL] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_DST_DL] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_DST_DMA] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { |
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.min = 0, .max = 255, |
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}, |
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.limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = { |
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.min = 0, .max = 255, |
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}, |
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}, |
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[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { |
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.limits[IPA_RSRC_GROUP_DST_UL] = { |
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.min = 1, .max = 1, |
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}, |
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.limits[IPA_RSRC_GROUP_DST_DL] = { |
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.min = 1, .max = 1, |
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}, |
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.limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { |
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.min = 1, .max = 1, |
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}, |
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.limits[IPA_RSRC_GROUP_DST_DMA] = { |
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.min = 1, .max = 1, |
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}, |
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.limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { |
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.min = 1, .max = 1, |
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}, |
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}, |
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}; |
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/* Resource configuration data for an SoC having IPA v3.1 */ |
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static const struct ipa_resource_data ipa_resource_data = { |
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.rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, |
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.rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, |
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.resource_src_count = ARRAY_SIZE(ipa_resource_src), |
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.resource_src = ipa_resource_src, |
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.resource_dst_count = ARRAY_SIZE(ipa_resource_dst), |
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.resource_dst = ipa_resource_dst, |
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}; |
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/* IPA-resident memory region data for an SoC having IPA v3.1 */ |
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static const struct ipa_mem ipa_mem_local_data[] = { |
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{ |
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.id = IPA_MEM_UC_SHARED, |
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.offset = 0x0000, |
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.size = 0x0080, |
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.canary_count = 0, |
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}, |
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{ |
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.id = IPA_MEM_UC_INFO, |
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.offset = 0x0080, |
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.size = 0x0200, |
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.canary_count = 0, |
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}, |
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{ |
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.id = IPA_MEM_V4_FILTER_HASHED, |
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.offset = 0x0288, |
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.size = 0x0078, |
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.canary_count = 2, |
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}, |
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{ |
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.id = IPA_MEM_V4_FILTER, |
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.offset = 0x0308, |
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.size = 0x0078, |
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.canary_count = 2, |
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}, |
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{ |
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.id = IPA_MEM_V6_FILTER_HASHED, |
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.offset = 0x0388, |
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.size = 0x0078, |
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.canary_count = 2, |
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}, |
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{ |
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.id = IPA_MEM_V6_FILTER, |
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.offset = 0x0408, |
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.size = 0x0078, |
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.canary_count = 2, |
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}, |
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{ |
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.id = IPA_MEM_V4_ROUTE_HASHED, |
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.offset = 0x0488, |
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.size = 0x0078, |
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.canary_count = 2, |
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}, |
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{ |
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.id = IPA_MEM_V4_ROUTE, |
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.offset = 0x0508, |
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.size = 0x0078, |
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.canary_count = 2, |
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}, |
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{ |
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.id = IPA_MEM_V6_ROUTE_HASHED, |
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.offset = 0x0588, |
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.size = 0x0078, |
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.canary_count = 2, |
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}, |
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{ |
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.id = IPA_MEM_V6_ROUTE, |
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.offset = 0x0608, |
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.size = 0x0078, |
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.canary_count = 2, |
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}, |
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{ |
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.id = IPA_MEM_MODEM_HEADER, |
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.offset = 0x0688, |
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.size = 0x0140, |
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.canary_count = 2, |
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}, |
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{ |
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.id = IPA_MEM_MODEM_PROC_CTX, |
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.offset = 0x07d0, |
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.size = 0x0200, |
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.canary_count = 2, |
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}, |
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{ |
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.id = IPA_MEM_AP_PROC_CTX, |
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.offset = 0x09d0, |
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.size = 0x0200, |
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.canary_count = 0, |
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}, |
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{ |
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.id = IPA_MEM_MODEM, |
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.offset = 0x0bd8, |
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.size = 0x1424, |
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.canary_count = 0, |
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}, |
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{ |
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.id = IPA_MEM_END_MARKER, |
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.offset = 0x2000, |
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.size = 0, |
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.canary_count = 1, |
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}, |
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}; |
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/* Memory configuration data for an SoC having IPA v3.1 */ |
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static const struct ipa_mem_data ipa_mem_data = { |
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.local_count = ARRAY_SIZE(ipa_mem_local_data), |
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.local = ipa_mem_local_data, |
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.imem_addr = 0x146bd000, |
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.imem_size = 0x00002000, |
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.smem_id = 497, |
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.smem_size = 0x00002000, |
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}; |
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/* Interconnect bandwidths are in 1000 byte/second units */ |
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static const struct ipa_interconnect_data ipa_interconnect_data[] = { |
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{ |
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.name = "memory", |
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.peak_bandwidth = 640000, /* 640 MBps */ |
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.average_bandwidth = 80000, /* 80 MBps */ |
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}, |
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{ |
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.name = "imem", |
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.peak_bandwidth = 640000, /* 640 MBps */ |
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.average_bandwidth = 80000, /* 80 MBps */ |
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}, |
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/* Average bandwidth is unused for the next interconnect */ |
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{ |
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.name = "config", |
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.peak_bandwidth = 80000, /* 80 MBps */ |
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.average_bandwidth = 0, /* unused */ |
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}, |
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}; |
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/* Clock and interconnect configuration data for an SoC having IPA v3.1 */ |
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static const struct ipa_clock_data ipa_clock_data = { |
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.core_clock_rate = 16 * 1000 * 1000, /* Hz */ |
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.interconnect_count = ARRAY_SIZE(ipa_interconnect_data), |
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.interconnect_data = ipa_interconnect_data, |
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}; |
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/* Configuration data for an SoC having IPA v3.1 */ |
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const struct ipa_data ipa_data_v3_1 = { |
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.version = IPA_VERSION_3_1, |
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.backward_compat = BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK, |
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.qsb_count = ARRAY_SIZE(ipa_qsb_data), |
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.qsb_data = ipa_qsb_data, |
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.endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), |
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.endpoint_data = ipa_gsi_endpoint_data, |
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.resource_data = &ipa_resource_data, |
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.mem_data = &ipa_mem_data, |
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.clock_data = &ipa_clock_data, |
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};
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