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494 lines
12 KiB
494 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* XGE PCSR module initialisation |
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* |
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* Copyright (C) 2014 Texas Instruments Incorporated |
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* Authors: Sandeep Nair <[email protected]> |
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* WingMan Kwok <[email protected]> |
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* |
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*/ |
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#include "netcp.h" |
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/* XGBE registers */ |
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#define XGBE_CTRL_OFFSET 0x0c |
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#define XGBE_SGMII_1_OFFSET 0x0114 |
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#define XGBE_SGMII_2_OFFSET 0x0214 |
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/* PCS-R registers */ |
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#define PCSR_CPU_CTRL_OFFSET 0x1fd0 |
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#define POR_EN BIT(29) |
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#define reg_rmw(addr, value, mask) \ |
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writel(((readl(addr) & (~(mask))) | \ |
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(value & (mask))), (addr)) |
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/* bit mask of width w at offset s */ |
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#define MASK_WID_SH(w, s) (((1 << w) - 1) << s) |
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/* shift value v to offset s */ |
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#define VAL_SH(v, s) (v << s) |
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#define PHY_A(serdes) 0 |
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struct serdes_cfg { |
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u32 ofs; |
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u32 val; |
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u32 mask; |
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}; |
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static struct serdes_cfg cfg_phyb_1p25g_156p25mhz_cmu0[] = { |
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{0x0000, 0x00800002, 0x00ff00ff}, |
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{0x0014, 0x00003838, 0x0000ffff}, |
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{0x0060, 0x1c44e438, 0xffffffff}, |
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{0x0064, 0x00c18400, 0x00ffffff}, |
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{0x0068, 0x17078200, 0xffffff00}, |
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{0x006c, 0x00000014, 0x000000ff}, |
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{0x0078, 0x0000c000, 0x0000ff00}, |
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{0x0000, 0x00000003, 0x000000ff}, |
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}; |
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static struct serdes_cfg cfg_phyb_10p3125g_156p25mhz_cmu1[] = { |
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{0x0c00, 0x00030002, 0x00ff00ff}, |
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{0x0c14, 0x00005252, 0x0000ffff}, |
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{0x0c28, 0x80000000, 0xff000000}, |
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{0x0c2c, 0x000000f6, 0x000000ff}, |
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{0x0c3c, 0x04000405, 0xff00ffff}, |
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{0x0c40, 0xc0800000, 0xffff0000}, |
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{0x0c44, 0x5a202062, 0xffffffff}, |
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{0x0c48, 0x40040424, 0xffffffff}, |
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{0x0c4c, 0x00004002, 0x0000ffff}, |
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{0x0c50, 0x19001c00, 0xff00ff00}, |
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{0x0c54, 0x00002100, 0x0000ff00}, |
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{0x0c58, 0x00000060, 0x000000ff}, |
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{0x0c60, 0x80131e7c, 0xffffffff}, |
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{0x0c64, 0x8400cb02, 0xff00ffff}, |
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{0x0c68, 0x17078200, 0xffffff00}, |
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{0x0c6c, 0x00000016, 0x000000ff}, |
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{0x0c74, 0x00000400, 0x0000ff00}, |
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{0x0c78, 0x0000c000, 0x0000ff00}, |
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{0x0c00, 0x00000003, 0x000000ff}, |
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}; |
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static struct serdes_cfg cfg_phyb_10p3125g_16bit_lane[] = { |
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{0x0204, 0x00000080, 0x000000ff}, |
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{0x0208, 0x0000920d, 0x0000ffff}, |
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{0x0204, 0xfc000000, 0xff000000}, |
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{0x0208, 0x00009104, 0x0000ffff}, |
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{0x0210, 0x1a000000, 0xff000000}, |
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{0x0214, 0x00006b58, 0x00ffffff}, |
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{0x0218, 0x75800084, 0xffff00ff}, |
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{0x022c, 0x00300000, 0x00ff0000}, |
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{0x0230, 0x00003800, 0x0000ff00}, |
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{0x024c, 0x008f0000, 0x00ff0000}, |
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{0x0250, 0x30000000, 0xff000000}, |
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{0x0260, 0x00000002, 0x000000ff}, |
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{0x0264, 0x00000057, 0x000000ff}, |
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{0x0268, 0x00575700, 0x00ffff00}, |
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{0x0278, 0xff000000, 0xff000000}, |
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{0x0280, 0x00500050, 0x00ff00ff}, |
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{0x0284, 0x00001f15, 0x0000ffff}, |
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{0x028c, 0x00006f00, 0x0000ff00}, |
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{0x0294, 0x00000000, 0xffffff00}, |
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{0x0298, 0x00002640, 0xff00ffff}, |
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{0x029c, 0x00000003, 0x000000ff}, |
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{0x02a4, 0x00000f13, 0x0000ffff}, |
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{0x02a8, 0x0001b600, 0x00ffff00}, |
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{0x0380, 0x00000030, 0x000000ff}, |
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{0x03c0, 0x00000200, 0x0000ff00}, |
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{0x03cc, 0x00000018, 0x000000ff}, |
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{0x03cc, 0x00000000, 0x000000ff}, |
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}; |
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static struct serdes_cfg cfg_phyb_10p3125g_comlane[] = { |
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{0x0a00, 0x00000800, 0x0000ff00}, |
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{0x0a84, 0x00000000, 0x000000ff}, |
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{0x0a8c, 0x00130000, 0x00ff0000}, |
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{0x0a90, 0x77a00000, 0xffff0000}, |
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{0x0a94, 0x00007777, 0x0000ffff}, |
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{0x0b08, 0x000f0000, 0xffff0000}, |
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{0x0b0c, 0x000f0000, 0x00ffffff}, |
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{0x0b10, 0xbe000000, 0xff000000}, |
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{0x0b14, 0x000000ff, 0x000000ff}, |
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{0x0b18, 0x00000014, 0x000000ff}, |
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{0x0b5c, 0x981b0000, 0xffff0000}, |
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{0x0b64, 0x00001100, 0x0000ff00}, |
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{0x0b78, 0x00000c00, 0x0000ff00}, |
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{0x0abc, 0xff000000, 0xff000000}, |
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{0x0ac0, 0x0000008b, 0x000000ff}, |
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}; |
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static struct serdes_cfg cfg_cm_c1_c2[] = { |
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{0x0208, 0x00000000, 0x00000f00}, |
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{0x0208, 0x00000000, 0x0000001f}, |
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{0x0204, 0x00000000, 0x00040000}, |
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{0x0208, 0x000000a0, 0x000000e0}, |
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}; |
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static void netcp_xgbe_serdes_cmu_init(void __iomem *serdes_regs) |
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{ |
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int i; |
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/* cmu0 setup */ |
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for (i = 0; i < ARRAY_SIZE(cfg_phyb_1p25g_156p25mhz_cmu0); i++) { |
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reg_rmw(serdes_regs + cfg_phyb_1p25g_156p25mhz_cmu0[i].ofs, |
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cfg_phyb_1p25g_156p25mhz_cmu0[i].val, |
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cfg_phyb_1p25g_156p25mhz_cmu0[i].mask); |
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} |
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/* cmu1 setup */ |
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for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_156p25mhz_cmu1); i++) { |
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reg_rmw(serdes_regs + cfg_phyb_10p3125g_156p25mhz_cmu1[i].ofs, |
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cfg_phyb_10p3125g_156p25mhz_cmu1[i].val, |
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cfg_phyb_10p3125g_156p25mhz_cmu1[i].mask); |
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} |
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} |
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/* lane is 0 based */ |
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static void netcp_xgbe_serdes_lane_config( |
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void __iomem *serdes_regs, int lane) |
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{ |
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int i; |
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/* lane setup */ |
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for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_16bit_lane); i++) { |
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reg_rmw(serdes_regs + |
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cfg_phyb_10p3125g_16bit_lane[i].ofs + |
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(0x200 * lane), |
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cfg_phyb_10p3125g_16bit_lane[i].val, |
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cfg_phyb_10p3125g_16bit_lane[i].mask); |
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} |
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/* disable auto negotiation*/ |
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reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, |
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0x00000000, 0x00000010); |
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/* disable link training */ |
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reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, |
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0x00000000, 0x00000200); |
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} |
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static void netcp_xgbe_serdes_com_enable(void __iomem *serdes_regs) |
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{ |
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int i; |
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for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_comlane); i++) { |
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reg_rmw(serdes_regs + cfg_phyb_10p3125g_comlane[i].ofs, |
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cfg_phyb_10p3125g_comlane[i].val, |
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cfg_phyb_10p3125g_comlane[i].mask); |
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} |
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} |
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static void netcp_xgbe_serdes_lane_enable( |
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void __iomem *serdes_regs, int lane) |
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{ |
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/* Set Lane Control Rate */ |
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writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane)); |
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} |
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static void netcp_xgbe_serdes_phyb_rst_clr(void __iomem *serdes_regs) |
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{ |
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reg_rmw(serdes_regs + 0x0a00, 0x0000001f, 0x000000ff); |
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} |
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static void netcp_xgbe_serdes_pll_disable(void __iomem *serdes_regs) |
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{ |
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writel(0x88000000, serdes_regs + 0x1ff4); |
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} |
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static void netcp_xgbe_serdes_pll_enable(void __iomem *serdes_regs) |
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{ |
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netcp_xgbe_serdes_phyb_rst_clr(serdes_regs); |
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writel(0xee000000, serdes_regs + 0x1ff4); |
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} |
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static int netcp_xgbe_wait_pll_locked(void __iomem *sw_regs) |
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{ |
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unsigned long timeout; |
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int ret = 0; |
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u32 val_1, val_0; |
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timeout = jiffies + msecs_to_jiffies(500); |
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do { |
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val_0 = (readl(sw_regs + XGBE_SGMII_1_OFFSET) & BIT(4)); |
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val_1 = (readl(sw_regs + XGBE_SGMII_2_OFFSET) & BIT(4)); |
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if (val_1 && val_0) |
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return 0; |
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if (time_after(jiffies, timeout)) { |
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ret = -ETIMEDOUT; |
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break; |
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} |
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cpu_relax(); |
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} while (true); |
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pr_err("XGBE serdes not locked: time out.\n"); |
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return ret; |
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} |
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static void netcp_xgbe_serdes_enable_xgmii_port(void __iomem *sw_regs) |
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{ |
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writel(0x03, sw_regs + XGBE_CTRL_OFFSET); |
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} |
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static u32 netcp_xgbe_serdes_read_tbus_val(void __iomem *serdes_regs) |
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{ |
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u32 tmp; |
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if (PHY_A(serdes_regs)) { |
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tmp = (readl(serdes_regs + 0x0ec) >> 24) & 0x0ff; |
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tmp |= ((readl(serdes_regs + 0x0fc) >> 16) & 0x00f00); |
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} else { |
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tmp = (readl(serdes_regs + 0x0f8) >> 16) & 0x0fff; |
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} |
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return tmp; |
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} |
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static void netcp_xgbe_serdes_write_tbus_addr(void __iomem *serdes_regs, |
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int select, int ofs) |
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{ |
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if (PHY_A(serdes_regs)) { |
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reg_rmw(serdes_regs + 0x0008, ((select << 5) + ofs) << 24, |
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~0x00ffffff); |
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return; |
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} |
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/* For 2 lane Phy-B, lane0 is actually lane1 */ |
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switch (select) { |
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case 1: |
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select = 2; |
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break; |
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case 2: |
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select = 3; |
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break; |
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default: |
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return; |
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} |
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reg_rmw(serdes_regs + 0x00fc, ((select << 8) + ofs) << 16, ~0xf800ffff); |
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} |
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static u32 netcp_xgbe_serdes_read_select_tbus(void __iomem *serdes_regs, |
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int select, int ofs) |
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{ |
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/* Set tbus address */ |
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netcp_xgbe_serdes_write_tbus_addr(serdes_regs, select, ofs); |
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/* Get TBUS Value */ |
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return netcp_xgbe_serdes_read_tbus_val(serdes_regs); |
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} |
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static void netcp_xgbe_serdes_reset_cdr(void __iomem *serdes_regs, |
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void __iomem *sig_detect_reg, int lane) |
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{ |
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u32 tmp, dlpf, tbus; |
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/*Get the DLPF values */ |
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tmp = netcp_xgbe_serdes_read_select_tbus( |
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serdes_regs, lane + 1, 5); |
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dlpf = tmp >> 2; |
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if (dlpf < 400 || dlpf > 700) { |
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reg_rmw(sig_detect_reg, VAL_SH(2, 1), MASK_WID_SH(2, 1)); |
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mdelay(1); |
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reg_rmw(sig_detect_reg, VAL_SH(0, 1), MASK_WID_SH(2, 1)); |
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} else { |
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tbus = netcp_xgbe_serdes_read_select_tbus(serdes_regs, lane + |
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1, 0xe); |
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pr_debug("XGBE: CDR centered, DLPF: %4d,%d,%d.\n", |
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tmp >> 2, tmp & 3, (tbus >> 2) & 3); |
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} |
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} |
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/* Call every 100 ms */ |
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static int netcp_xgbe_check_link_status(void __iomem *serdes_regs, |
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void __iomem *sw_regs, u32 lanes, |
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u32 *current_state, u32 *lane_down) |
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{ |
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void __iomem *pcsr_base = sw_regs + 0x0600; |
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void __iomem *sig_detect_reg; |
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u32 pcsr_rx_stat, blk_lock, blk_errs; |
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int loss, i, status = 1; |
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for (i = 0; i < lanes; i++) { |
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/* Get the Loss bit */ |
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loss = readl(serdes_regs + 0x1fc0 + 0x20 + (i * 0x04)) & 0x1; |
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/* Get Block Errors and Block Lock bits */ |
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pcsr_rx_stat = readl(pcsr_base + 0x0c + (i * 0x80)); |
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blk_lock = (pcsr_rx_stat >> 30) & 0x1; |
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blk_errs = (pcsr_rx_stat >> 16) & 0x0ff; |
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/* Get Signal Detect Overlay Address */ |
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sig_detect_reg = serdes_regs + (i * 0x200) + 0x200 + 0x04; |
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/* If Block errors maxed out, attempt recovery! */ |
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if (blk_errs == 0x0ff) |
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blk_lock = 0; |
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switch (current_state[i]) { |
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case 0: |
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/* if good link lock the signal detect ON! */ |
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if (!loss && blk_lock) { |
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pr_debug("XGBE PCSR Linked Lane: %d\n", i); |
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reg_rmw(sig_detect_reg, VAL_SH(3, 1), |
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MASK_WID_SH(2, 1)); |
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current_state[i] = 1; |
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} else if (!blk_lock) { |
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/* if no lock, then reset CDR */ |
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pr_debug("XGBE PCSR Recover Lane: %d\n", i); |
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netcp_xgbe_serdes_reset_cdr(serdes_regs, |
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sig_detect_reg, i); |
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} |
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break; |
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case 1: |
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if (!blk_lock) { |
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/* Link Lost? */ |
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lane_down[i] = 1; |
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current_state[i] = 2; |
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} |
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break; |
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case 2: |
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if (blk_lock) |
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/* Nope just noise */ |
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current_state[i] = 1; |
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else { |
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/* Lost the block lock, reset CDR if it is |
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* not centered and go back to sync state |
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*/ |
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netcp_xgbe_serdes_reset_cdr(serdes_regs, |
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sig_detect_reg, i); |
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current_state[i] = 0; |
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} |
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break; |
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default: |
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pr_err("XGBE: unknown current_state[%d] %d\n", |
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i, current_state[i]); |
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break; |
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} |
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if (blk_errs > 0) { |
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/* Reset the Error counts! */ |
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reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x19, 0), |
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MASK_WID_SH(8, 0)); |
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reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x00, 0), |
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MASK_WID_SH(8, 0)); |
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} |
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status &= (current_state[i] == 1); |
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} |
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return status; |
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} |
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static int netcp_xgbe_serdes_check_lane(void __iomem *serdes_regs, |
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void __iomem *sw_regs) |
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{ |
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u32 current_state[2] = {0, 0}; |
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int retries = 0, link_up; |
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u32 lane_down[2]; |
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do { |
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lane_down[0] = 0; |
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lane_down[1] = 0; |
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link_up = netcp_xgbe_check_link_status(serdes_regs, sw_regs, 2, |
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current_state, |
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lane_down); |
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/* if we did not get link up then wait 100ms before calling |
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* it again |
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*/ |
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if (link_up) |
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break; |
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if (lane_down[0]) |
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pr_debug("XGBE: detected link down on lane 0\n"); |
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if (lane_down[1]) |
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pr_debug("XGBE: detected link down on lane 1\n"); |
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if (++retries > 1) { |
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pr_debug("XGBE: timeout waiting for serdes link up\n"); |
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return -ETIMEDOUT; |
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} |
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mdelay(100); |
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} while (!link_up); |
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pr_debug("XGBE: PCSR link is up\n"); |
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return 0; |
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} |
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static void netcp_xgbe_serdes_setup_cm_c1_c2(void __iomem *serdes_regs, |
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int lane, int cm, int c1, int c2) |
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{ |
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int i; |
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for (i = 0; i < ARRAY_SIZE(cfg_cm_c1_c2); i++) { |
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reg_rmw(serdes_regs + cfg_cm_c1_c2[i].ofs + (0x200 * lane), |
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cfg_cm_c1_c2[i].val, |
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cfg_cm_c1_c2[i].mask); |
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} |
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} |
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static void netcp_xgbe_reset_serdes(void __iomem *serdes_regs) |
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{ |
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/* Toggle the POR_EN bit in CONFIG.CPU_CTRL */ |
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/* enable POR_EN bit */ |
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reg_rmw(serdes_regs + PCSR_CPU_CTRL_OFFSET, POR_EN, POR_EN); |
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usleep_range(10, 100); |
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/* disable POR_EN bit */ |
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reg_rmw(serdes_regs + PCSR_CPU_CTRL_OFFSET, 0, POR_EN); |
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usleep_range(10, 100); |
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} |
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static int netcp_xgbe_serdes_config(void __iomem *serdes_regs, |
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void __iomem *sw_regs) |
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{ |
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u32 ret, i; |
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netcp_xgbe_serdes_pll_disable(serdes_regs); |
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netcp_xgbe_serdes_cmu_init(serdes_regs); |
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for (i = 0; i < 2; i++) |
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netcp_xgbe_serdes_lane_config(serdes_regs, i); |
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netcp_xgbe_serdes_com_enable(serdes_regs); |
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/* This is EVM + RTM-BOC specific */ |
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for (i = 0; i < 2; i++) |
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netcp_xgbe_serdes_setup_cm_c1_c2(serdes_regs, i, 0, 0, 5); |
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netcp_xgbe_serdes_pll_enable(serdes_regs); |
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for (i = 0; i < 2; i++) |
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netcp_xgbe_serdes_lane_enable(serdes_regs, i); |
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|
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/* SB PLL Status Poll */ |
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ret = netcp_xgbe_wait_pll_locked(sw_regs); |
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if (ret) |
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return ret; |
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netcp_xgbe_serdes_enable_xgmii_port(sw_regs); |
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netcp_xgbe_serdes_check_lane(serdes_regs, sw_regs); |
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return ret; |
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} |
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int netcp_xgbe_serdes_init(void __iomem *serdes_regs, void __iomem *xgbe_regs) |
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{ |
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u32 val; |
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|
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/* read COMLANE bits 4:0 */ |
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val = readl(serdes_regs + 0xa00); |
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if (val & 0x1f) { |
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pr_debug("XGBE: serdes already in operation - reset\n"); |
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netcp_xgbe_reset_serdes(serdes_regs); |
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} |
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return netcp_xgbe_serdes_config(serdes_regs, xgbe_regs); |
|
}
|
|
|