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502 lines
17 KiB
502 lines
17 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Texas Instruments Ethernet Switch Driver |
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*/ |
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#ifndef DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ |
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#define DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ |
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#include "davinci_cpdma.h" |
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#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ |
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NETIF_MSG_DRV | NETIF_MSG_LINK | \ |
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NETIF_MSG_IFUP | NETIF_MSG_INTR | \ |
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NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ |
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NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ |
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NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ |
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NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ |
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NETIF_MSG_RX_STATUS) |
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#define cpsw_info(priv, type, format, ...) \ |
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do { \ |
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if (netif_msg_##type(priv) && net_ratelimit()) \ |
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dev_info(priv->dev, format, ## __VA_ARGS__); \ |
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} while (0) |
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#define cpsw_err(priv, type, format, ...) \ |
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do { \ |
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if (netif_msg_##type(priv) && net_ratelimit()) \ |
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dev_err(priv->dev, format, ## __VA_ARGS__); \ |
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} while (0) |
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#define cpsw_dbg(priv, type, format, ...) \ |
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do { \ |
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if (netif_msg_##type(priv) && net_ratelimit()) \ |
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dev_dbg(priv->dev, format, ## __VA_ARGS__); \ |
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} while (0) |
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#define cpsw_notice(priv, type, format, ...) \ |
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do { \ |
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if (netif_msg_##type(priv) && net_ratelimit()) \ |
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dev_notice(priv->dev, format, ## __VA_ARGS__); \ |
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} while (0) |
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#define ALE_ALL_PORTS 0x7 |
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#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) |
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#define CPSW_MINOR_VERSION(reg) (reg & 0xff) |
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#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) |
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#define CPSW_VERSION_1 0x19010a |
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#define CPSW_VERSION_2 0x19010c |
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#define CPSW_VERSION_3 0x19010f |
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#define CPSW_VERSION_4 0x190112 |
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#define HOST_PORT_NUM 0 |
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#define CPSW_ALE_PORTS_NUM 3 |
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#define CPSW_SLAVE_PORTS_NUM 2 |
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#define SLIVER_SIZE 0x40 |
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#define CPSW1_HOST_PORT_OFFSET 0x028 |
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#define CPSW1_SLAVE_OFFSET 0x050 |
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#define CPSW1_SLAVE_SIZE 0x040 |
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#define CPSW1_CPDMA_OFFSET 0x100 |
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#define CPSW1_STATERAM_OFFSET 0x200 |
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#define CPSW1_HW_STATS 0x400 |
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#define CPSW1_CPTS_OFFSET 0x500 |
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#define CPSW1_ALE_OFFSET 0x600 |
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#define CPSW1_SLIVER_OFFSET 0x700 |
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#define CPSW1_WR_OFFSET 0x900 |
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#define CPSW2_HOST_PORT_OFFSET 0x108 |
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#define CPSW2_SLAVE_OFFSET 0x200 |
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#define CPSW2_SLAVE_SIZE 0x100 |
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#define CPSW2_CPDMA_OFFSET 0x800 |
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#define CPSW2_HW_STATS 0x900 |
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#define CPSW2_STATERAM_OFFSET 0xa00 |
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#define CPSW2_CPTS_OFFSET 0xc00 |
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#define CPSW2_ALE_OFFSET 0xd00 |
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#define CPSW2_SLIVER_OFFSET 0xd80 |
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#define CPSW2_BD_OFFSET 0x2000 |
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#define CPSW2_WR_OFFSET 0x1200 |
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#define CPDMA_RXTHRESH 0x0c0 |
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#define CPDMA_RXFREE 0x0e0 |
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#define CPDMA_TXHDP 0x00 |
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#define CPDMA_RXHDP 0x20 |
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#define CPDMA_TXCP 0x40 |
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#define CPDMA_RXCP 0x60 |
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#define CPSW_POLL_WEIGHT 64 |
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#define CPSW_RX_VLAN_ENCAP_HDR_SIZE 4 |
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#define CPSW_MIN_PACKET_SIZE_VLAN (VLAN_ETH_ZLEN) |
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#define CPSW_MIN_PACKET_SIZE (ETH_ZLEN) |
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#define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN +\ |
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ETH_FCS_LEN +\ |
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CPSW_RX_VLAN_ENCAP_HDR_SIZE) |
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#define RX_PRIORITY_MAPPING 0x76543210 |
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#define TX_PRIORITY_MAPPING 0x33221100 |
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#define CPDMA_TX_PRIORITY_MAP 0x76543210 |
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#define CPSW_VLAN_AWARE BIT(1) |
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#define CPSW_RX_VLAN_ENCAP BIT(2) |
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#define CPSW_ALE_VLAN_AWARE 1 |
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#define CPSW_FIFO_NORMAL_MODE (0 << 16) |
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#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) |
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#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) |
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#define CPSW_INTPACEEN (0x3f << 16) |
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#define CPSW_INTPRESCALE_MASK (0x7FF << 0) |
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#define CPSW_CMINTMAX_CNT 63 |
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#define CPSW_CMINTMIN_CNT 2 |
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#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) |
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#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) |
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#define IRQ_NUM 2 |
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#define CPSW_MAX_QUEUES 8 |
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#define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256 |
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#define CPSW_ALE_AGEOUT_DEFAULT 10 /* sec */ |
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#define CPSW_FIFO_QUEUE_TYPE_SHIFT 16 |
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#define CPSW_FIFO_SHAPE_EN_SHIFT 16 |
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#define CPSW_FIFO_RATE_EN_SHIFT 20 |
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#define CPSW_TC_NUM 4 |
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#define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1) |
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#define CPSW_PCT_MASK 0x7f |
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#define CPSW_BD_RAM_SIZE 0x2000 |
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#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29 |
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#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0) |
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#define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT 16 |
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#define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT 8 |
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#define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0) |
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enum { |
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CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0, |
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CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV, |
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CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG, |
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CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG, |
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}; |
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struct cpsw_wr_regs { |
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u32 id_ver; |
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u32 soft_reset; |
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u32 control; |
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u32 int_control; |
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u32 rx_thresh_en; |
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u32 rx_en; |
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u32 tx_en; |
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u32 misc_en; |
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u32 mem_allign1[8]; |
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u32 rx_thresh_stat; |
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u32 rx_stat; |
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u32 tx_stat; |
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u32 misc_stat; |
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u32 mem_allign2[8]; |
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u32 rx_imax; |
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u32 tx_imax; |
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}; |
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struct cpsw_ss_regs { |
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u32 id_ver; |
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u32 control; |
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u32 soft_reset; |
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u32 stat_port_en; |
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u32 ptype; |
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u32 soft_idle; |
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u32 thru_rate; |
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u32 gap_thresh; |
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u32 tx_start_wds; |
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u32 flow_control; |
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u32 vlan_ltype; |
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u32 ts_ltype; |
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u32 dlr_ltype; |
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}; |
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/* CPSW_PORT_V1 */ |
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#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ |
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#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ |
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#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ |
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#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ |
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#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ |
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#define CPSW1_TS_CTL 0x14 /* Time Sync Control */ |
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#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ |
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#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ |
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/* CPSW_PORT_V2 */ |
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#define CPSW2_CONTROL 0x00 /* Control Register */ |
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#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ |
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#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ |
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#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ |
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#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ |
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#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ |
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#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ |
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/* CPSW_PORT_V1 and V2 */ |
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#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ |
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#define SA_HI 0x24 /* CPGMAC_SL Source Address High */ |
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#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ |
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/* CPSW_PORT_V2 only */ |
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#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ |
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#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ |
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#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ |
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#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ |
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#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ |
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#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ |
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#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ |
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#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ |
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/* Bit definitions for the CPSW2_CONTROL register */ |
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#define PASS_PRI_TAGGED BIT(24) /* Pass Priority Tagged */ |
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#define VLAN_LTYPE2_EN BIT(21) /* VLAN LTYPE 2 enable */ |
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#define VLAN_LTYPE1_EN BIT(20) /* VLAN LTYPE 1 enable */ |
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#define DSCP_PRI_EN BIT(16) /* DSCP Priority Enable */ |
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#define TS_107 BIT(15) /* Tyme Sync Dest IP Address 107 */ |
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#define TS_320 BIT(14) /* Time Sync Dest Port 320 enable */ |
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#define TS_319 BIT(13) /* Time Sync Dest Port 319 enable */ |
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#define TS_132 BIT(12) /* Time Sync Dest IP Addr 132 enable */ |
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#define TS_131 BIT(11) /* Time Sync Dest IP Addr 131 enable */ |
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#define TS_130 BIT(10) /* Time Sync Dest IP Addr 130 enable */ |
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#define TS_129 BIT(9) /* Time Sync Dest IP Addr 129 enable */ |
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#define TS_TTL_NONZERO BIT(8) /* Time Sync Time To Live Non-zero enable */ |
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#define TS_ANNEX_F_EN BIT(6) /* Time Sync Annex F enable */ |
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#define TS_ANNEX_D_EN BIT(4) /* Time Sync Annex D enable */ |
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#define TS_LTYPE2_EN BIT(3) /* Time Sync LTYPE 2 enable */ |
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#define TS_LTYPE1_EN BIT(2) /* Time Sync LTYPE 1 enable */ |
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#define TS_TX_EN BIT(1) /* Time Sync Transmit Enable */ |
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#define TS_RX_EN BIT(0) /* Time Sync Receive Enable */ |
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#define CTRL_V2_TS_BITS \ |
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(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ |
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TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN | VLAN_LTYPE1_EN) |
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#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) |
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#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) |
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#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) |
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#define CTRL_V3_TS_BITS \ |
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(TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ |
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TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ |
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TS_LTYPE1_EN | VLAN_LTYPE1_EN) |
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#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) |
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#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) |
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#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) |
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/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ |
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#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ |
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#define TS_SEQ_ID_OFFSET_MASK (0x3f) |
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#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ |
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#define TS_MSG_TYPE_EN_MASK (0xffff) |
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/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ |
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#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) |
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/* Bit definitions for the CPSW1_TS_CTL register */ |
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#define CPSW_V1_TS_RX_EN BIT(0) |
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#define CPSW_V1_TS_TX_EN BIT(4) |
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#define CPSW_V1_MSG_TYPE_OFS 16 |
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/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ |
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#define CPSW_V1_SEQ_ID_OFS_SHIFT 16 |
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#define CPSW_MAX_BLKS_TX 15 |
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#define CPSW_MAX_BLKS_TX_SHIFT 4 |
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#define CPSW_MAX_BLKS_RX 5 |
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struct cpsw_host_regs { |
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u32 max_blks; |
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u32 blk_cnt; |
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u32 tx_in_ctl; |
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u32 port_vlan; |
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u32 tx_pri_map; |
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u32 cpdma_tx_pri_map; |
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u32 cpdma_rx_chan_map; |
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}; |
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struct cpsw_slave_data { |
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struct device_node *slave_node; |
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struct device_node *phy_node; |
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char phy_id[MII_BUS_ID_SIZE]; |
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phy_interface_t phy_if; |
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u8 mac_addr[ETH_ALEN]; |
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u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */ |
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struct phy *ifphy; |
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bool disabled; |
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}; |
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struct cpsw_platform_data { |
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struct cpsw_slave_data *slave_data; |
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u32 ss_reg_ofs; /* Subsystem control register offset */ |
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u32 channels; /* number of cpdma channels (symmetric) */ |
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u32 slaves; /* number of slave cpgmac ports */ |
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u32 active_slave;/* time stamping, ethtool and SIOCGMIIPHY slave */ |
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u32 bd_ram_size; /*buffer descriptor ram size */ |
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u32 mac_control; /* Mac control register */ |
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u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/ |
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bool dual_emac; /* Enable Dual EMAC mode */ |
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}; |
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struct cpsw_slave { |
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void __iomem *regs; |
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int slave_num; |
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u32 mac_control; |
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struct cpsw_slave_data *data; |
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struct phy_device *phy; |
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struct net_device *ndev; |
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u32 port_vlan; |
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struct cpsw_sl *mac_sl; |
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}; |
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static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) |
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{ |
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return readl_relaxed(slave->regs + offset); |
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} |
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static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) |
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{ |
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writel_relaxed(val, slave->regs + offset); |
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} |
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struct cpsw_vector { |
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struct cpdma_chan *ch; |
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int budget; |
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}; |
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struct cpsw_common { |
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struct device *dev; |
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struct cpsw_platform_data data; |
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struct napi_struct napi_rx; |
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struct napi_struct napi_tx; |
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struct cpsw_ss_regs __iomem *regs; |
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struct cpsw_wr_regs __iomem *wr_regs; |
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u8 __iomem *hw_stats; |
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struct cpsw_host_regs __iomem *host_port_regs; |
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u32 version; |
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u32 coal_intvl; |
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u32 bus_freq_mhz; |
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int rx_packet_max; |
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int descs_pool_size; |
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struct cpsw_slave *slaves; |
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struct cpdma_ctlr *dma; |
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struct cpsw_vector txv[CPSW_MAX_QUEUES]; |
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struct cpsw_vector rxv[CPSW_MAX_QUEUES]; |
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struct cpsw_ale *ale; |
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bool quirk_irq; |
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bool rx_irq_disabled; |
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bool tx_irq_disabled; |
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u32 irqs_table[IRQ_NUM]; |
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int misc_irq; |
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struct cpts *cpts; |
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struct devlink *devlink; |
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int rx_ch_num, tx_ch_num; |
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int speed; |
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int usage_count; |
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struct page_pool *page_pool[CPSW_MAX_QUEUES]; |
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u8 br_members; |
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struct net_device *hw_bridge_dev; |
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bool ale_bypass; |
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u8 base_mac[ETH_ALEN]; |
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}; |
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struct cpsw_priv { |
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struct net_device *ndev; |
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struct device *dev; |
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u32 msg_enable; |
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u8 mac_addr[ETH_ALEN]; |
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bool rx_pause; |
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bool tx_pause; |
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bool mqprio_hw; |
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int fifo_bw[CPSW_TC_NUM]; |
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int shp_cfg_speed; |
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int tx_ts_enabled; |
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int rx_ts_enabled; |
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struct bpf_prog *xdp_prog; |
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struct xdp_rxq_info xdp_rxq[CPSW_MAX_QUEUES]; |
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struct xdp_attachment_info xdpi; |
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u32 emac_port; |
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struct cpsw_common *cpsw; |
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int offload_fwd_mark; |
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u32 tx_packet_min; |
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}; |
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#define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw) |
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#define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi) |
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extern int (*cpsw_slave_index)(struct cpsw_common *cpsw, |
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struct cpsw_priv *priv); |
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struct addr_sync_ctx { |
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struct net_device *ndev; |
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const u8 *addr; /* address to be synched */ |
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int consumed; /* number of address instances */ |
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int flush; /* flush flag */ |
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}; |
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#define CPSW_XMETA_OFFSET ALIGN(sizeof(struct xdp_frame), sizeof(long)) |
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#define CPSW_XDP_CONSUMED 1 |
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#define CPSW_XDP_PASS 0 |
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struct __aligned(sizeof(long)) cpsw_meta_xdp { |
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struct net_device *ndev; |
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int ch; |
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}; |
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/* The buf includes headroom compatible with both skb and xdpf */ |
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#define CPSW_HEADROOM_NA (max(XDP_PACKET_HEADROOM, NET_SKB_PAD) + NET_IP_ALIGN) |
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#define CPSW_HEADROOM ALIGN(CPSW_HEADROOM_NA, sizeof(long)) |
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static inline int cpsw_is_xdpf_handle(void *handle) |
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{ |
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return (unsigned long)handle & BIT(0); |
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} |
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static inline void *cpsw_xdpf_to_handle(struct xdp_frame *xdpf) |
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{ |
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return (void *)((unsigned long)xdpf | BIT(0)); |
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} |
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static inline struct xdp_frame *cpsw_handle_to_xdpf(void *handle) |
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{ |
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return (struct xdp_frame *)((unsigned long)handle & ~BIT(0)); |
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} |
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int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs, |
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int ale_ageout, phys_addr_t desc_mem_phys, |
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int descs_pool_size); |
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void cpsw_split_res(struct cpsw_common *cpsw); |
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int cpsw_fill_rx_channels(struct cpsw_priv *priv); |
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void cpsw_intr_enable(struct cpsw_common *cpsw); |
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void cpsw_intr_disable(struct cpsw_common *cpsw); |
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void cpsw_tx_handler(void *token, int len, int status); |
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int cpsw_create_xdp_rxqs(struct cpsw_common *cpsw); |
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void cpsw_destroy_xdp_rxqs(struct cpsw_common *cpsw); |
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int cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf); |
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int cpsw_xdp_tx_frame(struct cpsw_priv *priv, struct xdp_frame *xdpf, |
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struct page *page, int port); |
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int cpsw_run_xdp(struct cpsw_priv *priv, int ch, struct xdp_buff *xdp, |
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struct page *page, int port, int *len); |
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irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id); |
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irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id); |
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irqreturn_t cpsw_misc_interrupt(int irq, void *dev_id); |
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int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget); |
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int cpsw_tx_poll(struct napi_struct *napi_tx, int budget); |
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int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget); |
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int cpsw_rx_poll(struct napi_struct *napi_rx, int budget); |
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void cpsw_rx_vlan_encap(struct sk_buff *skb); |
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void soft_reset(const char *module, void __iomem *reg); |
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void cpsw_set_slave_mac(struct cpsw_slave *slave, struct cpsw_priv *priv); |
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void cpsw_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue); |
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int cpsw_need_resplit(struct cpsw_common *cpsw); |
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int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd); |
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int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate); |
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int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type, |
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void *type_data); |
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bool cpsw_shp_is_off(struct cpsw_priv *priv); |
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void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv); |
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void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv); |
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/* ethtool */ |
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u32 cpsw_get_msglevel(struct net_device *ndev); |
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void cpsw_set_msglevel(struct net_device *ndev, u32 value); |
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int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal, |
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struct kernel_ethtool_coalesce *kernel_coal, |
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struct netlink_ext_ack *extack); |
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int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal, |
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struct kernel_ethtool_coalesce *kernel_coal, |
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struct netlink_ext_ack *extack); |
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int cpsw_get_sset_count(struct net_device *ndev, int sset); |
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void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data); |
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void cpsw_get_ethtool_stats(struct net_device *ndev, |
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struct ethtool_stats *stats, u64 *data); |
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void cpsw_get_pauseparam(struct net_device *ndev, |
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struct ethtool_pauseparam *pause); |
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void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol); |
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int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol); |
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int cpsw_get_regs_len(struct net_device *ndev); |
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void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p); |
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int cpsw_ethtool_op_begin(struct net_device *ndev); |
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void cpsw_ethtool_op_complete(struct net_device *ndev); |
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void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch); |
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int cpsw_get_link_ksettings(struct net_device *ndev, |
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struct ethtool_link_ksettings *ecmd); |
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int cpsw_set_link_ksettings(struct net_device *ndev, |
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const struct ethtool_link_ksettings *ecmd); |
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int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata); |
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int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata); |
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int cpsw_nway_reset(struct net_device *ndev); |
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void cpsw_get_ringparam(struct net_device *ndev, |
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struct ethtool_ringparam *ering); |
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int cpsw_set_ringparam(struct net_device *ndev, |
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struct ethtool_ringparam *ering); |
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int cpsw_set_channels_common(struct net_device *ndev, |
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struct ethtool_channels *chs, |
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cpdma_handler_fn rx_handler); |
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int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info); |
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#endif /* DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ */
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