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365 lines
10 KiB
365 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* 10G controller driver for Samsung SoCs |
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* |
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* Copyright (C) 2013 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com |
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* |
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* Author: Siva Reddy Kallam <[email protected]> |
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*/ |
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#include <linux/delay.h> |
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#include <linux/export.h> |
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#include <linux/io.h> |
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#include <linux/netdevice.h> |
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#include <linux/phy.h> |
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#include "sxgbe_common.h" |
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#include "sxgbe_dma.h" |
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#include "sxgbe_reg.h" |
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#include "sxgbe_desc.h" |
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/* DMA core initialization */ |
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static int sxgbe_dma_init(void __iomem *ioaddr, int fix_burst, int burst_map) |
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{ |
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u32 reg_val; |
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reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); |
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/* if fix_burst = 0, Set UNDEF = 1 of DMA_Sys_Mode Register. |
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* if fix_burst = 1, Set UNDEF = 0 of DMA_Sys_Mode Register. |
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* burst_map is bitmap for BLEN[4, 8, 16, 32, 64, 128 and 256]. |
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* Set burst_map irrespective of fix_burst value. |
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*/ |
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if (!fix_burst) |
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reg_val |= SXGBE_DMA_AXI_UNDEF_BURST; |
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/* write burst len map */ |
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reg_val |= (burst_map << SXGBE_DMA_BLENMAP_LSHIFT); |
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writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); |
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return 0; |
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} |
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static void sxgbe_dma_channel_init(void __iomem *ioaddr, int cha_num, |
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int fix_burst, int pbl, dma_addr_t dma_tx, |
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dma_addr_t dma_rx, int t_rsize, int r_rsize) |
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{ |
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u32 reg_val; |
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dma_addr_t dma_addr; |
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reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); |
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/* set the pbl */ |
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if (fix_burst) { |
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reg_val |= SXGBE_DMA_PBL_X8MODE; |
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writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); |
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/* program the TX pbl */ |
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reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); |
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reg_val |= (pbl << SXGBE_DMA_TXPBL_LSHIFT); |
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writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); |
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/* program the RX pbl */ |
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reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); |
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reg_val |= (pbl << SXGBE_DMA_RXPBL_LSHIFT); |
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writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); |
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} |
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/* program desc registers */ |
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writel(upper_32_bits(dma_tx), |
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ioaddr + SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num)); |
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writel(lower_32_bits(dma_tx), |
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ioaddr + SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num)); |
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writel(upper_32_bits(dma_rx), |
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ioaddr + SXGBE_DMA_CHA_RXDESC_HADD_REG(cha_num)); |
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writel(lower_32_bits(dma_rx), |
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ioaddr + SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num)); |
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/* program tail pointers */ |
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/* assumption: upper 32 bits are constant and |
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* same as TX/RX desc list |
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*/ |
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dma_addr = dma_tx + ((t_rsize - 1) * SXGBE_DESC_SIZE_BYTES); |
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writel(lower_32_bits(dma_addr), |
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ioaddr + SXGBE_DMA_CHA_TXDESC_TAILPTR_REG(cha_num)); |
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dma_addr = dma_rx + ((r_rsize - 1) * SXGBE_DESC_SIZE_BYTES); |
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writel(lower_32_bits(dma_addr), |
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ioaddr + SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num)); |
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/* program the ring sizes */ |
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writel(t_rsize - 1, ioaddr + SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num)); |
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writel(r_rsize - 1, ioaddr + SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num)); |
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/* Enable TX/RX interrupts */ |
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writel(SXGBE_DMA_ENA_INT, |
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ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(cha_num)); |
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} |
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static void sxgbe_enable_dma_transmission(void __iomem *ioaddr, int cha_num) |
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{ |
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u32 tx_config; |
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tx_config = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); |
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tx_config |= SXGBE_TX_START_DMA; |
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writel(tx_config, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); |
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} |
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static void sxgbe_enable_dma_irq(void __iomem *ioaddr, int dma_cnum) |
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{ |
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/* Enable TX/RX interrupts */ |
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writel(SXGBE_DMA_ENA_INT, |
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ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(dma_cnum)); |
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} |
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static void sxgbe_disable_dma_irq(void __iomem *ioaddr, int dma_cnum) |
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{ |
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/* Disable TX/RX interrupts */ |
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writel(0, ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(dma_cnum)); |
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} |
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static void sxgbe_dma_start_tx(void __iomem *ioaddr, int tchannels) |
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{ |
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int cnum; |
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u32 tx_ctl_reg; |
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for (cnum = 0; cnum < tchannels; cnum++) { |
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tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); |
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tx_ctl_reg |= SXGBE_TX_ENABLE; |
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writel(tx_ctl_reg, |
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ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); |
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} |
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} |
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static void sxgbe_dma_start_tx_queue(void __iomem *ioaddr, int dma_cnum) |
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{ |
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u32 tx_ctl_reg; |
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tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); |
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tx_ctl_reg |= SXGBE_TX_ENABLE; |
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writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); |
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} |
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static void sxgbe_dma_stop_tx_queue(void __iomem *ioaddr, int dma_cnum) |
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{ |
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u32 tx_ctl_reg; |
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tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); |
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tx_ctl_reg &= ~(SXGBE_TX_ENABLE); |
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writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); |
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} |
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static void sxgbe_dma_stop_tx(void __iomem *ioaddr, int tchannels) |
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{ |
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int cnum; |
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u32 tx_ctl_reg; |
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for (cnum = 0; cnum < tchannels; cnum++) { |
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tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); |
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tx_ctl_reg &= ~(SXGBE_TX_ENABLE); |
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writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); |
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} |
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} |
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static void sxgbe_dma_start_rx(void __iomem *ioaddr, int rchannels) |
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{ |
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int cnum; |
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u32 rx_ctl_reg; |
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for (cnum = 0; cnum < rchannels; cnum++) { |
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rx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); |
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rx_ctl_reg |= SXGBE_RX_ENABLE; |
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writel(rx_ctl_reg, |
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ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); |
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} |
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} |
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static void sxgbe_dma_stop_rx(void __iomem *ioaddr, int rchannels) |
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{ |
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int cnum; |
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u32 rx_ctl_reg; |
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for (cnum = 0; cnum < rchannels; cnum++) { |
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rx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); |
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rx_ctl_reg &= ~(SXGBE_RX_ENABLE); |
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writel(rx_ctl_reg, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); |
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} |
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} |
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static int sxgbe_tx_dma_int_status(void __iomem *ioaddr, int channel_no, |
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struct sxgbe_extra_stats *x) |
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{ |
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u32 int_status = readl(ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); |
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u32 clear_val = 0; |
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u32 ret_val = 0; |
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/* TX Normal Interrupt Summary */ |
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if (likely(int_status & SXGBE_DMA_INT_STATUS_NIS)) { |
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x->normal_irq_n++; |
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if (int_status & SXGBE_DMA_INT_STATUS_TI) { |
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ret_val |= handle_tx; |
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x->tx_normal_irq_n++; |
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clear_val |= SXGBE_DMA_INT_STATUS_TI; |
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} |
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if (int_status & SXGBE_DMA_INT_STATUS_TBU) { |
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x->tx_underflow_irq++; |
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ret_val |= tx_bump_tc; |
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clear_val |= SXGBE_DMA_INT_STATUS_TBU; |
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} |
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} else if (unlikely(int_status & SXGBE_DMA_INT_STATUS_AIS)) { |
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/* TX Abnormal Interrupt Summary */ |
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if (int_status & SXGBE_DMA_INT_STATUS_TPS) { |
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ret_val |= tx_hard_error; |
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clear_val |= SXGBE_DMA_INT_STATUS_TPS; |
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x->tx_process_stopped_irq++; |
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} |
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if (int_status & SXGBE_DMA_INT_STATUS_FBE) { |
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ret_val |= tx_hard_error; |
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x->fatal_bus_error_irq++; |
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/* Assumption: FBE bit is the combination of |
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* all the bus access erros and cleared when |
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* the respective error bits cleared |
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*/ |
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/* check for actual cause */ |
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if (int_status & SXGBE_DMA_INT_STATUS_TEB0) { |
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x->tx_read_transfer_err++; |
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clear_val |= SXGBE_DMA_INT_STATUS_TEB0; |
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} else { |
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x->tx_write_transfer_err++; |
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} |
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if (int_status & SXGBE_DMA_INT_STATUS_TEB1) { |
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x->tx_desc_access_err++; |
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clear_val |= SXGBE_DMA_INT_STATUS_TEB1; |
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} else { |
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x->tx_buffer_access_err++; |
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} |
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if (int_status & SXGBE_DMA_INT_STATUS_TEB2) { |
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x->tx_data_transfer_err++; |
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clear_val |= SXGBE_DMA_INT_STATUS_TEB2; |
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} |
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} |
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/* context descriptor error */ |
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if (int_status & SXGBE_DMA_INT_STATUS_CTXTERR) { |
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x->tx_ctxt_desc_err++; |
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clear_val |= SXGBE_DMA_INT_STATUS_CTXTERR; |
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} |
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} |
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/* clear the served bits */ |
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writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); |
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return ret_val; |
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} |
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static int sxgbe_rx_dma_int_status(void __iomem *ioaddr, int channel_no, |
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struct sxgbe_extra_stats *x) |
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{ |
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u32 int_status = readl(ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); |
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u32 clear_val = 0; |
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u32 ret_val = 0; |
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/* RX Normal Interrupt Summary */ |
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if (likely(int_status & SXGBE_DMA_INT_STATUS_NIS)) { |
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x->normal_irq_n++; |
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if (int_status & SXGBE_DMA_INT_STATUS_RI) { |
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ret_val |= handle_rx; |
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x->rx_normal_irq_n++; |
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clear_val |= SXGBE_DMA_INT_STATUS_RI; |
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} |
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} else if (unlikely(int_status & SXGBE_DMA_INT_STATUS_AIS)) { |
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/* RX Abnormal Interrupt Summary */ |
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if (int_status & SXGBE_DMA_INT_STATUS_RBU) { |
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ret_val |= rx_bump_tc; |
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clear_val |= SXGBE_DMA_INT_STATUS_RBU; |
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x->rx_underflow_irq++; |
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} |
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if (int_status & SXGBE_DMA_INT_STATUS_RPS) { |
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ret_val |= rx_hard_error; |
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clear_val |= SXGBE_DMA_INT_STATUS_RPS; |
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x->rx_process_stopped_irq++; |
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} |
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if (int_status & SXGBE_DMA_INT_STATUS_FBE) { |
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ret_val |= rx_hard_error; |
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x->fatal_bus_error_irq++; |
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/* Assumption: FBE bit is the combination of |
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* all the bus access erros and cleared when |
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* the respective error bits cleared |
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*/ |
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/* check for actual cause */ |
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if (int_status & SXGBE_DMA_INT_STATUS_REB0) { |
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x->rx_read_transfer_err++; |
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clear_val |= SXGBE_DMA_INT_STATUS_REB0; |
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} else { |
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x->rx_write_transfer_err++; |
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} |
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if (int_status & SXGBE_DMA_INT_STATUS_REB1) { |
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x->rx_desc_access_err++; |
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clear_val |= SXGBE_DMA_INT_STATUS_REB1; |
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} else { |
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x->rx_buffer_access_err++; |
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} |
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if (int_status & SXGBE_DMA_INT_STATUS_REB2) { |
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x->rx_data_transfer_err++; |
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clear_val |= SXGBE_DMA_INT_STATUS_REB2; |
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} |
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} |
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} |
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/* clear the served bits */ |
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writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); |
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return ret_val; |
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} |
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/* Program the HW RX Watchdog */ |
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static void sxgbe_dma_rx_watchdog(void __iomem *ioaddr, u32 riwt) |
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{ |
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u32 que_num; |
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SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, que_num) { |
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writel(riwt, |
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ioaddr + SXGBE_DMA_CHA_INT_RXWATCHTMR_REG(que_num)); |
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} |
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} |
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static void sxgbe_enable_tso(void __iomem *ioaddr, u8 chan_num) |
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{ |
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u32 ctrl; |
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ctrl = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num)); |
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ctrl |= SXGBE_DMA_CHA_TXCTL_TSE_ENABLE; |
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writel(ctrl, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num)); |
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} |
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static const struct sxgbe_dma_ops sxgbe_dma_ops = { |
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.init = sxgbe_dma_init, |
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.cha_init = sxgbe_dma_channel_init, |
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.enable_dma_transmission = sxgbe_enable_dma_transmission, |
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.enable_dma_irq = sxgbe_enable_dma_irq, |
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.disable_dma_irq = sxgbe_disable_dma_irq, |
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.start_tx = sxgbe_dma_start_tx, |
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.start_tx_queue = sxgbe_dma_start_tx_queue, |
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.stop_tx = sxgbe_dma_stop_tx, |
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.stop_tx_queue = sxgbe_dma_stop_tx_queue, |
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.start_rx = sxgbe_dma_start_rx, |
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.stop_rx = sxgbe_dma_stop_rx, |
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.tx_dma_int_status = sxgbe_tx_dma_int_status, |
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.rx_dma_int_status = sxgbe_rx_dma_int_status, |
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.rx_watchdog = sxgbe_dma_rx_watchdog, |
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.enable_tso = sxgbe_enable_tso, |
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}; |
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const struct sxgbe_dma_ops *sxgbe_get_dma_ops(void) |
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{ |
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return &sxgbe_dma_ops; |
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}
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