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532 lines
15 KiB
532 lines
15 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* 10G controller driver for Samsung SoCs |
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* |
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* Copyright (C) 2013 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com |
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* |
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* Author: Siva Reddy Kallam <[email protected]> |
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*/ |
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#ifndef __SXGBE_COMMON_H__ |
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#define __SXGBE_COMMON_H__ |
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/* forward references */ |
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struct sxgbe_desc_ops; |
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struct sxgbe_dma_ops; |
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struct sxgbe_mtl_ops; |
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#define SXGBE_RESOURCE_NAME "sam_sxgbeeth" |
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#define DRV_MODULE_VERSION "November_2013" |
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/* MAX HW feature words */ |
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#define SXGBE_HW_WORDS 3 |
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#define SXGBE_RX_COE_NONE 0 |
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/* CSR Frequency Access Defines*/ |
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#define SXGBE_CSR_F_150M 150000000 |
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#define SXGBE_CSR_F_250M 250000000 |
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#define SXGBE_CSR_F_300M 300000000 |
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#define SXGBE_CSR_F_350M 350000000 |
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#define SXGBE_CSR_F_400M 400000000 |
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#define SXGBE_CSR_F_500M 500000000 |
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/* pause time */ |
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#define SXGBE_PAUSE_TIME 0x200 |
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/* tx queues */ |
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#define SXGBE_TX_QUEUES 8 |
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#define SXGBE_RX_QUEUES 16 |
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/* Calculated based how much time does it take to fill 256KB Rx memory |
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* at 10Gb speed at 156MHz clock rate and considered little less then |
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* the actual value. |
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*/ |
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#define SXGBE_MAX_DMA_RIWT 0x70 |
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#define SXGBE_MIN_DMA_RIWT 0x01 |
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/* Tx coalesce parameters */ |
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#define SXGBE_COAL_TX_TIMER 40000 |
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#define SXGBE_MAX_COAL_TX_TICK 100000 |
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#define SXGBE_TX_MAX_FRAMES 512 |
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#define SXGBE_TX_FRAMES 128 |
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/* SXGBE TX FIFO is 8K, Rx FIFO is 16K */ |
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#define BUF_SIZE_16KiB 16384 |
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#define BUF_SIZE_8KiB 8192 |
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#define BUF_SIZE_4KiB 4096 |
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#define BUF_SIZE_2KiB 2048 |
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#define SXGBE_DEFAULT_LIT_LS 0x3E8 |
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#define SXGBE_DEFAULT_TWT_LS 0x0 |
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/* Flow Control defines */ |
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#define SXGBE_FLOW_OFF 0 |
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#define SXGBE_FLOW_RX 1 |
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#define SXGBE_FLOW_TX 2 |
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#define SXGBE_FLOW_AUTO (SXGBE_FLOW_TX | SXGBE_FLOW_RX) |
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#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ |
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/* errors */ |
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#define RX_GMII_ERR 0x01 |
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#define RX_WATCHDOG_ERR 0x02 |
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#define RX_CRC_ERR 0x03 |
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#define RX_GAINT_ERR 0x04 |
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#define RX_IP_HDR_ERR 0x05 |
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#define RX_PAYLOAD_ERR 0x06 |
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#define RX_OVERFLOW_ERR 0x07 |
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/* pkt type */ |
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#define RX_LEN_PKT 0x00 |
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#define RX_MACCTL_PKT 0x01 |
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#define RX_DCBCTL_PKT 0x02 |
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#define RX_ARP_PKT 0x03 |
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#define RX_OAM_PKT 0x04 |
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#define RX_UNTAG_PKT 0x05 |
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#define RX_OTHER_PKT 0x07 |
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#define RX_SVLAN_PKT 0x08 |
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#define RX_CVLAN_PKT 0x09 |
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#define RX_DVLAN_OCVLAN_ICVLAN_PKT 0x0A |
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#define RX_DVLAN_OSVLAN_ISVLAN_PKT 0x0B |
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#define RX_DVLAN_OSVLAN_ICVLAN_PKT 0x0C |
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#define RX_DVLAN_OCVLAN_ISVLAN_PKT 0x0D |
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#define RX_NOT_IP_PKT 0x00 |
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#define RX_IPV4_TCP_PKT 0x01 |
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#define RX_IPV4_UDP_PKT 0x02 |
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#define RX_IPV4_ICMP_PKT 0x03 |
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#define RX_IPV4_UNKNOWN_PKT 0x07 |
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#define RX_IPV6_TCP_PKT 0x09 |
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#define RX_IPV6_UDP_PKT 0x0A |
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#define RX_IPV6_ICMP_PKT 0x0B |
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#define RX_IPV6_UNKNOWN_PKT 0x0F |
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#define RX_NO_PTP 0x00 |
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#define RX_PTP_SYNC 0x01 |
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#define RX_PTP_FOLLOW_UP 0x02 |
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#define RX_PTP_DELAY_REQ 0x03 |
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#define RX_PTP_DELAY_RESP 0x04 |
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#define RX_PTP_PDELAY_REQ 0x05 |
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#define RX_PTP_PDELAY_RESP 0x06 |
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#define RX_PTP_PDELAY_FOLLOW_UP 0x07 |
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#define RX_PTP_ANNOUNCE 0x08 |
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#define RX_PTP_MGMT 0x09 |
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#define RX_PTP_SIGNAL 0x0A |
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#define RX_PTP_RESV_MSG 0x0F |
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/* EEE-LPI mode flags*/ |
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#define TX_ENTRY_LPI_MODE 0x10 |
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#define TX_EXIT_LPI_MODE 0x20 |
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#define RX_ENTRY_LPI_MODE 0x40 |
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#define RX_EXIT_LPI_MODE 0x80 |
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/* EEE-LPI Interrupt status flag */ |
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#define LPI_INT_STATUS BIT(5) |
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/* EEE-LPI Default timer values */ |
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#define LPI_LINK_STATUS_TIMER 0x3E8 |
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#define LPI_MAC_WAIT_TIMER 0x00 |
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/* EEE-LPI Control and status definitions */ |
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#define LPI_CTRL_STATUS_TXA BIT(19) |
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#define LPI_CTRL_STATUS_PLSDIS BIT(18) |
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#define LPI_CTRL_STATUS_PLS BIT(17) |
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#define LPI_CTRL_STATUS_LPIEN BIT(16) |
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#define LPI_CTRL_STATUS_TXRSTP BIT(11) |
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#define LPI_CTRL_STATUS_RXRSTP BIT(10) |
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#define LPI_CTRL_STATUS_RLPIST BIT(9) |
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#define LPI_CTRL_STATUS_TLPIST BIT(8) |
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#define LPI_CTRL_STATUS_RLPIEX BIT(3) |
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#define LPI_CTRL_STATUS_RLPIEN BIT(2) |
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#define LPI_CTRL_STATUS_TLPIEX BIT(1) |
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#define LPI_CTRL_STATUS_TLPIEN BIT(0) |
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enum dma_irq_status { |
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tx_hard_error = BIT(0), |
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tx_bump_tc = BIT(1), |
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handle_tx = BIT(2), |
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rx_hard_error = BIT(3), |
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rx_bump_tc = BIT(4), |
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handle_rx = BIT(5), |
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}; |
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#define NETIF_F_HW_VLAN_ALL (NETIF_F_HW_VLAN_CTAG_RX | \ |
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NETIF_F_HW_VLAN_STAG_RX | \ |
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NETIF_F_HW_VLAN_CTAG_TX | \ |
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NETIF_F_HW_VLAN_STAG_TX | \ |
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NETIF_F_HW_VLAN_CTAG_FILTER | \ |
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NETIF_F_HW_VLAN_STAG_FILTER) |
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/* MMC control defines */ |
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#define SXGBE_MMC_CTRL_CNT_FRZ 0x00000008 |
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/* SXGBE HW ADDR regs */ |
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#define SXGBE_ADDR_HIGH(reg) (((reg > 15) ? 0x00000800 : 0x00000040) + \ |
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(reg * 8)) |
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#define SXGBE_ADDR_LOW(reg) (((reg > 15) ? 0x00000804 : 0x00000044) + \ |
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(reg * 8)) |
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#define SXGBE_MAX_PERFECT_ADDRESSES 32 /* Maximum unicast perfect filtering */ |
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#define SXGBE_FRAME_FILTER 0x00000004 /* Frame Filter */ |
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/* SXGBE Frame Filter defines */ |
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#define SXGBE_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */ |
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#define SXGBE_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */ |
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#define SXGBE_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */ |
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#define SXGBE_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */ |
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#define SXGBE_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */ |
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#define SXGBE_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */ |
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#define SXGBE_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */ |
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#define SXGBE_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */ |
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#define SXGBE_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */ |
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#define SXGBE_FRAME_FILTER_RA 0x80000000 /* Receive all mode */ |
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#define SXGBE_HASH_TABLE_SIZE 64 |
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#define SXGBE_HASH_HIGH 0x00000008 /* Multicast Hash Table High */ |
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#define SXGBE_HASH_LOW 0x0000000c /* Multicast Hash Table Low */ |
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#define SXGBE_HI_REG_AE 0x80000000 |
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/* Minimum and maximum MTU */ |
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#define MIN_MTU 68 |
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#define MAX_MTU 9000 |
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#define SXGBE_FOR_EACH_QUEUE(max_queues, queue_num) \ |
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for (queue_num = 0; queue_num < max_queues; queue_num++) |
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#define DRV_VERSION "1.0.0" |
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#define SXGBE_MAX_RX_CHANNELS 16 |
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#define SXGBE_MAX_TX_CHANNELS 16 |
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#define START_MAC_REG_OFFSET 0x0000 |
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#define MAX_MAC_REG_OFFSET 0x0DFC |
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#define START_MTL_REG_OFFSET 0x1000 |
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#define MAX_MTL_REG_OFFSET 0x18FC |
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#define START_DMA_REG_OFFSET 0x3000 |
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#define MAX_DMA_REG_OFFSET 0x38FC |
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#define REG_SPACE_SIZE 0x2000 |
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/* sxgbe statistics counters */ |
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struct sxgbe_extra_stats { |
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/* TX/RX IRQ events */ |
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unsigned long tx_underflow_irq; |
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unsigned long tx_process_stopped_irq; |
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unsigned long tx_ctxt_desc_err; |
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unsigned long tx_threshold; |
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unsigned long rx_threshold; |
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unsigned long tx_pkt_n; |
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unsigned long rx_pkt_n; |
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unsigned long normal_irq_n; |
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unsigned long tx_normal_irq_n; |
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unsigned long rx_normal_irq_n; |
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unsigned long napi_poll; |
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unsigned long tx_clean; |
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unsigned long tx_reset_ic_bit; |
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unsigned long rx_process_stopped_irq; |
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unsigned long rx_underflow_irq; |
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/* Bus access errors */ |
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unsigned long fatal_bus_error_irq; |
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unsigned long tx_read_transfer_err; |
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unsigned long tx_write_transfer_err; |
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unsigned long tx_desc_access_err; |
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unsigned long tx_buffer_access_err; |
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unsigned long tx_data_transfer_err; |
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unsigned long rx_read_transfer_err; |
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unsigned long rx_write_transfer_err; |
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unsigned long rx_desc_access_err; |
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unsigned long rx_buffer_access_err; |
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unsigned long rx_data_transfer_err; |
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/* EEE-LPI stats */ |
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unsigned long tx_lpi_entry_n; |
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unsigned long tx_lpi_exit_n; |
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unsigned long rx_lpi_entry_n; |
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unsigned long rx_lpi_exit_n; |
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unsigned long eee_wakeup_error_n; |
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/* RX specific */ |
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/* L2 error */ |
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unsigned long rx_code_gmii_err; |
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unsigned long rx_watchdog_err; |
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unsigned long rx_crc_err; |
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unsigned long rx_gaint_pkt_err; |
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unsigned long ip_hdr_err; |
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unsigned long ip_payload_err; |
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unsigned long overflow_error; |
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/* L2 Pkt type */ |
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unsigned long len_pkt; |
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unsigned long mac_ctl_pkt; |
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unsigned long dcb_ctl_pkt; |
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unsigned long arp_pkt; |
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unsigned long oam_pkt; |
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unsigned long untag_okt; |
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unsigned long other_pkt; |
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unsigned long svlan_tag_pkt; |
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unsigned long cvlan_tag_pkt; |
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unsigned long dvlan_ocvlan_icvlan_pkt; |
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unsigned long dvlan_osvlan_isvlan_pkt; |
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unsigned long dvlan_osvlan_icvlan_pkt; |
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unsigned long dvan_ocvlan_icvlan_pkt; |
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/* L3/L4 Pkt type */ |
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unsigned long not_ip_pkt; |
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unsigned long ip4_tcp_pkt; |
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unsigned long ip4_udp_pkt; |
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unsigned long ip4_icmp_pkt; |
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unsigned long ip4_unknown_pkt; |
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unsigned long ip6_tcp_pkt; |
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unsigned long ip6_udp_pkt; |
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unsigned long ip6_icmp_pkt; |
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unsigned long ip6_unknown_pkt; |
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/* Filter specific */ |
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unsigned long vlan_filter_match; |
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unsigned long sa_filter_fail; |
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unsigned long da_filter_fail; |
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unsigned long hash_filter_pass; |
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unsigned long l3_filter_match; |
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unsigned long l4_filter_match; |
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/* RX context specific */ |
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unsigned long timestamp_dropped; |
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unsigned long rx_msg_type_no_ptp; |
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unsigned long rx_ptp_type_sync; |
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unsigned long rx_ptp_type_follow_up; |
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unsigned long rx_ptp_type_delay_req; |
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unsigned long rx_ptp_type_delay_resp; |
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unsigned long rx_ptp_type_pdelay_req; |
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unsigned long rx_ptp_type_pdelay_resp; |
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unsigned long rx_ptp_type_pdelay_follow_up; |
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unsigned long rx_ptp_announce; |
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unsigned long rx_ptp_mgmt; |
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unsigned long rx_ptp_signal; |
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unsigned long rx_ptp_resv_msg_type; |
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}; |
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struct mac_link { |
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int port; |
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int duplex; |
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int speed; |
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}; |
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struct mii_regs { |
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unsigned int addr; /* MII Address */ |
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unsigned int data; /* MII Data */ |
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}; |
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struct sxgbe_core_ops { |
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/* MAC core initialization */ |
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void (*core_init)(void __iomem *ioaddr); |
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/* Dump MAC registers */ |
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void (*dump_regs)(void __iomem *ioaddr); |
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/* Handle extra events on specific interrupts hw dependent */ |
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int (*host_irq_status)(void __iomem *ioaddr, |
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struct sxgbe_extra_stats *x); |
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/* Set power management mode (e.g. magic frame) */ |
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void (*pmt)(void __iomem *ioaddr, unsigned long mode); |
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/* Set/Get Unicast MAC addresses */ |
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void (*set_umac_addr)(void __iomem *ioaddr, unsigned char *addr, |
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unsigned int reg_n); |
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void (*get_umac_addr)(void __iomem *ioaddr, unsigned char *addr, |
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unsigned int reg_n); |
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void (*enable_rx)(void __iomem *ioaddr, bool enable); |
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void (*enable_tx)(void __iomem *ioaddr, bool enable); |
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/* controller version specific operations */ |
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int (*get_controller_version)(void __iomem *ioaddr); |
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/* If supported then get the optional core features */ |
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unsigned int (*get_hw_feature)(void __iomem *ioaddr, |
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unsigned char feature_index); |
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/* adjust SXGBE speed */ |
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void (*set_speed)(void __iomem *ioaddr, unsigned char speed); |
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/* EEE-LPI specific operations */ |
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void (*set_eee_mode)(void __iomem *ioaddr); |
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void (*reset_eee_mode)(void __iomem *ioaddr); |
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void (*set_eee_timer)(void __iomem *ioaddr, const int ls, |
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const int tw); |
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void (*set_eee_pls)(void __iomem *ioaddr, const int link); |
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/* Enable disable checksum offload operations */ |
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void (*enable_rx_csum)(void __iomem *ioaddr); |
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void (*disable_rx_csum)(void __iomem *ioaddr); |
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void (*enable_rxqueue)(void __iomem *ioaddr, int queue_num); |
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void (*disable_rxqueue)(void __iomem *ioaddr, int queue_num); |
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}; |
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const struct sxgbe_core_ops *sxgbe_get_core_ops(void); |
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struct sxgbe_ops { |
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const struct sxgbe_core_ops *mac; |
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const struct sxgbe_desc_ops *desc; |
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const struct sxgbe_dma_ops *dma; |
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const struct sxgbe_mtl_ops *mtl; |
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struct mii_regs mii; /* MII register Addresses */ |
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struct mac_link link; |
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unsigned int ctrl_uid; |
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unsigned int ctrl_id; |
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}; |
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/* SXGBE private data structures */ |
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struct sxgbe_tx_queue { |
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unsigned int irq_no; |
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struct sxgbe_priv_data *priv_ptr; |
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struct sxgbe_tx_norm_desc *dma_tx; |
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dma_addr_t dma_tx_phy; |
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dma_addr_t *tx_skbuff_dma; |
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struct sk_buff **tx_skbuff; |
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struct timer_list txtimer; |
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unsigned int cur_tx; |
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unsigned int dirty_tx; |
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u32 tx_count_frames; |
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u32 tx_coal_frames; |
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u32 tx_coal_timer; |
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int hwts_tx_en; |
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u16 prev_mss; |
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u8 queue_no; |
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}; |
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struct sxgbe_rx_queue { |
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struct sxgbe_priv_data *priv_ptr; |
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struct sxgbe_rx_norm_desc *dma_rx; |
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struct sk_buff **rx_skbuff; |
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unsigned int cur_rx; |
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unsigned int dirty_rx; |
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unsigned int irq_no; |
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u32 rx_riwt; |
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dma_addr_t *rx_skbuff_dma; |
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dma_addr_t dma_rx_phy; |
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u8 queue_no; |
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}; |
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/* SXGBE HW capabilities */ |
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struct sxgbe_hw_features { |
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/****** CAP [0] *******/ |
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unsigned int pmt_remote_wake_up; |
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unsigned int pmt_magic_frame; |
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/* IEEE 1588-2008 */ |
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unsigned int atime_stamp; |
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unsigned int eee; |
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unsigned int tx_csum_offload; |
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unsigned int rx_csum_offload; |
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unsigned int multi_macaddr; |
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unsigned int tstamp_srcselect; |
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unsigned int sa_vlan_insert; |
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/****** CAP [1] *******/ |
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unsigned int rxfifo_size; |
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unsigned int txfifo_size; |
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unsigned int atstmap_hword; |
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unsigned int dcb_enable; |
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unsigned int splithead_enable; |
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unsigned int tcpseg_offload; |
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unsigned int debug_mem; |
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unsigned int rss_enable; |
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unsigned int hash_tsize; |
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unsigned int l3l4_filer_size; |
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/* This value is in bytes and |
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* as mentioned in HW features |
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* of SXGBE data book |
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*/ |
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unsigned int rx_mtl_qsize; |
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unsigned int tx_mtl_qsize; |
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/****** CAP [2] *******/ |
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/* TX and RX number of channels */ |
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unsigned int rx_mtl_queues; |
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unsigned int tx_mtl_queues; |
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unsigned int rx_dma_channels; |
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unsigned int tx_dma_channels; |
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unsigned int pps_output_count; |
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unsigned int aux_input_count; |
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}; |
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struct sxgbe_priv_data { |
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/* DMA descriptos */ |
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struct sxgbe_tx_queue *txq[SXGBE_TX_QUEUES]; |
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struct sxgbe_rx_queue *rxq[SXGBE_RX_QUEUES]; |
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u8 cur_rx_qnum; |
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unsigned int dma_tx_size; |
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unsigned int dma_rx_size; |
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unsigned int dma_buf_sz; |
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u32 rx_riwt; |
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struct napi_struct napi; |
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void __iomem *ioaddr; |
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struct net_device *dev; |
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struct device *device; |
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struct sxgbe_ops *hw; /* sxgbe specific ops */ |
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int no_csum_insertion; |
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int irq; |
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int rxcsum_insertion; |
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spinlock_t stats_lock; /* lock for tx/rx statatics */ |
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int oldlink; |
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int speed; |
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int oldduplex; |
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struct mii_bus *mii; |
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int mii_irq[PHY_MAX_ADDR]; |
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u8 rx_pause; |
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u8 tx_pause; |
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struct sxgbe_extra_stats xstats; |
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struct sxgbe_plat_data *plat; |
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struct sxgbe_hw_features hw_cap; |
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u32 msg_enable; |
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struct clk *sxgbe_clk; |
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int clk_csr; |
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unsigned int mode; |
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unsigned int default_addend; |
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/* advanced time stamp support */ |
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u32 adv_ts; |
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int use_riwt; |
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struct ptp_clock *ptp_clock; |
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/* tc control */ |
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int tx_tc; |
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int rx_tc; |
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/* EEE-LPI specific members */ |
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struct timer_list eee_ctrl_timer; |
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bool tx_path_in_lpi_mode; |
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int lpi_irq; |
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int eee_enabled; |
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int eee_active; |
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int tx_lpi_timer; |
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}; |
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/* Function prototypes */ |
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struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device, |
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struct sxgbe_plat_data *plat_dat, |
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void __iomem *addr); |
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int sxgbe_drv_remove(struct net_device *ndev); |
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void sxgbe_set_ethtool_ops(struct net_device *netdev); |
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int sxgbe_mdio_unregister(struct net_device *ndev); |
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int sxgbe_mdio_register(struct net_device *ndev); |
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int sxgbe_register_platform(void); |
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void sxgbe_unregister_platform(void); |
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#ifdef CONFIG_PM |
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int sxgbe_suspend(struct net_device *ndev); |
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int sxgbe_resume(struct net_device *ndev); |
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int sxgbe_freeze(struct net_device *ndev); |
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int sxgbe_restore(struct net_device *ndev); |
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#endif /* CONFIG_PM */ |
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const struct sxgbe_mtl_ops *sxgbe_get_mtl_ops(void); |
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void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv); |
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bool sxgbe_eee_init(struct sxgbe_priv_data * const priv); |
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#endif /* __SXGBE_COMMON_H__ */
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