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215 lines
6.4 KiB
215 lines
6.4 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
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*/ |
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/* Qualcomm Technologies, Inc. QDF2400 EMAC SGMII Controller driver. |
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*/ |
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#include <linux/iopoll.h> |
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#include "emac.h" |
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/* EMAC_SGMII register offsets */ |
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#define EMAC_SGMII_PHY_TX_PWR_CTRL 0x000C |
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#define EMAC_SGMII_PHY_LANE_CTRL1 0x0018 |
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#define EMAC_SGMII_PHY_CDR_CTRL0 0x0058 |
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#define EMAC_SGMII_PHY_POW_DWN_CTRL0 0x0080 |
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#define EMAC_SGMII_PHY_RESET_CTRL 0x00a8 |
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#define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4 |
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/* SGMII digital lane registers */ |
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#define EMAC_SGMII_LN_DRVR_CTRL0 0x000C |
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#define EMAC_SGMII_LN_DRVR_CTRL1 0x0010 |
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#define EMAC_SGMII_LN_DRVR_TAP_EN 0x0018 |
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#define EMAC_SGMII_LN_TX_MARGINING 0x001C |
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#define EMAC_SGMII_LN_TX_PRE 0x0020 |
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#define EMAC_SGMII_LN_TX_POST 0x0024 |
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#define EMAC_SGMII_LN_TX_BAND_MODE 0x0060 |
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#define EMAC_SGMII_LN_LANE_MODE 0x0064 |
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#define EMAC_SGMII_LN_PARALLEL_RATE 0x007C |
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#define EMAC_SGMII_LN_CML_CTRL_MODE0 0x00C0 |
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#define EMAC_SGMII_LN_MIXER_CTRL_MODE0 0x00D8 |
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#define EMAC_SGMII_LN_VGA_INITVAL 0x013C |
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#define EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0 0x0184 |
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#define EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0 0x0190 |
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#define EMAC_SGMII_LN_UCDR_SO_CONFIG 0x019C |
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#define EMAC_SGMII_LN_RX_BAND 0x01A4 |
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#define EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0 0x01C0 |
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#define EMAC_SGMII_LN_RSM_CONFIG 0x01F8 |
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#define EMAC_SGMII_LN_SIGDET_ENABLES 0x0230 |
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#define EMAC_SGMII_LN_SIGDET_CNTRL 0x0234 |
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#define EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL 0x0238 |
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#define EMAC_SGMII_LN_RX_EN_SIGNAL 0x02AC |
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#define EMAC_SGMII_LN_RX_MISC_CNTRL0 0x02B8 |
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#define EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV 0x02C8 |
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#define EMAC_SGMII_LN_RX_RESECODE_OFFSET 0x02CC |
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/* SGMII digital lane register values */ |
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#define UCDR_STEP_BY_TWO_MODE0 BIT(7) |
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#define UCDR_xO_GAIN_MODE(x) ((x) & 0x7f) |
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#define UCDR_ENABLE BIT(6) |
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#define UCDR_SO_SATURATION(x) ((x) & 0x3f) |
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#define SIGDET_LP_BYP_PS4 BIT(7) |
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#define SIGDET_EN_PS0_TO_PS2 BIT(6) |
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#define TXVAL_VALID_INIT BIT(4) |
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#define KR_PCIGEN3_MODE BIT(0) |
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#define MAIN_EN BIT(0) |
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#define TX_MARGINING_MUX BIT(6) |
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#define TX_MARGINING(x) ((x) & 0x3f) |
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#define TX_PRE_MUX BIT(6) |
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#define TX_POST_MUX BIT(6) |
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#define CML_GEAR_MODE(x) (((x) & 7) << 3) |
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#define CML2CMOS_IBOOST_MODE(x) ((x) & 7) |
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#define RESCODE_OFFSET(x) ((x) & 0x1f) |
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#define MIXER_LOADB_MODE(x) (((x) & 0xf) << 2) |
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#define MIXER_DATARATE_MODE(x) ((x) & 3) |
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#define VGA_THRESH_DFE(x) ((x) & 0x3f) |
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#define SIGDET_LP_BYP_PS0_TO_PS2 BIT(5) |
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#define SIGDET_FLT_BYP BIT(0) |
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#define SIGDET_LVL(x) (((x) & 0xf) << 4) |
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#define SIGDET_DEGLITCH_CTRL(x) (((x) & 0xf) << 1) |
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#define INVERT_PCS_RX_CLK BIT(7) |
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#define DRVR_LOGIC_CLK_EN BIT(4) |
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#define DRVR_LOGIC_CLK_DIV(x) ((x) & 0xf) |
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#define PARALLEL_RATE_MODE0(x) ((x) & 0x3) |
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#define BAND_MODE0(x) ((x) & 0x3) |
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#define LANE_MODE(x) ((x) & 0x1f) |
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#define CDR_PD_SEL_MODE0(x) (((x) & 0x3) << 5) |
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#define EN_DLL_MODE0 BIT(4) |
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#define EN_IQ_DCC_MODE0 BIT(3) |
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#define EN_IQCAL_MODE0 BIT(2) |
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#define BYPASS_RSM_SAMP_CAL BIT(1) |
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#define BYPASS_RSM_DLL_CAL BIT(0) |
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#define L0_RX_EQUALIZE_ENABLE BIT(6) |
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#define PWRDN_B BIT(0) |
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#define CDR_MAX_CNT(x) ((x) & 0xff) |
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#define SERDES_START_WAIT_TIMES 100 |
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struct emac_reg_write { |
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unsigned int offset; |
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u32 val; |
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}; |
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static void emac_reg_write_all(void __iomem *base, |
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const struct emac_reg_write *itr, size_t size) |
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{ |
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size_t i; |
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for (i = 0; i < size; ++itr, ++i) |
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writel(itr->val, base + itr->offset); |
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} |
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static const struct emac_reg_write sgmii_laned[] = { |
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/* CDR Settings */ |
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{EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0, |
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UCDR_STEP_BY_TWO_MODE0 | UCDR_xO_GAIN_MODE(10)}, |
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{EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0, UCDR_xO_GAIN_MODE(0)}, |
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{EMAC_SGMII_LN_UCDR_SO_CONFIG, UCDR_ENABLE | UCDR_SO_SATURATION(12)}, |
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/* TX/RX Settings */ |
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{EMAC_SGMII_LN_RX_EN_SIGNAL, SIGDET_LP_BYP_PS4 | SIGDET_EN_PS0_TO_PS2}, |
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{EMAC_SGMII_LN_DRVR_CTRL0, TXVAL_VALID_INIT | KR_PCIGEN3_MODE}, |
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{EMAC_SGMII_LN_DRVR_TAP_EN, MAIN_EN}, |
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{EMAC_SGMII_LN_TX_MARGINING, TX_MARGINING_MUX | TX_MARGINING(25)}, |
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{EMAC_SGMII_LN_TX_PRE, TX_PRE_MUX}, |
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{EMAC_SGMII_LN_TX_POST, TX_POST_MUX}, |
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{EMAC_SGMII_LN_CML_CTRL_MODE0, |
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CML_GEAR_MODE(1) | CML2CMOS_IBOOST_MODE(1)}, |
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{EMAC_SGMII_LN_MIXER_CTRL_MODE0, |
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MIXER_LOADB_MODE(12) | MIXER_DATARATE_MODE(1)}, |
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{EMAC_SGMII_LN_VGA_INITVAL, VGA_THRESH_DFE(31)}, |
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{EMAC_SGMII_LN_SIGDET_ENABLES, |
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SIGDET_LP_BYP_PS0_TO_PS2 | SIGDET_FLT_BYP}, |
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{EMAC_SGMII_LN_SIGDET_CNTRL, SIGDET_LVL(8)}, |
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{EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL, SIGDET_DEGLITCH_CTRL(4)}, |
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{EMAC_SGMII_LN_RX_MISC_CNTRL0, INVERT_PCS_RX_CLK}, |
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{EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV, |
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DRVR_LOGIC_CLK_EN | DRVR_LOGIC_CLK_DIV(4)}, |
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{EMAC_SGMII_LN_PARALLEL_RATE, PARALLEL_RATE_MODE0(1)}, |
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{EMAC_SGMII_LN_TX_BAND_MODE, BAND_MODE0(1)}, |
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{EMAC_SGMII_LN_RX_BAND, BAND_MODE0(2)}, |
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{EMAC_SGMII_LN_DRVR_CTRL1, RESCODE_OFFSET(7)}, |
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{EMAC_SGMII_LN_RX_RESECODE_OFFSET, RESCODE_OFFSET(9)}, |
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{EMAC_SGMII_LN_LANE_MODE, LANE_MODE(26)}, |
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{EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0, CDR_PD_SEL_MODE0(2) | |
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EN_DLL_MODE0 | EN_IQ_DCC_MODE0 | EN_IQCAL_MODE0}, |
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{EMAC_SGMII_LN_RSM_CONFIG, BYPASS_RSM_SAMP_CAL | BYPASS_RSM_DLL_CAL}, |
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}; |
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static const struct emac_reg_write physical_coding_sublayer_programming[] = { |
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{EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B}, |
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{EMAC_SGMII_PHY_CDR_CTRL0, CDR_MAX_CNT(15)}, |
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{EMAC_SGMII_PHY_TX_PWR_CTRL, 0}, |
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{EMAC_SGMII_PHY_LANE_CTRL1, L0_RX_EQUALIZE_ENABLE}, |
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}; |
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int emac_sgmii_init_qdf2400(struct emac_adapter *adpt) |
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{ |
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struct emac_sgmii *phy = &adpt->phy; |
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void __iomem *phy_regs = phy->base; |
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void __iomem *laned = phy->digital; |
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unsigned int i; |
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u32 lnstatus; |
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/* PCS lane-x init */ |
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emac_reg_write_all(phy->base, physical_coding_sublayer_programming, |
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ARRAY_SIZE(physical_coding_sublayer_programming)); |
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/* SGMII lane-x init */ |
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emac_reg_write_all(phy->digital, sgmii_laned, ARRAY_SIZE(sgmii_laned)); |
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/* Power up PCS and start reset lane state machine */ |
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writel(0, phy_regs + EMAC_SGMII_PHY_RESET_CTRL); |
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writel(1, laned + SGMII_LN_RSM_START); |
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/* Wait for c_ready assertion */ |
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for (i = 0; i < SERDES_START_WAIT_TIMES; i++) { |
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lnstatus = readl(phy_regs + SGMII_PHY_LN_LANE_STATUS); |
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if (lnstatus & BIT(1)) |
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break; |
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usleep_range(100, 200); |
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} |
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if (i == SERDES_START_WAIT_TIMES) { |
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netdev_err(adpt->netdev, "SGMII failed to start\n"); |
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return -EIO; |
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} |
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/* Disable digital and SERDES loopback */ |
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writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN0); |
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writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN2); |
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writel(0, phy_regs + SGMII_PHY_LN_CDR_CTRL1); |
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/* Mask out all the SGMII Interrupt */ |
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writel(0, phy_regs + EMAC_SGMII_PHY_INTERRUPT_MASK); |
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return 0; |
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}
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