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140 lines
3.8 KiB
140 lines
3.8 KiB
/* SPDX-License-Identifier: GPL-2.0+ */ |
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// Copyright (c) 2021 Hisilicon Limited. |
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#ifndef __HCLGE_PTP_H |
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#define __HCLGE_PTP_H |
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#include <linux/ptp_clock_kernel.h> |
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#include <linux/net_tstamp.h> |
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#include <linux/types.h> |
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#define HCLGE_PTP_REG_OFFSET 0x29000 |
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#define HCLGE_PTP_TX_TS_SEQID_REG 0x0 |
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#define HCLGE_PTP_TX_TS_NSEC_REG 0x4 |
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#define HCLGE_PTP_TX_TS_NSEC_MASK GENMASK(29, 0) |
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#define HCLGE_PTP_TX_TS_SEC_L_REG 0x8 |
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#define HCLGE_PTP_TX_TS_SEC_H_REG 0xC |
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#define HCLGE_PTP_TX_TS_SEC_H_MASK GENMASK(15, 0) |
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#define HCLGE_PTP_TX_TS_CNT_REG 0x30 |
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#define HCLGE_PTP_TIME_SEC_H_REG 0x50 |
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#define HCLGE_PTP_TIME_SEC_H_MASK GENMASK(15, 0) |
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#define HCLGE_PTP_TIME_SEC_L_REG 0x54 |
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#define HCLGE_PTP_TIME_NSEC_REG 0x58 |
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#define HCLGE_PTP_TIME_NSEC_MASK GENMASK(29, 0) |
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#define HCLGE_PTP_TIME_NSEC_NEG BIT(31) |
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#define HCLGE_PTP_TIME_SYNC_REG 0x5C |
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#define HCLGE_PTP_TIME_SYNC_EN BIT(0) |
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#define HCLGE_PTP_TIME_ADJ_REG 0x60 |
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#define HCLGE_PTP_TIME_ADJ_EN BIT(0) |
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#define HCLGE_PTP_CYCLE_QUO_REG 0x64 |
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#define HCLGE_PTP_CYCLE_QUO_MASK GENMASK(7, 0) |
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#define HCLGE_PTP_CYCLE_DEN_REG 0x68 |
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#define HCLGE_PTP_CYCLE_NUM_REG 0x6C |
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#define HCLGE_PTP_CYCLE_CFG_REG 0x70 |
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#define HCLGE_PTP_CYCLE_ADJ_EN BIT(0) |
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#define HCLGE_PTP_CUR_TIME_SEC_H_REG 0x74 |
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#define HCLGE_PTP_CUR_TIME_SEC_L_REG 0x78 |
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#define HCLGE_PTP_CUR_TIME_NSEC_REG 0x7C |
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#define HCLGE_PTP_CYCLE_ADJ_MAX 500000000 |
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#define HCLGE_PTP_SEC_H_OFFSET 32u |
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#define HCLGE_PTP_SEC_L_MASK GENMASK(31, 0) |
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#define HCLGE_PTP_FLAG_EN 0 |
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#define HCLGE_PTP_FLAG_TX_EN 1 |
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#define HCLGE_PTP_FLAG_RX_EN 2 |
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struct hclge_ptp_cycle { |
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u32 quo; |
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u32 numer; |
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u32 den; |
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}; |
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struct hclge_ptp { |
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struct hclge_dev *hdev; |
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struct ptp_clock *clock; |
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struct sk_buff *tx_skb; |
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unsigned long flags; |
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void __iomem *io_base; |
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struct ptp_clock_info info; |
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struct hwtstamp_config ts_cfg; |
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spinlock_t lock; /* protects ptp registers */ |
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u32 ptp_cfg; |
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u32 last_tx_seqid; |
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struct hclge_ptp_cycle cycle; |
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unsigned long tx_start; |
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unsigned long tx_cnt; |
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unsigned long tx_skipped; |
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unsigned long tx_cleaned; |
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unsigned long last_rx; |
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unsigned long rx_cnt; |
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unsigned long tx_timeout; |
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}; |
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struct hclge_ptp_int_cmd { |
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#define HCLGE_PTP_INT_EN_B BIT(0) |
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u8 int_en; |
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u8 rsvd[23]; |
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}; |
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enum hclge_ptp_udp_type { |
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HCLGE_PTP_UDP_NOT_TYPE, |
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HCLGE_PTP_UDP_P13F_TYPE, |
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HCLGE_PTP_UDP_P140_TYPE, |
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HCLGE_PTP_UDP_FULL_TYPE, |
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}; |
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enum hclge_ptp_msg_type { |
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HCLGE_PTP_MSG_TYPE_V2_L2, |
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HCLGE_PTP_MSG_TYPE_V2, |
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HCLGE_PTP_MSG_TYPE_V2_EVENT, |
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}; |
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enum hclge_ptp_msg0_type { |
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HCLGE_PTP_MSG0_V2_DELAY_REQ = 1, |
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HCLGE_PTP_MSG0_V2_PDELAY_REQ, |
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HCLGE_PTP_MSG0_V2_DELAY_RESP, |
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HCLGE_PTP_MSG0_V2_EVENT = 0xF, |
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}; |
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#define HCLGE_PTP_MSG1_V2_DEFAULT 1 |
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struct hclge_ptp_cfg_cmd { |
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#define HCLGE_PTP_EN_B BIT(0) |
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#define HCLGE_PTP_TX_EN_B BIT(1) |
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#define HCLGE_PTP_RX_EN_B BIT(2) |
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#define HCLGE_PTP_UDP_EN_SHIFT 3 |
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#define HCLGE_PTP_UDP_EN_MASK GENMASK(4, 3) |
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#define HCLGE_PTP_MSG_TYPE_SHIFT 8 |
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#define HCLGE_PTP_MSG_TYPE_MASK GENMASK(9, 8) |
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#define HCLGE_PTP_MSG1_SHIFT 16 |
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#define HCLGE_PTP_MSG1_MASK GENMASK(19, 16) |
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#define HCLGE_PTP_MSG0_SHIFT 24 |
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#define HCLGE_PTP_MSG0_MASK GENMASK(27, 24) |
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__le32 cfg; |
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u8 rsvd[20]; |
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}; |
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static inline struct hclge_dev *hclge_ptp_get_hdev(struct ptp_clock_info *info) |
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{ |
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struct hclge_ptp *ptp = container_of(info, struct hclge_ptp, info); |
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return ptp->hdev; |
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} |
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bool hclge_ptp_set_tx_info(struct hnae3_handle *handle, struct sk_buff *skb); |
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void hclge_ptp_clean_tx_hwts(struct hclge_dev *hdev); |
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void hclge_ptp_get_rx_hwts(struct hnae3_handle *handle, struct sk_buff *skb, |
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u32 nsec, u32 sec); |
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int hclge_ptp_get_cfg(struct hclge_dev *hdev, struct ifreq *ifr); |
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int hclge_ptp_set_cfg(struct hclge_dev *hdev, struct ifreq *ifr); |
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int hclge_ptp_init(struct hclge_dev *hdev); |
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void hclge_ptp_uninit(struct hclge_dev *hdev); |
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int hclge_ptp_get_ts_info(struct hnae3_handle *handle, |
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struct ethtool_ts_info *info); |
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int hclge_ptp_cfg_qry(struct hclge_dev *hdev, u32 *cfg); |
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#endif
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