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352 lines
6.6 KiB
352 lines
6.6 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2017 Chelsio Communications. All rights reserved. |
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*/ |
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#ifndef __CUDBG_ENTITY_H__ |
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#define __CUDBG_ENTITY_H__ |
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#define EDC0_FLAG 0 |
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#define EDC1_FLAG 1 |
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#define MC_FLAG 2 |
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#define MC0_FLAG 3 |
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#define MC1_FLAG 4 |
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#define HMA_FLAG 5 |
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#define CUDBG_ENTITY_SIGNATURE 0xCCEDB001 |
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struct cudbg_mbox_log { |
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struct mbox_cmd entry; |
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u32 hi[MBOX_LEN / 8]; |
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u32 lo[MBOX_LEN / 8]; |
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}; |
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struct cudbg_cim_qcfg { |
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u8 chip; |
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u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; |
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u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; |
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u16 thres[CIM_NUM_IBQ]; |
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u32 obq_wr[2 * CIM_NUM_OBQ_T5]; |
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u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)]; |
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}; |
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struct cudbg_rss_vf_conf { |
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u32 rss_vf_vfl; |
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u32 rss_vf_vfh; |
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}; |
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struct cudbg_pm_stats { |
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u32 tx_cnt[T6_PM_NSTATS]; |
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u32 rx_cnt[T6_PM_NSTATS]; |
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u64 tx_cyc[T6_PM_NSTATS]; |
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u64 rx_cyc[T6_PM_NSTATS]; |
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}; |
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struct cudbg_hw_sched { |
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u32 kbps[NTX_SCHED]; |
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u32 ipg[NTX_SCHED]; |
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u32 pace_tab[NTX_SCHED]; |
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u32 mode; |
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u32 map; |
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}; |
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#define SGE_QBASE_DATA_REG_NUM 4 |
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struct sge_qbase_reg_field { |
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u32 reg_addr; |
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u32 reg_data[SGE_QBASE_DATA_REG_NUM]; |
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/* Max supported PFs */ |
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u32 pf_data_value[PCIE_FW_MASTER_M + 1][SGE_QBASE_DATA_REG_NUM]; |
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/* Max supported VFs */ |
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u32 vf_data_value[T6_VF_M + 1][SGE_QBASE_DATA_REG_NUM]; |
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u32 vfcount; /* Actual number of max vfs in current configuration */ |
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}; |
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struct ireg_field { |
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u32 ireg_addr; |
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u32 ireg_data; |
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u32 ireg_local_offset; |
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u32 ireg_offset_range; |
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}; |
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struct ireg_buf { |
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struct ireg_field tp_pio; |
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u32 outbuf[32]; |
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}; |
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struct cudbg_ulprx_la { |
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u32 data[ULPRX_LA_SIZE * 8]; |
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u32 size; |
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}; |
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struct cudbg_tp_la { |
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u32 size; |
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u32 mode; |
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u8 data[]; |
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}; |
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static const char * const cudbg_region[] = { |
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"DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", |
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"Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", |
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"Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", |
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"TDDP region:", "TPT region:", "STAG region:", "RQ region:", |
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"RQUDP region:", "PBL region:", "TXPBL region:", |
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"DBVFIFO region:", "ULPRX state:", "ULPTX state:", |
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"On-chip queues:" |
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}; |
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/* Memory region info relative to current memory (i.e. wrt 0). */ |
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struct cudbg_region_info { |
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bool exist; /* Does region exists in current memory? */ |
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u32 start; /* Start wrt 0 */ |
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u32 end; /* End wrt 0 */ |
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}; |
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struct cudbg_mem_desc { |
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u32 base; |
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u32 limit; |
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u32 idx; |
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}; |
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#define CUDBG_MEMINFO_REV 1 |
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struct cudbg_meminfo { |
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struct cudbg_mem_desc avail[4]; |
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struct cudbg_mem_desc mem[ARRAY_SIZE(cudbg_region) + 3]; |
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u32 avail_c; |
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u32 mem_c; |
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u32 up_ram_lo; |
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u32 up_ram_hi; |
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u32 up_extmem2_lo; |
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u32 up_extmem2_hi; |
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u32 rx_pages_data[3]; |
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u32 tx_pages_data[4]; |
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u32 p_structs; |
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u32 reserved[12]; |
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u32 port_used[4]; |
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u32 port_alloc[4]; |
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u32 loopback_used[NCHAN]; |
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u32 loopback_alloc[NCHAN]; |
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u32 p_structs_free_cnt; |
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u32 free_rx_cnt; |
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u32 free_tx_cnt; |
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}; |
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struct cudbg_cim_pif_la { |
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int size; |
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u8 data[]; |
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}; |
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struct cudbg_clk_info { |
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u64 retransmit_min; |
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u64 retransmit_max; |
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u64 persist_timer_min; |
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u64 persist_timer_max; |
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u64 keepalive_idle_timer; |
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u64 keepalive_interval; |
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u64 initial_srtt; |
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u64 finwait2_timer; |
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u32 dack_timer; |
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u32 res; |
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u32 cclk_ps; |
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u32 tre; |
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u32 dack_re; |
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}; |
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struct cudbg_tid_info_region { |
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u32 ntids; |
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u32 nstids; |
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u32 stid_base; |
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u32 hash_base; |
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u32 natids; |
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u32 nftids; |
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u32 ftid_base; |
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u32 aftid_base; |
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u32 aftid_end; |
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u32 sftid_base; |
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u32 nsftids; |
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u32 uotid_base; |
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u32 nuotids; |
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u32 sb; |
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u32 flags; |
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u32 le_db_conf; |
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u32 ip_users; |
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u32 ipv6_users; |
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u32 hpftid_base; |
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u32 nhpftids; |
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}; |
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#define CUDBG_TID_INFO_REV 1 |
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struct cudbg_tid_info_region_rev1 { |
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struct cudbg_ver_hdr ver_hdr; |
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struct cudbg_tid_info_region tid; |
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u32 tid_start; |
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u32 reserved[16]; |
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}; |
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#define CUDBG_LOWMEM_MAX_CTXT_QIDS 256 |
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#define CUDBG_MAX_FL_QIDS 1024 |
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struct cudbg_ch_cntxt { |
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u32 cntxt_type; |
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u32 cntxt_id; |
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u32 data[SGE_CTXT_SIZE / 4]; |
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}; |
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#define CUDBG_MAX_RPLC_SIZE 128 |
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struct cudbg_mps_tcam { |
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u64 mask; |
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u32 rplc[8]; |
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u32 idx; |
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u32 cls_lo; |
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u32 cls_hi; |
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u32 rplc_size; |
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u32 vniy; |
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u32 vnix; |
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u32 dip_hit; |
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u32 vlan_vld; |
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u32 repli; |
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u16 ivlan; |
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u8 addr[ETH_ALEN]; |
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u8 lookup_type; |
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u8 port_num; |
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u8 reserved[2]; |
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}; |
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#define CUDBG_VPD_VER_ADDR 0x18c7 |
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#define CUDBG_VPD_VER_LEN 2 |
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struct cudbg_vpd_data { |
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u8 sn[SERNUM_LEN + 1]; |
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u8 bn[PN_LEN + 1]; |
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u8 na[MACADDR_LEN + 1]; |
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u8 mn[ID_LEN + 1]; |
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u16 fw_major; |
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u16 fw_minor; |
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u16 fw_micro; |
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u16 fw_build; |
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u32 scfg_vers; |
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u32 vpd_vers; |
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}; |
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#define CUDBG_MAX_TCAM_TID 0x800 |
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#define CUDBG_T6_CLIP 1536 |
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#define CUDBG_MAX_TID_COMP_EN 6144 |
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#define CUDBG_MAX_TID_COMP_DIS 3072 |
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enum cudbg_le_entry_types { |
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LE_ET_UNKNOWN = 0, |
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LE_ET_TCAM_CON = 1, |
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LE_ET_TCAM_SERVER = 2, |
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LE_ET_TCAM_FILTER = 3, |
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LE_ET_TCAM_CLIP = 4, |
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LE_ET_TCAM_ROUTING = 5, |
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LE_ET_HASH_CON = 6, |
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LE_ET_INVALID_TID = 8, |
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}; |
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struct cudbg_tcam { |
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u32 filter_start; |
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u32 server_start; |
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u32 clip_start; |
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u32 routing_start; |
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u32 tid_hash_base; |
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u32 max_tid; |
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}; |
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struct cudbg_tid_data { |
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u32 tid; |
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u32 dbig_cmd; |
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u32 dbig_conf; |
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u32 dbig_rsp_stat; |
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u32 data[NUM_LE_DB_DBGI_RSP_DATA_INSTANCES]; |
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}; |
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#define CUDBG_NUM_ULPTX 11 |
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#define CUDBG_NUM_ULPTX_READ 512 |
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#define CUDBG_NUM_ULPTX_ASIC 6 |
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#define CUDBG_NUM_ULPTX_ASIC_READ 128 |
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#define CUDBG_ULPTX_LA_REV 1 |
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struct cudbg_ulptx_la { |
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u32 rdptr[CUDBG_NUM_ULPTX]; |
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u32 wrptr[CUDBG_NUM_ULPTX]; |
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u32 rddata[CUDBG_NUM_ULPTX]; |
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u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ]; |
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u32 rdptr_asic[CUDBG_NUM_ULPTX_ASIC_READ]; |
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u32 rddata_asic[CUDBG_NUM_ULPTX_ASIC_READ][CUDBG_NUM_ULPTX_ASIC]; |
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}; |
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#define CUDBG_CHAC_PBT_ADDR 0x2800 |
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#define CUDBG_CHAC_PBT_LRF 0x3000 |
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#define CUDBG_CHAC_PBT_DATA 0x3800 |
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#define CUDBG_PBT_DYNAMIC_ENTRIES 8 |
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#define CUDBG_PBT_STATIC_ENTRIES 16 |
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#define CUDBG_LRF_ENTRIES 8 |
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#define CUDBG_PBT_DATA_ENTRIES 512 |
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struct cudbg_pbt_tables { |
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u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES]; |
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u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES]; |
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u32 lrf_table[CUDBG_LRF_ENTRIES]; |
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u32 pbt_data[CUDBG_PBT_DATA_ENTRIES]; |
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}; |
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enum cudbg_qdesc_qtype { |
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CUDBG_QTYPE_UNKNOWN = 0, |
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CUDBG_QTYPE_NIC_TXQ, |
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CUDBG_QTYPE_NIC_RXQ, |
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CUDBG_QTYPE_NIC_FLQ, |
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CUDBG_QTYPE_CTRLQ, |
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CUDBG_QTYPE_FWEVTQ, |
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CUDBG_QTYPE_INTRQ, |
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CUDBG_QTYPE_PTP_TXQ, |
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CUDBG_QTYPE_OFLD_TXQ, |
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CUDBG_QTYPE_RDMA_RXQ, |
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CUDBG_QTYPE_RDMA_FLQ, |
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CUDBG_QTYPE_RDMA_CIQ, |
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CUDBG_QTYPE_ISCSI_RXQ, |
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CUDBG_QTYPE_ISCSI_FLQ, |
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CUDBG_QTYPE_ISCSIT_RXQ, |
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CUDBG_QTYPE_ISCSIT_FLQ, |
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CUDBG_QTYPE_CRYPTO_TXQ, |
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CUDBG_QTYPE_CRYPTO_RXQ, |
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CUDBG_QTYPE_CRYPTO_FLQ, |
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CUDBG_QTYPE_TLS_RXQ, |
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CUDBG_QTYPE_TLS_FLQ, |
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CUDBG_QTYPE_ETHOFLD_TXQ, |
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CUDBG_QTYPE_ETHOFLD_RXQ, |
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CUDBG_QTYPE_ETHOFLD_FLQ, |
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CUDBG_QTYPE_MAX, |
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}; |
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#define CUDBG_QDESC_REV 1 |
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struct cudbg_qdesc_entry { |
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u32 data_size; |
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u32 qtype; |
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u32 qid; |
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u32 desc_size; |
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u32 num_desc; |
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u8 data[]; /* Must be last */ |
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}; |
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struct cudbg_qdesc_info { |
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u32 qdesc_entry_size; |
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u32 num_queues; |
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u8 data[]; /* Must be last */ |
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}; |
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#define IREG_NUM_ELEM 4 |
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#define CUDBG_NUM_PCIE_CONFIG_REGS 0x61 |
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#endif /* __CUDBG_ENTITY_H__ */
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