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236 lines
9.4 KiB
236 lines
9.4 KiB
/* Generic NS8390 register definitions. */ |
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/* This file is part of Donald Becker's 8390 drivers, and is distributed |
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* under the same license. Auto-loading of 8390.o only in v2.2 - Paul G. |
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* Some of these names and comments originated from the Crynwr |
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* packet drivers, which are distributed under the GPL. |
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*/ |
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#ifndef _8390_h |
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#define _8390_h |
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#include <linux/if_ether.h> |
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#include <linux/ioport.h> |
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#include <linux/irqreturn.h> |
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#include <linux/skbuff.h> |
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#define TX_PAGES 12 /* Two Tx slots */ |
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/* The 8390 specific per-packet-header format. */ |
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struct e8390_pkt_hdr { |
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unsigned char status; /* status */ |
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unsigned char next; /* pointer to next packet. */ |
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unsigned short count; /* header + packet length in bytes */ |
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}; |
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#ifdef CONFIG_NET_POLL_CONTROLLER |
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void ei_poll(struct net_device *dev); |
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void eip_poll(struct net_device *dev); |
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#endif |
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/* Without I/O delay - non ISA or later chips */ |
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void NS8390_init(struct net_device *dev, int startp); |
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int ei_open(struct net_device *dev); |
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int ei_close(struct net_device *dev); |
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irqreturn_t ei_interrupt(int irq, void *dev_id); |
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void ei_tx_timeout(struct net_device *dev, unsigned int txqueue); |
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netdev_tx_t ei_start_xmit(struct sk_buff *skb, struct net_device *dev); |
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void ei_set_multicast_list(struct net_device *dev); |
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struct net_device_stats *ei_get_stats(struct net_device *dev); |
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extern const struct net_device_ops ei_netdev_ops; |
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struct net_device *__alloc_ei_netdev(int size); |
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static inline struct net_device *alloc_ei_netdev(void) |
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{ |
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return __alloc_ei_netdev(0); |
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} |
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/* With I/O delay form */ |
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void NS8390p_init(struct net_device *dev, int startp); |
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int eip_open(struct net_device *dev); |
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int eip_close(struct net_device *dev); |
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irqreturn_t eip_interrupt(int irq, void *dev_id); |
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void eip_tx_timeout(struct net_device *dev, unsigned int txqueue); |
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netdev_tx_t eip_start_xmit(struct sk_buff *skb, struct net_device *dev); |
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void eip_set_multicast_list(struct net_device *dev); |
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struct net_device_stats *eip_get_stats(struct net_device *dev); |
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extern const struct net_device_ops eip_netdev_ops; |
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struct net_device *__alloc_eip_netdev(int size); |
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static inline struct net_device *alloc_eip_netdev(void) |
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{ |
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return __alloc_eip_netdev(0); |
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} |
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/* You have one of these per-board */ |
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struct ei_device { |
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const char *name; |
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void (*reset_8390)(struct net_device *dev); |
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void (*get_8390_hdr)(struct net_device *dev, |
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struct e8390_pkt_hdr *hdr, int ring_page); |
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void (*block_output)(struct net_device *dev, int count, |
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const unsigned char *buf, int start_page); |
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void (*block_input)(struct net_device *dev, int count, |
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struct sk_buff *skb, int ring_offset); |
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unsigned long rmem_start; |
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unsigned long rmem_end; |
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void __iomem *mem; |
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unsigned char mcfilter[8]; |
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unsigned open:1; |
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unsigned word16:1; /* We have the 16-bit (vs 8-bit) |
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* version of the card. |
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*/ |
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unsigned bigendian:1; /* 16-bit big endian mode. Do NOT |
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* set this on random 8390 clones! |
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*/ |
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unsigned txing:1; /* Transmit Active */ |
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unsigned irqlock:1; /* 8390's intrs disabled when '1'. */ |
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unsigned dmaing:1; /* Remote DMA Active */ |
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unsigned char tx_start_page, rx_start_page, stop_page; |
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unsigned char current_page; /* Read pointer in buffer */ |
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unsigned char interface_num; /* Net port (AUI, 10bT.) to use. */ |
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unsigned char txqueue; /* Tx Packet buffer queue length. */ |
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short tx1, tx2; /* Packet lengths for ping-pong tx. */ |
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short lasttx; /* Alpha version consistency check. */ |
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unsigned char reg0; /* Register '0' in a WD8013 */ |
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unsigned char reg5; /* Register '5' in a WD8013 */ |
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unsigned char saved_irq; /* Original dev->irq value. */ |
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u32 *reg_offset; /* Register mapping table */ |
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spinlock_t page_lock; /* Page register locks */ |
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unsigned long priv; /* Private field to store bus IDs etc. */ |
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u32 msg_enable; /* debug message level */ |
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#ifdef AX88796_PLATFORM |
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unsigned char rxcr_base; /* default value for RXCR */ |
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#endif |
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}; |
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/* The maximum number of 8390 interrupt service routines called per IRQ. */ |
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#define MAX_SERVICE 12 |
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/* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */ |
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#define TX_TIMEOUT (20*HZ/100) |
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#define ei_status (*(struct ei_device *)netdev_priv(dev)) |
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/* Some generic ethernet register configurations. */ |
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#define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */ |
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#define E8390_RX_IRQ_MASK 0x5 |
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#ifdef AX88796_PLATFORM |
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#define E8390_RXCONFIG (ei_status.rxcr_base | 0x04) |
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#define E8390_RXOFF (ei_status.rxcr_base | 0x20) |
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#else |
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/* EN0_RXCR: broadcasts, no multicast,errors */ |
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#define E8390_RXCONFIG 0x4 |
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/* EN0_RXCR: Accept no packets */ |
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#define E8390_RXOFF 0x20 |
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#endif |
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/* EN0_TXCR: Normal transmit mode */ |
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#define E8390_TXCONFIG 0x00 |
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/* EN0_TXCR: Transmitter off */ |
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#define E8390_TXOFF 0x02 |
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/* Register accessed at EN_CMD, the 8390 base addr. */ |
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#define E8390_STOP 0x01 /* Stop and reset the chip */ |
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#define E8390_START 0x02 /* Start the chip, clear reset */ |
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#define E8390_TRANS 0x04 /* Transmit a frame */ |
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#define E8390_RREAD 0x08 /* Remote read */ |
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#define E8390_RWRITE 0x10 /* Remote write */ |
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#define E8390_NODMA 0x20 /* Remote DMA */ |
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#define E8390_PAGE0 0x00 /* Select page chip registers */ |
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#define E8390_PAGE1 0x40 /* using the two high-order bits */ |
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#define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
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/* Only generate indirect loads given a machine that needs them. |
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* - removed AMIGA_PCMCIA from this list, handled as ISA io now |
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* - the _p for generates no delay by default 8390p.c overrides this. |
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*/ |
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#ifndef ei_inb |
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#define ei_inb(_p) inb(_p) |
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#define ei_outb(_v, _p) outb(_v, _p) |
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#define ei_inb_p(_p) inb(_p) |
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#define ei_outb_p(_v, _p) outb(_v, _p) |
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#endif |
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#ifndef EI_SHIFT |
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#define EI_SHIFT(x) (x) |
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#endif |
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#define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */ |
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/* Page 0 register offsets. */ |
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#define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */ |
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#define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */ |
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#define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */ |
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#define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */ |
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#define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */ |
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#define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */ |
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#define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */ |
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#define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */ |
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#define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */ |
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#define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */ |
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#define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */ |
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#define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */ |
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#define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */ |
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#define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */ |
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#define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */ |
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#define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */ |
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#define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */ |
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#define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */ |
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#define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */ |
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#define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */ |
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#define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */ |
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#define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */ |
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#define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */ |
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#define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */ |
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#define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */ |
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#define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */ |
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/* Bits in EN0_ISR - Interrupt status register */ |
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#define ENISR_RX 0x01 /* Receiver, no error */ |
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#define ENISR_TX 0x02 /* Transmitter, no error */ |
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#define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
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#define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
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#define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
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#define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
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#define ENISR_RDC 0x40 /* remote dma complete */ |
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#define ENISR_RESET 0x80 /* Reset completed */ |
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#define ENISR_ALL 0x3f /* Interrupts we will enable */ |
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/* Bits in EN0_DCFG - Data config register */ |
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#define ENDCFG_WTS 0x01 /* word transfer mode selection */ |
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#define ENDCFG_BOS 0x02 /* byte order selection */ |
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/* Page 1 register offsets. */ |
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#define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */ |
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#define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */ |
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#define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */ |
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#define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */ |
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#define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */ |
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/* Bits in received packet status byte and EN0_RSR*/ |
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#define ENRSR_RXOK 0x01 /* Received a good packet */ |
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#define ENRSR_CRC 0x02 /* CRC error */ |
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#define ENRSR_FAE 0x04 /* frame alignment error */ |
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#define ENRSR_FO 0x08 /* FIFO overrun */ |
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#define ENRSR_MPA 0x10 /* missed pkt */ |
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#define ENRSR_PHY 0x20 /* physical/multicast address */ |
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#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
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#define ENRSR_DEF 0x80 /* deferring */ |
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/* Transmitted packet status, EN0_TSR. */ |
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#define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
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#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
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#define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
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#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
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#define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
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#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
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#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
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#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
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#endif /* _8390_h */
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