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589 lines
14 KiB
589 lines
14 KiB
// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 |
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/* |
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* Mellanox i2c driver |
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* |
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* Copyright (C) 2016-2020 Mellanox Technologies |
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*/ |
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|
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#include <linux/delay.h> |
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#include <linux/i2c.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/platform_data/mlxreg.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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/* General defines */ |
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#define MLXPLAT_CPLD_LPC_I2C_BASE_ADDR 0x2000 |
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#define MLXCPLD_I2C_DEVICE_NAME "i2c_mlxcpld" |
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#define MLXCPLD_I2C_VALID_FLAG (I2C_M_RECV_LEN | I2C_M_RD) |
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#define MLXCPLD_I2C_BUS_NUM 1 |
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#define MLXCPLD_I2C_DATA_REG_SZ 36 |
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#define MLXCPLD_I2C_DATA_SZ_BIT BIT(5) |
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#define MLXCPLD_I2C_DATA_SZ_MASK GENMASK(6, 5) |
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#define MLXCPLD_I2C_SMBUS_BLK_BIT BIT(7) |
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#define MLXCPLD_I2C_MAX_ADDR_LEN 4 |
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#define MLXCPLD_I2C_RETR_NUM 2 |
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#define MLXCPLD_I2C_XFER_TO 500000 /* usec */ |
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#define MLXCPLD_I2C_POLL_TIME 400 /* usec */ |
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/* LPC I2C registers */ |
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#define MLXCPLD_LPCI2C_CPBLTY_REG 0x0 |
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#define MLXCPLD_LPCI2C_CTRL_REG 0x1 |
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#define MLXCPLD_LPCI2C_HALF_CYC_REG 0x4 |
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#define MLXCPLD_LPCI2C_I2C_HOLD_REG 0x5 |
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#define MLXCPLD_LPCI2C_CMD_REG 0x6 |
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#define MLXCPLD_LPCI2C_NUM_DAT_REG 0x7 |
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#define MLXCPLD_LPCI2C_NUM_ADDR_REG 0x8 |
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#define MLXCPLD_LPCI2C_STATUS_REG 0x9 |
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#define MLXCPLD_LPCI2C_DATA_REG 0xa |
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/* LPC I2C masks and parametres */ |
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#define MLXCPLD_LPCI2C_RST_SEL_MASK 0x1 |
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#define MLXCPLD_LPCI2C_TRANS_END 0x1 |
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#define MLXCPLD_LPCI2C_STATUS_NACK 0x10 |
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#define MLXCPLD_LPCI2C_NO_IND 0 |
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#define MLXCPLD_LPCI2C_ACK_IND 1 |
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#define MLXCPLD_LPCI2C_NACK_IND 2 |
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#define MLXCPLD_I2C_FREQ_1000KHZ_SET 0x04 |
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#define MLXCPLD_I2C_FREQ_400KHZ_SET 0x0c |
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#define MLXCPLD_I2C_FREQ_100KHZ_SET 0x42 |
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enum mlxcpld_i2c_frequency { |
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MLXCPLD_I2C_FREQ_1000KHZ = 1, |
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MLXCPLD_I2C_FREQ_400KHZ = 2, |
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MLXCPLD_I2C_FREQ_100KHZ = 3, |
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}; |
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struct mlxcpld_i2c_curr_xfer { |
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u8 cmd; |
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u8 addr_width; |
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u8 data_len; |
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u8 msg_num; |
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struct i2c_msg *msg; |
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}; |
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struct mlxcpld_i2c_priv { |
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struct i2c_adapter adap; |
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u32 base_addr; |
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struct mutex lock; |
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struct mlxcpld_i2c_curr_xfer xfer; |
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struct device *dev; |
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bool smbus_block; |
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}; |
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static void mlxcpld_i2c_lpc_write_buf(u8 *data, u8 len, u32 addr) |
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{ |
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int i; |
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for (i = 0; i < len - len % 4; i += 4) |
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outl(*(u32 *)(data + i), addr + i); |
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for (; i < len; ++i) |
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outb(*(data + i), addr + i); |
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} |
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static void mlxcpld_i2c_lpc_read_buf(u8 *data, u8 len, u32 addr) |
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{ |
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int i; |
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for (i = 0; i < len - len % 4; i += 4) |
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*(u32 *)(data + i) = inl(addr + i); |
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for (; i < len; ++i) |
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*(data + i) = inb(addr + i); |
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} |
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static void mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv *priv, u8 offs, |
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u8 *data, u8 datalen) |
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{ |
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u32 addr = priv->base_addr + offs; |
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switch (datalen) { |
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case 1: |
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*(data) = inb(addr); |
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break; |
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case 2: |
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*((u16 *)data) = inw(addr); |
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break; |
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case 3: |
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*((u16 *)data) = inw(addr); |
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*(data + 2) = inb(addr + 2); |
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break; |
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case 4: |
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*((u32 *)data) = inl(addr); |
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break; |
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default: |
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mlxcpld_i2c_lpc_read_buf(data, datalen, addr); |
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break; |
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} |
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} |
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static void mlxcpld_i2c_write_comm(struct mlxcpld_i2c_priv *priv, u8 offs, |
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u8 *data, u8 datalen) |
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{ |
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u32 addr = priv->base_addr + offs; |
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switch (datalen) { |
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case 1: |
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outb(*(data), addr); |
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break; |
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case 2: |
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outw(*((u16 *)data), addr); |
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break; |
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case 3: |
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outw(*((u16 *)data), addr); |
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outb(*(data + 2), addr + 2); |
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break; |
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case 4: |
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outl(*((u32 *)data), addr); |
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break; |
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default: |
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mlxcpld_i2c_lpc_write_buf(data, datalen, addr); |
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break; |
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} |
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} |
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/* |
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* Check validity of received i2c messages parameters. |
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* Returns 0 if OK, other - in case of invalid parameters. |
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*/ |
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static int mlxcpld_i2c_check_msg_params(struct mlxcpld_i2c_priv *priv, |
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struct i2c_msg *msgs, int num) |
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{ |
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int i; |
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if (!num) { |
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dev_err(priv->dev, "Incorrect 0 num of messages\n"); |
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return -EINVAL; |
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} |
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if (unlikely(msgs[0].addr > 0x7f)) { |
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dev_err(priv->dev, "Invalid address 0x%03x\n", |
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msgs[0].addr); |
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return -EINVAL; |
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} |
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for (i = 0; i < num; ++i) { |
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if (unlikely(!msgs[i].buf)) { |
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dev_err(priv->dev, "Invalid buf in msg[%d]\n", |
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i); |
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return -EINVAL; |
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} |
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if (unlikely(msgs[0].addr != msgs[i].addr)) { |
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dev_err(priv->dev, "Invalid addr in msg[%d]\n", |
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i); |
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return -EINVAL; |
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} |
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} |
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return 0; |
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} |
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/* |
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* Check if transfer is completed and status of operation. |
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* Returns 0 - transfer completed (both ACK or NACK), |
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* negative - transfer isn't finished. |
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*/ |
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static int mlxcpld_i2c_check_status(struct mlxcpld_i2c_priv *priv, int *status) |
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{ |
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u8 val; |
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mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1); |
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if (val & MLXCPLD_LPCI2C_TRANS_END) { |
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if (val & MLXCPLD_LPCI2C_STATUS_NACK) |
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/* |
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* The slave is unable to accept the data. No such |
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* slave, command not understood, or unable to accept |
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* any more data. |
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*/ |
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*status = MLXCPLD_LPCI2C_NACK_IND; |
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else |
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*status = MLXCPLD_LPCI2C_ACK_IND; |
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return 0; |
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} |
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*status = MLXCPLD_LPCI2C_NO_IND; |
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return -EIO; |
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} |
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static void mlxcpld_i2c_set_transf_data(struct mlxcpld_i2c_priv *priv, |
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struct i2c_msg *msgs, int num, |
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u8 comm_len) |
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{ |
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priv->xfer.msg = msgs; |
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priv->xfer.msg_num = num; |
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/* |
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* All upper layers currently are never use transfer with more than |
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* 2 messages. Actually, it's also not so relevant in Mellanox systems |
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* because of HW limitation. Max size of transfer is not more than 32 |
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* or 68 bytes in the current x86 LPCI2C bridge. |
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*/ |
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priv->xfer.cmd = msgs[num - 1].flags & I2C_M_RD; |
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if (priv->xfer.cmd == I2C_M_RD && comm_len != msgs[0].len) { |
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priv->xfer.addr_width = msgs[0].len; |
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priv->xfer.data_len = comm_len - priv->xfer.addr_width; |
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} else { |
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priv->xfer.addr_width = 0; |
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priv->xfer.data_len = comm_len; |
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} |
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} |
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/* Reset CPLD LPCI2C block */ |
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static void mlxcpld_i2c_reset(struct mlxcpld_i2c_priv *priv) |
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{ |
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u8 val; |
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mutex_lock(&priv->lock); |
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mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1); |
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val &= ~MLXCPLD_LPCI2C_RST_SEL_MASK; |
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mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1); |
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mutex_unlock(&priv->lock); |
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} |
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/* Make sure the CPLD is ready to start transmitting. */ |
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static int mlxcpld_i2c_check_busy(struct mlxcpld_i2c_priv *priv) |
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{ |
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u8 val; |
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mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1); |
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if (val & MLXCPLD_LPCI2C_TRANS_END) |
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return 0; |
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return -EIO; |
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} |
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static int mlxcpld_i2c_wait_for_free(struct mlxcpld_i2c_priv *priv) |
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{ |
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int timeout = 0; |
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do { |
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if (!mlxcpld_i2c_check_busy(priv)) |
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break; |
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usleep_range(MLXCPLD_I2C_POLL_TIME / 2, MLXCPLD_I2C_POLL_TIME); |
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timeout += MLXCPLD_I2C_POLL_TIME; |
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} while (timeout <= MLXCPLD_I2C_XFER_TO); |
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if (timeout > MLXCPLD_I2C_XFER_TO) |
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return -ETIMEDOUT; |
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return 0; |
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} |
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/* |
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* Wait for master transfer to complete. |
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* It puts current process to sleep until we get interrupt or timeout expires. |
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* Returns the number of transferred or read bytes or error (<0). |
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*/ |
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static int mlxcpld_i2c_wait_for_tc(struct mlxcpld_i2c_priv *priv) |
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{ |
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int status, i, timeout = 0; |
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u8 datalen, val; |
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do { |
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usleep_range(MLXCPLD_I2C_POLL_TIME / 2, MLXCPLD_I2C_POLL_TIME); |
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if (!mlxcpld_i2c_check_status(priv, &status)) |
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break; |
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timeout += MLXCPLD_I2C_POLL_TIME; |
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} while (status == 0 && timeout < MLXCPLD_I2C_XFER_TO); |
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switch (status) { |
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case MLXCPLD_LPCI2C_NO_IND: |
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return -ETIMEDOUT; |
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case MLXCPLD_LPCI2C_ACK_IND: |
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if (priv->xfer.cmd != I2C_M_RD) |
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return (priv->xfer.addr_width + priv->xfer.data_len); |
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if (priv->xfer.msg_num == 1) |
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i = 0; |
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else |
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i = 1; |
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if (!priv->xfer.msg[i].buf) |
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return -EINVAL; |
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/* |
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* Actual read data len will be always the same as |
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* requested len. 0xff (line pull-up) will be returned |
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* if slave has no data to return. Thus don't read |
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* MLXCPLD_LPCI2C_NUM_DAT_REG reg from CPLD. Only in case of |
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* SMBus block read transaction data len can be different, |
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* check this case. |
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*/ |
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mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val, |
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1); |
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if (priv->smbus_block && (val & MLXCPLD_I2C_SMBUS_BLK_BIT)) { |
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mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG, |
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&datalen, 1); |
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if (unlikely(datalen > I2C_SMBUS_BLOCK_MAX)) { |
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dev_err(priv->dev, "Incorrect smbus block read message len\n"); |
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return -EPROTO; |
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} |
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} else { |
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datalen = priv->xfer.data_len; |
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} |
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mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_DATA_REG, |
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priv->xfer.msg[i].buf, datalen); |
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return datalen; |
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case MLXCPLD_LPCI2C_NACK_IND: |
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return -ENXIO; |
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default: |
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return -EINVAL; |
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} |
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} |
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static void mlxcpld_i2c_xfer_msg(struct mlxcpld_i2c_priv *priv) |
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{ |
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int i, len = 0; |
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u8 cmd, val; |
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mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG, |
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&priv->xfer.data_len, 1); |
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val = priv->xfer.addr_width; |
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/* Notify HW about SMBus block read transaction */ |
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if (priv->smbus_block && priv->xfer.msg_num >= 2 && |
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priv->xfer.msg[1].len == 1 && |
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(priv->xfer.msg[1].flags & I2C_M_RECV_LEN) && |
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(priv->xfer.msg[1].flags & I2C_M_RD)) |
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val |= MLXCPLD_I2C_SMBUS_BLK_BIT; |
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mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val, 1); |
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for (i = 0; i < priv->xfer.msg_num; i++) { |
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if ((priv->xfer.msg[i].flags & I2C_M_RD) != I2C_M_RD) { |
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/* Don't write to CPLD buffer in read transaction */ |
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mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_DATA_REG + |
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len, priv->xfer.msg[i].buf, |
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priv->xfer.msg[i].len); |
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len += priv->xfer.msg[i].len; |
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} |
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} |
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/* |
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* Set target slave address with command for master transfer. |
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* It should be latest executed function before CPLD transaction. |
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*/ |
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cmd = (priv->xfer.msg[0].addr << 1) | priv->xfer.cmd; |
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mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CMD_REG, &cmd, 1); |
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} |
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/* |
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* Generic lpc-i2c transfer. |
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* Returns the number of processed messages or error (<0). |
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*/ |
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static int mlxcpld_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, |
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int num) |
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{ |
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struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap); |
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u8 comm_len = 0; |
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int i, err; |
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err = mlxcpld_i2c_check_msg_params(priv, msgs, num); |
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if (err) { |
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dev_err(priv->dev, "Incorrect message\n"); |
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return err; |
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} |
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for (i = 0; i < num; ++i) |
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comm_len += msgs[i].len; |
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/* Check bus state */ |
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if (mlxcpld_i2c_wait_for_free(priv)) { |
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dev_err(priv->dev, "LPCI2C bridge is busy\n"); |
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/* |
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* Usually it means something serious has happened. |
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* We can not have unfinished previous transfer |
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* so it doesn't make any sense to try to stop it. |
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* Probably we were not able to recover from the |
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* previous error. |
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* The only reasonable thing - is soft reset. |
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*/ |
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mlxcpld_i2c_reset(priv); |
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if (mlxcpld_i2c_check_busy(priv)) { |
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dev_err(priv->dev, "LPCI2C bridge is busy after reset\n"); |
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return -EIO; |
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} |
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} |
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mlxcpld_i2c_set_transf_data(priv, msgs, num, comm_len); |
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mutex_lock(&priv->lock); |
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/* Do real transfer. Can't fail */ |
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mlxcpld_i2c_xfer_msg(priv); |
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/* Wait for transaction complete */ |
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err = mlxcpld_i2c_wait_for_tc(priv); |
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mutex_unlock(&priv->lock); |
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return err < 0 ? err : num; |
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} |
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static u32 mlxcpld_i2c_func(struct i2c_adapter *adap) |
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{ |
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struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap); |
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if (priv->smbus_block) |
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
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I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_BLOCK_DATA; |
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else |
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
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I2C_FUNC_SMBUS_I2C_BLOCK; |
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} |
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static const struct i2c_algorithm mlxcpld_i2c_algo = { |
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.master_xfer = mlxcpld_i2c_xfer, |
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.functionality = mlxcpld_i2c_func |
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}; |
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static const struct i2c_adapter_quirks mlxcpld_i2c_quirks = { |
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.flags = I2C_AQ_COMB_WRITE_THEN_READ, |
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.max_read_len = MLXCPLD_I2C_DATA_REG_SZ - MLXCPLD_I2C_MAX_ADDR_LEN, |
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.max_write_len = MLXCPLD_I2C_DATA_REG_SZ, |
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.max_comb_1st_msg_len = 4, |
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}; |
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static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext = { |
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.flags = I2C_AQ_COMB_WRITE_THEN_READ, |
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.max_read_len = MLXCPLD_I2C_DATA_REG_SZ * 2 - MLXCPLD_I2C_MAX_ADDR_LEN, |
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.max_write_len = MLXCPLD_I2C_DATA_REG_SZ * 2, |
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.max_comb_1st_msg_len = 4, |
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}; |
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static struct i2c_adapter mlxcpld_i2c_adapter = { |
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.owner = THIS_MODULE, |
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.name = "i2c-mlxcpld", |
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.class = I2C_CLASS_HWMON | I2C_CLASS_SPD, |
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.algo = &mlxcpld_i2c_algo, |
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.quirks = &mlxcpld_i2c_quirks, |
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.retries = MLXCPLD_I2C_RETR_NUM, |
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.nr = MLXCPLD_I2C_BUS_NUM, |
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}; |
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static int |
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mlxcpld_i2c_set_frequency(struct mlxcpld_i2c_priv *priv, |
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struct mlxreg_core_hotplug_platform_data *pdata) |
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{ |
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struct mlxreg_core_item *item = pdata->items; |
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struct mlxreg_core_data *data; |
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u32 regval; |
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u8 freq; |
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int err; |
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if (!item) |
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return 0; |
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/* Read frequency setting. */ |
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data = item->data; |
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err = regmap_read(pdata->regmap, data->reg, ®val); |
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if (err) |
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return err; |
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/* Set frequency only if it is not 100KHz, which is default. */ |
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switch ((regval & data->mask) >> data->bit) { |
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case MLXCPLD_I2C_FREQ_1000KHZ: |
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freq = MLXCPLD_I2C_FREQ_1000KHZ_SET; |
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break; |
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case MLXCPLD_I2C_FREQ_400KHZ: |
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freq = MLXCPLD_I2C_FREQ_400KHZ_SET; |
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break; |
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default: |
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return 0; |
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} |
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mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_HALF_CYC_REG, &freq, 1); |
|
|
|
return 0; |
|
} |
|
|
|
static int mlxcpld_i2c_probe(struct platform_device *pdev) |
|
{ |
|
struct mlxreg_core_hotplug_platform_data *pdata; |
|
struct mlxcpld_i2c_priv *priv; |
|
int err; |
|
u8 val; |
|
|
|
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
mutex_init(&priv->lock); |
|
platform_set_drvdata(pdev, priv); |
|
|
|
priv->dev = &pdev->dev; |
|
priv->base_addr = MLXPLAT_CPLD_LPC_I2C_BASE_ADDR; |
|
|
|
/* Set I2C bus frequency if platform data provides this info. */ |
|
pdata = dev_get_platdata(&pdev->dev); |
|
if (pdata) { |
|
err = mlxcpld_i2c_set_frequency(priv, pdata); |
|
if (err) |
|
goto mlxcpld_i2_probe_failed; |
|
} |
|
|
|
/* Register with i2c layer */ |
|
mlxcpld_i2c_adapter.timeout = usecs_to_jiffies(MLXCPLD_I2C_XFER_TO); |
|
/* Read capability register */ |
|
mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CPBLTY_REG, &val, 1); |
|
/* Check support for extended transaction length */ |
|
if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_SZ_BIT) |
|
mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext; |
|
/* Check support for smbus block transaction */ |
|
if (val & MLXCPLD_I2C_SMBUS_BLK_BIT) |
|
priv->smbus_block = true; |
|
if (pdev->id >= -1) |
|
mlxcpld_i2c_adapter.nr = pdev->id; |
|
priv->adap = mlxcpld_i2c_adapter; |
|
priv->adap.dev.parent = &pdev->dev; |
|
i2c_set_adapdata(&priv->adap, priv); |
|
|
|
err = i2c_add_numbered_adapter(&priv->adap); |
|
if (err) |
|
goto mlxcpld_i2_probe_failed; |
|
|
|
return 0; |
|
|
|
mlxcpld_i2_probe_failed: |
|
mutex_destroy(&priv->lock); |
|
return err; |
|
} |
|
|
|
static int mlxcpld_i2c_remove(struct platform_device *pdev) |
|
{ |
|
struct mlxcpld_i2c_priv *priv = platform_get_drvdata(pdev); |
|
|
|
i2c_del_adapter(&priv->adap); |
|
mutex_destroy(&priv->lock); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver mlxcpld_i2c_driver = { |
|
.probe = mlxcpld_i2c_probe, |
|
.remove = mlxcpld_i2c_remove, |
|
.driver = { |
|
.name = MLXCPLD_I2C_DEVICE_NAME, |
|
}, |
|
}; |
|
|
|
module_platform_driver(mlxcpld_i2c_driver); |
|
|
|
MODULE_AUTHOR("Michael Shych <[email protected]>"); |
|
MODULE_DESCRIPTION("Mellanox I2C-CPLD controller driver"); |
|
MODULE_LICENSE("Dual BSD/GPL"); |
|
MODULE_ALIAS("platform:i2c-mlxcpld");
|
|
|