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504 lines
14 KiB
504 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* HiSilicon I2C Controller Driver for Kunpeng SoC |
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* |
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* Copyright (c) 2021 HiSilicon Technologies Co., Ltd. |
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*/ |
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#include <linux/bits.h> |
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#include <linux/bitfield.h> |
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#include <linux/completion.h> |
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#include <linux/i2c.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/platform_device.h> |
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#include <linux/property.h> |
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#define HISI_I2C_FRAME_CTRL 0x0000 |
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#define HISI_I2C_FRAME_CTRL_SPEED_MODE GENMASK(1, 0) |
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#define HISI_I2C_FRAME_CTRL_ADDR_TEN BIT(2) |
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#define HISI_I2C_SLV_ADDR 0x0004 |
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#define HISI_I2C_SLV_ADDR_VAL GENMASK(9, 0) |
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#define HISI_I2C_SLV_ADDR_GC_S_MODE BIT(10) |
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#define HISI_I2C_SLV_ADDR_GC_S_EN BIT(11) |
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#define HISI_I2C_CMD_TXDATA 0x0008 |
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#define HISI_I2C_CMD_TXDATA_DATA GENMASK(7, 0) |
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#define HISI_I2C_CMD_TXDATA_RW BIT(8) |
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#define HISI_I2C_CMD_TXDATA_P_EN BIT(9) |
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#define HISI_I2C_CMD_TXDATA_SR_EN BIT(10) |
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#define HISI_I2C_RXDATA 0x000c |
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#define HISI_I2C_RXDATA_DATA GENMASK(7, 0) |
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#define HISI_I2C_SS_SCL_HCNT 0x0010 |
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#define HISI_I2C_SS_SCL_LCNT 0x0014 |
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#define HISI_I2C_FS_SCL_HCNT 0x0018 |
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#define HISI_I2C_FS_SCL_LCNT 0x001c |
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#define HISI_I2C_HS_SCL_HCNT 0x0020 |
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#define HISI_I2C_HS_SCL_LCNT 0x0024 |
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#define HISI_I2C_FIFO_CTRL 0x0028 |
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#define HISI_I2C_FIFO_RX_CLR BIT(0) |
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#define HISI_I2C_FIFO_TX_CLR BIT(1) |
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#define HISI_I2C_FIFO_RX_AF_THRESH GENMASK(7, 2) |
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#define HISI_I2C_FIFO_TX_AE_THRESH GENMASK(13, 8) |
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#define HISI_I2C_FIFO_STATE 0x002c |
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#define HISI_I2C_FIFO_STATE_RX_RERR BIT(0) |
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#define HISI_I2C_FIFO_STATE_RX_WERR BIT(1) |
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#define HISI_I2C_FIFO_STATE_RX_EMPTY BIT(3) |
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#define HISI_I2C_FIFO_STATE_TX_RERR BIT(6) |
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#define HISI_I2C_FIFO_STATE_TX_WERR BIT(7) |
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#define HISI_I2C_FIFO_STATE_TX_FULL BIT(11) |
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#define HISI_I2C_SDA_HOLD 0x0030 |
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#define HISI_I2C_SDA_HOLD_TX GENMASK(15, 0) |
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#define HISI_I2C_SDA_HOLD_RX GENMASK(23, 16) |
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#define HISI_I2C_FS_SPK_LEN 0x0038 |
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#define HISI_I2C_FS_SPK_LEN_CNT GENMASK(7, 0) |
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#define HISI_I2C_HS_SPK_LEN 0x003c |
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#define HISI_I2C_HS_SPK_LEN_CNT GENMASK(7, 0) |
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#define HISI_I2C_INT_MSTAT 0x0044 |
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#define HISI_I2C_INT_CLR 0x0048 |
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#define HISI_I2C_INT_MASK 0x004C |
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#define HISI_I2C_TRANS_STATE 0x0050 |
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#define HISI_I2C_TRANS_ERR 0x0054 |
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#define HISI_I2C_VERSION 0x0058 |
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#define HISI_I2C_INT_ALL GENMASK(4, 0) |
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#define HISI_I2C_INT_TRANS_CPLT BIT(0) |
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#define HISI_I2C_INT_TRANS_ERR BIT(1) |
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#define HISI_I2C_INT_FIFO_ERR BIT(2) |
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#define HISI_I2C_INT_RX_FULL BIT(3) |
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#define HISI_I2C_INT_TX_EMPTY BIT(4) |
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#define HISI_I2C_INT_ERR \ |
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(HISI_I2C_INT_TRANS_ERR | HISI_I2C_INT_FIFO_ERR) |
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#define HISI_I2C_STD_SPEED_MODE 0 |
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#define HISI_I2C_FAST_SPEED_MODE 1 |
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#define HISI_I2C_HIGH_SPEED_MODE 2 |
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#define HISI_I2C_TX_FIFO_DEPTH 64 |
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#define HISI_I2C_RX_FIFO_DEPTH 64 |
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#define HISI_I2C_TX_F_AE_THRESH 1 |
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#define HISI_I2C_RX_F_AF_THRESH 60 |
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#define HZ_PER_KHZ 1000 |
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#define NSEC_TO_CYCLES(ns, clk_rate_khz) \ |
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DIV_ROUND_UP_ULL((clk_rate_khz) * (ns), NSEC_PER_MSEC) |
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struct hisi_i2c_controller { |
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struct i2c_adapter adapter; |
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void __iomem *iobase; |
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struct device *dev; |
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int irq; |
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/* Intermediates for recording the transfer process */ |
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struct completion *completion; |
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struct i2c_msg *msgs; |
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int msg_num; |
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int msg_tx_idx; |
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int buf_tx_idx; |
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int msg_rx_idx; |
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int buf_rx_idx; |
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u16 tar_addr; |
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u32 xfer_err; |
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/* I2C bus configuration */ |
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struct i2c_timings t; |
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u32 clk_rate_khz; |
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u32 spk_len; |
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}; |
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static void hisi_i2c_enable_int(struct hisi_i2c_controller *ctlr, u32 mask) |
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{ |
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writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); |
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} |
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static void hisi_i2c_disable_int(struct hisi_i2c_controller *ctlr, u32 mask) |
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{ |
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writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); |
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} |
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static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask) |
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{ |
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writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); |
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} |
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static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr) |
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{ |
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u32 int_err = ctlr->xfer_err, reg; |
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if (int_err & HISI_I2C_INT_FIFO_ERR) { |
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reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); |
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if (reg & HISI_I2C_FIFO_STATE_RX_RERR) |
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dev_err(ctlr->dev, "rx fifo error read\n"); |
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if (reg & HISI_I2C_FIFO_STATE_RX_WERR) |
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dev_err(ctlr->dev, "rx fifo error write\n"); |
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if (reg & HISI_I2C_FIFO_STATE_TX_RERR) |
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dev_err(ctlr->dev, "tx fifo error read\n"); |
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if (reg & HISI_I2C_FIFO_STATE_TX_WERR) |
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dev_err(ctlr->dev, "tx fifo error write\n"); |
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} |
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} |
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static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr) |
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{ |
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struct i2c_msg *msg = ctlr->msgs; |
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u32 reg; |
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reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); |
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reg &= ~HISI_I2C_FRAME_CTRL_ADDR_TEN; |
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if (msg->flags & I2C_M_TEN) |
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reg |= HISI_I2C_FRAME_CTRL_ADDR_TEN; |
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writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); |
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reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR); |
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reg &= ~HISI_I2C_SLV_ADDR_VAL; |
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reg |= FIELD_PREP(HISI_I2C_SLV_ADDR_VAL, msg->addr); |
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writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR); |
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reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL); |
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reg |= HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR; |
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writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); |
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reg &= ~(HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR); |
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writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); |
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hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); |
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hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL); |
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return 0; |
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} |
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static void hisi_i2c_reset_xfer(struct hisi_i2c_controller *ctlr) |
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{ |
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ctlr->msg_num = 0; |
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ctlr->xfer_err = 0; |
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ctlr->msg_tx_idx = 0; |
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ctlr->msg_rx_idx = 0; |
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ctlr->buf_tx_idx = 0; |
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ctlr->buf_rx_idx = 0; |
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} |
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/* |
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* Initialize the transfer information and start the I2C bus transfer. |
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* We only configure the transfer and do some pre/post works here, and |
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* wait for the transfer done. The major transfer process is performed |
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* in the IRQ handler. |
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*/ |
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static int hisi_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, |
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int num) |
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{ |
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struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap); |
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DECLARE_COMPLETION_ONSTACK(done); |
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int ret = num; |
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hisi_i2c_reset_xfer(ctlr); |
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ctlr->completion = &done; |
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ctlr->msg_num = num; |
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ctlr->msgs = msgs; |
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hisi_i2c_start_xfer(ctlr); |
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if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) { |
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hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); |
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synchronize_irq(ctlr->irq); |
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i2c_recover_bus(&ctlr->adapter); |
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dev_err(ctlr->dev, "bus transfer timeout\n"); |
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ret = -EIO; |
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} |
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if (ctlr->xfer_err) { |
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hisi_i2c_handle_errors(ctlr); |
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ret = -EIO; |
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} |
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hisi_i2c_reset_xfer(ctlr); |
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ctlr->completion = NULL; |
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return ret; |
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} |
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static u32 hisi_i2c_functionality(struct i2c_adapter *adap) |
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{ |
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return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; |
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} |
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static const struct i2c_algorithm hisi_i2c_algo = { |
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.master_xfer = hisi_i2c_master_xfer, |
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.functionality = hisi_i2c_functionality, |
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}; |
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static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr) |
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{ |
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struct i2c_msg *cur_msg; |
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u32 fifo_state; |
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while (ctlr->msg_rx_idx < ctlr->msg_num) { |
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cur_msg = ctlr->msgs + ctlr->msg_rx_idx; |
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if (!(cur_msg->flags & I2C_M_RD)) { |
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ctlr->msg_rx_idx++; |
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continue; |
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} |
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fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); |
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while (!(fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) && |
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ctlr->buf_rx_idx < cur_msg->len) { |
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cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA); |
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fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); |
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} |
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if (ctlr->buf_rx_idx == cur_msg->len) { |
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ctlr->buf_rx_idx = 0; |
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ctlr->msg_rx_idx++; |
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} |
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if (fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) |
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break; |
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} |
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return 0; |
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} |
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static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) |
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{ |
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int max_write = HISI_I2C_TX_FIFO_DEPTH; |
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bool need_restart = false, last_msg; |
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struct i2c_msg *cur_msg; |
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u32 cmd, fifo_state; |
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while (ctlr->msg_tx_idx < ctlr->msg_num) { |
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cur_msg = ctlr->msgs + ctlr->msg_tx_idx; |
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last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1); |
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/* Signal the SR bit when we start transferring a new message */ |
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if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx) |
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need_restart = true; |
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fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); |
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while (!(fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) && |
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ctlr->buf_tx_idx < cur_msg->len && max_write) { |
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cmd = 0; |
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if (need_restart) { |
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cmd |= HISI_I2C_CMD_TXDATA_SR_EN; |
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need_restart = false; |
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} |
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/* Signal the STOP bit at the last frame of the last message */ |
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if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg) |
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cmd |= HISI_I2C_CMD_TXDATA_P_EN; |
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if (cur_msg->flags & I2C_M_RD) |
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cmd |= HISI_I2C_CMD_TXDATA_RW; |
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else |
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cmd |= FIELD_PREP(HISI_I2C_CMD_TXDATA_DATA, |
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cur_msg->buf[ctlr->buf_tx_idx]); |
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writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA); |
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ctlr->buf_tx_idx++; |
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max_write--; |
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fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); |
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} |
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/* Update the transfer index after per message transfer is done. */ |
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if (ctlr->buf_tx_idx == cur_msg->len) { |
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ctlr->buf_tx_idx = 0; |
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ctlr->msg_tx_idx++; |
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} |
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if ((fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) || |
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max_write == 0) |
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break; |
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} |
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} |
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static irqreturn_t hisi_i2c_irq(int irq, void *context) |
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{ |
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struct hisi_i2c_controller *ctlr = context; |
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u32 int_stat; |
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int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT); |
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hisi_i2c_clear_int(ctlr, int_stat); |
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if (!(int_stat & HISI_I2C_INT_ALL)) |
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return IRQ_NONE; |
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if (int_stat & HISI_I2C_INT_TX_EMPTY) |
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hisi_i2c_xfer_msg(ctlr); |
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if (int_stat & HISI_I2C_INT_ERR) { |
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ctlr->xfer_err = int_stat; |
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goto out; |
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} |
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/* Drain the rx fifo before finish the transfer */ |
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if (int_stat & (HISI_I2C_INT_TRANS_CPLT | HISI_I2C_INT_RX_FULL)) |
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hisi_i2c_read_rx_fifo(ctlr); |
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out: |
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if (int_stat & HISI_I2C_INT_TRANS_CPLT || ctlr->xfer_err) { |
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hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); |
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hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); |
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complete(ctlr->completion); |
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} |
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return IRQ_HANDLED; |
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} |
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/* |
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* Helper function for calculating and configuring the HIGH and LOW |
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* periods of SCL clock. The caller will pass the ratio of the |
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* counts (divide / divisor) according to the target speed mode, |
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* and the target registers. |
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*/ |
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static void hisi_i2c_set_scl(struct hisi_i2c_controller *ctlr, |
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u32 divide, u32 divisor, |
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u32 reg_hcnt, u32 reg_lcnt) |
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{ |
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u32 total_cnt, t_scl_hcnt, t_scl_lcnt, scl_fall_cnt, scl_rise_cnt; |
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u32 scl_hcnt, scl_lcnt; |
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/* Total SCL clock cycles per speed period */ |
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total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz); |
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/* Total HIGH level SCL clock cycles including edges */ |
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t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor); |
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/* Total LOW level SCL clock cycles including edges */ |
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t_scl_lcnt = total_cnt - t_scl_hcnt; |
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/* Fall edge SCL clock cycles */ |
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scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz); |
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/* Rise edge SCL clock cycles */ |
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scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz); |
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/* Calculated HIGH and LOW periods of SCL clock */ |
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scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt; |
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scl_lcnt = t_scl_lcnt - 1 - scl_rise_cnt; |
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writel(scl_hcnt, ctlr->iobase + reg_hcnt); |
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writel(scl_lcnt, ctlr->iobase + reg_lcnt); |
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} |
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static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr) |
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{ |
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u32 reg, sda_hold_cnt, speed_mode; |
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i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true); |
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ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz); |
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switch (ctlr->t.bus_freq_hz) { |
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case I2C_MAX_FAST_MODE_FREQ: |
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speed_mode = HISI_I2C_FAST_SPEED_MODE; |
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hisi_i2c_set_scl(ctlr, 26, 76, HISI_I2C_FS_SCL_HCNT, HISI_I2C_FS_SCL_LCNT); |
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break; |
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case I2C_MAX_HIGH_SPEED_MODE_FREQ: |
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speed_mode = HISI_I2C_HIGH_SPEED_MODE; |
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hisi_i2c_set_scl(ctlr, 6, 22, HISI_I2C_HS_SCL_HCNT, HISI_I2C_HS_SCL_LCNT); |
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break; |
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case I2C_MAX_STANDARD_MODE_FREQ: |
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default: |
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speed_mode = HISI_I2C_STD_SPEED_MODE; |
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/* For default condition force the bus speed to standard mode. */ |
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ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; |
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hisi_i2c_set_scl(ctlr, 40, 87, HISI_I2C_SS_SCL_HCNT, HISI_I2C_SS_SCL_LCNT); |
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break; |
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} |
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reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); |
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reg &= ~HISI_I2C_FRAME_CTRL_SPEED_MODE; |
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reg |= FIELD_PREP(HISI_I2C_FRAME_CTRL_SPEED_MODE, speed_mode); |
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writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); |
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sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz); |
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reg = FIELD_PREP(HISI_I2C_SDA_HOLD_TX, sda_hold_cnt); |
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writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD); |
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writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN); |
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reg = FIELD_PREP(HISI_I2C_FIFO_RX_AF_THRESH, HISI_I2C_RX_F_AF_THRESH); |
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reg |= FIELD_PREP(HISI_I2C_FIFO_TX_AE_THRESH, HISI_I2C_TX_F_AE_THRESH); |
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writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); |
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} |
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static int hisi_i2c_probe(struct platform_device *pdev) |
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{ |
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struct hisi_i2c_controller *ctlr; |
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struct device *dev = &pdev->dev; |
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struct i2c_adapter *adapter; |
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u64 clk_rate_hz; |
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u32 hw_version; |
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int ret; |
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|
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ctlr = devm_kzalloc(dev, sizeof(*ctlr), GFP_KERNEL); |
|
if (!ctlr) |
|
return -ENOMEM; |
|
|
|
ctlr->iobase = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(ctlr->iobase)) |
|
return PTR_ERR(ctlr->iobase); |
|
|
|
ctlr->irq = platform_get_irq(pdev, 0); |
|
if (ctlr->irq < 0) |
|
return ctlr->irq; |
|
|
|
ctlr->dev = dev; |
|
|
|
hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); |
|
|
|
ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr); |
|
if (ret) { |
|
dev_err(dev, "failed to request irq handler, ret = %d\n", ret); |
|
return ret; |
|
} |
|
|
|
ret = device_property_read_u64(dev, "clk_rate", &clk_rate_hz); |
|
if (ret) { |
|
dev_err(dev, "failed to get clock frequency, ret = %d\n", ret); |
|
return ret; |
|
} |
|
|
|
ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ); |
|
|
|
hisi_i2c_configure_bus(ctlr); |
|
|
|
adapter = &ctlr->adapter; |
|
snprintf(adapter->name, sizeof(adapter->name), |
|
"HiSilicon I2C Controller %s", dev_name(dev)); |
|
adapter->owner = THIS_MODULE; |
|
adapter->algo = &hisi_i2c_algo; |
|
adapter->dev.parent = dev; |
|
i2c_set_adapdata(adapter, ctlr); |
|
|
|
ret = devm_i2c_add_adapter(dev, adapter); |
|
if (ret) |
|
return ret; |
|
|
|
hw_version = readl(ctlr->iobase + HISI_I2C_VERSION); |
|
dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n", |
|
i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct acpi_device_id hisi_i2c_acpi_ids[] = { |
|
{ "HISI03D1", 0 }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(acpi, hisi_i2c_acpi_ids); |
|
|
|
static struct platform_driver hisi_i2c_driver = { |
|
.probe = hisi_i2c_probe, |
|
.driver = { |
|
.name = "hisi-i2c", |
|
.acpi_match_table = hisi_i2c_acpi_ids, |
|
}, |
|
}; |
|
module_platform_driver(hisi_i2c_driver); |
|
|
|
MODULE_AUTHOR("Yicong Yang <[email protected]>"); |
|
MODULE_DESCRIPTION("HiSilicon I2C Controller Driver"); |
|
MODULE_LICENSE("GPL");
|
|
|