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451 lines
11 KiB
451 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* I2C driver for the Renesas EMEV2 SoC |
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* |
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* Copyright (C) 2015 Wolfram Sang <[email protected]> |
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* Copyright 2013 Codethink Ltd. |
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* Copyright 2010-2015 Renesas Electronics Corporation |
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*/ |
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#include <linux/clk.h> |
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#include <linux/completion.h> |
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#include <linux/device.h> |
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#include <linux/i2c.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/sched.h> |
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/* I2C Registers */ |
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#define I2C_OFS_IICACT0 0x00 /* start */ |
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#define I2C_OFS_IIC0 0x04 /* shift */ |
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#define I2C_OFS_IICC0 0x08 /* control */ |
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#define I2C_OFS_SVA0 0x0c /* slave address */ |
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#define I2C_OFS_IICCL0 0x10 /* clock select */ |
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#define I2C_OFS_IICX0 0x14 /* extension */ |
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#define I2C_OFS_IICS0 0x18 /* status */ |
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#define I2C_OFS_IICSE0 0x1c /* status For emulation */ |
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#define I2C_OFS_IICF0 0x20 /* IIC flag */ |
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/* I2C IICACT0 Masks */ |
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#define I2C_BIT_IICE0 0x0001 |
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/* I2C IICC0 Masks */ |
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#define I2C_BIT_LREL0 0x0040 |
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#define I2C_BIT_WREL0 0x0020 |
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#define I2C_BIT_SPIE0 0x0010 |
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#define I2C_BIT_WTIM0 0x0008 |
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#define I2C_BIT_ACKE0 0x0004 |
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#define I2C_BIT_STT0 0x0002 |
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#define I2C_BIT_SPT0 0x0001 |
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/* I2C IICCL0 Masks */ |
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#define I2C_BIT_SMC0 0x0008 |
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#define I2C_BIT_DFC0 0x0004 |
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/* I2C IICSE0 Masks */ |
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#define I2C_BIT_MSTS0 0x0080 |
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#define I2C_BIT_ALD0 0x0040 |
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#define I2C_BIT_EXC0 0x0020 |
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#define I2C_BIT_COI0 0x0010 |
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#define I2C_BIT_TRC0 0x0008 |
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#define I2C_BIT_ACKD0 0x0004 |
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#define I2C_BIT_STD0 0x0002 |
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#define I2C_BIT_SPD0 0x0001 |
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/* I2C IICF0 Masks */ |
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#define I2C_BIT_STCF 0x0080 |
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#define I2C_BIT_IICBSY 0x0040 |
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#define I2C_BIT_STCEN 0x0002 |
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#define I2C_BIT_IICRSV 0x0001 |
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struct em_i2c_device { |
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void __iomem *base; |
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struct i2c_adapter adap; |
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struct completion msg_done; |
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struct clk *sclk; |
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struct i2c_client *slave; |
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int irq; |
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}; |
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static inline void em_clear_set_bit(struct em_i2c_device *priv, u8 clear, u8 set, u8 reg) |
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{ |
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writeb((readb(priv->base + reg) & ~clear) | set, priv->base + reg); |
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} |
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static int em_i2c_wait_for_event(struct em_i2c_device *priv) |
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{ |
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unsigned long time_left; |
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int status; |
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reinit_completion(&priv->msg_done); |
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time_left = wait_for_completion_timeout(&priv->msg_done, priv->adap.timeout); |
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if (!time_left) |
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return -ETIMEDOUT; |
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status = readb(priv->base + I2C_OFS_IICSE0); |
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return status & I2C_BIT_ALD0 ? -EAGAIN : status; |
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} |
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static void em_i2c_stop(struct em_i2c_device *priv) |
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{ |
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/* Send Stop condition */ |
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em_clear_set_bit(priv, 0, I2C_BIT_SPT0 | I2C_BIT_SPIE0, I2C_OFS_IICC0); |
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/* Wait for stop condition */ |
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em_i2c_wait_for_event(priv); |
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} |
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static void em_i2c_reset(struct i2c_adapter *adap) |
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{ |
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struct em_i2c_device *priv = i2c_get_adapdata(adap); |
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int retr; |
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/* If I2C active */ |
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if (readb(priv->base + I2C_OFS_IICACT0) & I2C_BIT_IICE0) { |
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/* Disable I2C operation */ |
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writeb(0, priv->base + I2C_OFS_IICACT0); |
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retr = 1000; |
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while (readb(priv->base + I2C_OFS_IICACT0) == 1 && retr) |
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retr--; |
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WARN_ON(retr == 0); |
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} |
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/* Transfer mode set */ |
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writeb(I2C_BIT_DFC0, priv->base + I2C_OFS_IICCL0); |
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/* Can Issue start without detecting a stop, Reservation disabled. */ |
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writeb(I2C_BIT_STCEN | I2C_BIT_IICRSV, priv->base + I2C_OFS_IICF0); |
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/* I2C enable, 9 bit interrupt mode */ |
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writeb(I2C_BIT_WTIM0, priv->base + I2C_OFS_IICC0); |
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/* Enable I2C operation */ |
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writeb(I2C_BIT_IICE0, priv->base + I2C_OFS_IICACT0); |
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retr = 1000; |
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while (readb(priv->base + I2C_OFS_IICACT0) == 0 && retr) |
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retr--; |
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WARN_ON(retr == 0); |
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} |
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static int __em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, |
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int stop) |
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{ |
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struct em_i2c_device *priv = i2c_get_adapdata(adap); |
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int count, status, read = !!(msg->flags & I2C_M_RD); |
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/* Send start condition */ |
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em_clear_set_bit(priv, 0, I2C_BIT_ACKE0 | I2C_BIT_WTIM0, I2C_OFS_IICC0); |
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em_clear_set_bit(priv, 0, I2C_BIT_STT0, I2C_OFS_IICC0); |
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/* Send slave address and R/W type */ |
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writeb(i2c_8bit_addr_from_msg(msg), priv->base + I2C_OFS_IIC0); |
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/* Wait for transaction */ |
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status = em_i2c_wait_for_event(priv); |
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if (status < 0) |
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goto out_reset; |
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/* Received NACK (result of setting slave address and R/W) */ |
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if (!(status & I2C_BIT_ACKD0)) { |
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em_i2c_stop(priv); |
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goto out; |
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} |
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/* Extra setup for read transactions */ |
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if (read) { |
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/* 8 bit interrupt mode */ |
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em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0, I2C_OFS_IICC0); |
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em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0, I2C_OFS_IICC0); |
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/* Wait for transaction */ |
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status = em_i2c_wait_for_event(priv); |
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if (status < 0) |
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goto out_reset; |
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} |
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/* Send / receive data */ |
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for (count = 0; count < msg->len; count++) { |
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if (read) { /* Read transaction */ |
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msg->buf[count] = readb(priv->base + I2C_OFS_IIC0); |
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em_clear_set_bit(priv, 0, I2C_BIT_WREL0, I2C_OFS_IICC0); |
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} else { /* Write transaction */ |
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/* Received NACK */ |
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if (!(status & I2C_BIT_ACKD0)) { |
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em_i2c_stop(priv); |
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goto out; |
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} |
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/* Write data */ |
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writeb(msg->buf[count], priv->base + I2C_OFS_IIC0); |
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} |
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/* Wait for R/W transaction */ |
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status = em_i2c_wait_for_event(priv); |
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if (status < 0) |
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goto out_reset; |
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} |
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if (stop) |
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em_i2c_stop(priv); |
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return count; |
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out_reset: |
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em_i2c_reset(adap); |
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out: |
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return status < 0 ? status : -ENXIO; |
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} |
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static int em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, |
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int num) |
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{ |
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struct em_i2c_device *priv = i2c_get_adapdata(adap); |
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int ret, i; |
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if (readb(priv->base + I2C_OFS_IICF0) & I2C_BIT_IICBSY) |
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return -EAGAIN; |
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for (i = 0; i < num; i++) { |
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ret = __em_i2c_xfer(adap, &msgs[i], (i == (num - 1))); |
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if (ret < 0) |
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return ret; |
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} |
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/* I2C transfer completed */ |
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return num; |
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} |
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static bool em_i2c_slave_irq(struct em_i2c_device *priv) |
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{ |
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u8 status, value; |
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enum i2c_slave_event event; |
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int ret; |
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if (!priv->slave) |
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return false; |
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status = readb(priv->base + I2C_OFS_IICSE0); |
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/* Extension code, do not participate */ |
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if (status & I2C_BIT_EXC0) { |
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em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0); |
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return true; |
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} |
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/* Stop detected, we don't know if it's for slave or master */ |
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if (status & I2C_BIT_SPD0) { |
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/* Notify slave device */ |
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i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); |
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/* Pretend we did not handle the interrupt */ |
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return false; |
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} |
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/* Only handle interrupts addressed to us */ |
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if (!(status & I2C_BIT_COI0)) |
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return false; |
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/* Enable stop interrupts */ |
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em_clear_set_bit(priv, 0, I2C_BIT_SPIE0, I2C_OFS_IICC0); |
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/* Transmission or Reception */ |
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if (status & I2C_BIT_TRC0) { |
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if (status & I2C_BIT_ACKD0) { |
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/* 9 bit interrupt mode */ |
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em_clear_set_bit(priv, 0, I2C_BIT_WTIM0, I2C_OFS_IICC0); |
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/* Send data */ |
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event = status & I2C_BIT_STD0 ? |
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I2C_SLAVE_READ_REQUESTED : |
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I2C_SLAVE_READ_PROCESSED; |
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i2c_slave_event(priv->slave, event, &value); |
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writeb(value, priv->base + I2C_OFS_IIC0); |
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} else { |
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/* NACK, stop transmitting */ |
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em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0); |
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} |
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} else { |
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/* 8 bit interrupt mode */ |
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em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0, |
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I2C_OFS_IICC0); |
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em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0, |
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I2C_OFS_IICC0); |
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if (status & I2C_BIT_STD0) { |
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i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, |
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&value); |
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} else { |
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/* Recv data */ |
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value = readb(priv->base + I2C_OFS_IIC0); |
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ret = i2c_slave_event(priv->slave, |
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I2C_SLAVE_WRITE_RECEIVED, &value); |
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if (ret < 0) |
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em_clear_set_bit(priv, I2C_BIT_ACKE0, 0, |
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I2C_OFS_IICC0); |
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} |
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} |
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return true; |
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} |
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static irqreturn_t em_i2c_irq_handler(int this_irq, void *dev_id) |
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{ |
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struct em_i2c_device *priv = dev_id; |
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if (em_i2c_slave_irq(priv)) |
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return IRQ_HANDLED; |
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complete(&priv->msg_done); |
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return IRQ_HANDLED; |
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} |
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static u32 em_i2c_func(struct i2c_adapter *adap) |
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{ |
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE; |
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} |
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static int em_i2c_reg_slave(struct i2c_client *slave) |
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{ |
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struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter); |
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if (priv->slave) |
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return -EBUSY; |
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if (slave->flags & I2C_CLIENT_TEN) |
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return -EAFNOSUPPORT; |
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priv->slave = slave; |
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/* Set slave address */ |
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writeb(slave->addr << 1, priv->base + I2C_OFS_SVA0); |
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return 0; |
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} |
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static int em_i2c_unreg_slave(struct i2c_client *slave) |
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{ |
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struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter); |
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WARN_ON(!priv->slave); |
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writeb(0, priv->base + I2C_OFS_SVA0); |
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/* |
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* Wait for interrupt to finish. New slave irqs cannot happen because we |
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* cleared the slave address and, thus, only extension codes will be |
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* detected which do not use the slave ptr. |
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*/ |
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synchronize_irq(priv->irq); |
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priv->slave = NULL; |
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return 0; |
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} |
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static const struct i2c_algorithm em_i2c_algo = { |
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.master_xfer = em_i2c_xfer, |
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.functionality = em_i2c_func, |
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.reg_slave = em_i2c_reg_slave, |
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.unreg_slave = em_i2c_unreg_slave, |
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}; |
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static int em_i2c_probe(struct platform_device *pdev) |
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{ |
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struct em_i2c_device *priv; |
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int ret; |
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(priv->base)) |
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return PTR_ERR(priv->base); |
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strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name)); |
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priv->sclk = devm_clk_get(&pdev->dev, "sclk"); |
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if (IS_ERR(priv->sclk)) |
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return PTR_ERR(priv->sclk); |
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ret = clk_prepare_enable(priv->sclk); |
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if (ret) |
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return ret; |
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priv->adap.timeout = msecs_to_jiffies(100); |
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priv->adap.retries = 5; |
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priv->adap.dev.parent = &pdev->dev; |
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priv->adap.algo = &em_i2c_algo; |
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priv->adap.owner = THIS_MODULE; |
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priv->adap.dev.of_node = pdev->dev.of_node; |
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init_completion(&priv->msg_done); |
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platform_set_drvdata(pdev, priv); |
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i2c_set_adapdata(&priv->adap, priv); |
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em_i2c_reset(&priv->adap); |
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ret = platform_get_irq(pdev, 0); |
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if (ret < 0) |
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goto err_clk; |
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priv->irq = ret; |
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ret = devm_request_irq(&pdev->dev, priv->irq, em_i2c_irq_handler, 0, |
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"em_i2c", priv); |
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if (ret) |
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goto err_clk; |
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ret = i2c_add_adapter(&priv->adap); |
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if (ret) |
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goto err_clk; |
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dev_info(&pdev->dev, "Added i2c controller %d, irq %d\n", priv->adap.nr, |
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priv->irq); |
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return 0; |
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err_clk: |
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clk_disable_unprepare(priv->sclk); |
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return ret; |
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} |
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static int em_i2c_remove(struct platform_device *dev) |
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{ |
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struct em_i2c_device *priv = platform_get_drvdata(dev); |
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i2c_del_adapter(&priv->adap); |
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clk_disable_unprepare(priv->sclk); |
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return 0; |
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} |
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static const struct of_device_id em_i2c_ids[] = { |
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{ .compatible = "renesas,iic-emev2", }, |
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{ } |
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}; |
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static struct platform_driver em_i2c_driver = { |
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.probe = em_i2c_probe, |
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.remove = em_i2c_remove, |
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.driver = { |
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.name = "em-i2c", |
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.of_match_table = em_i2c_ids, |
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} |
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}; |
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module_platform_driver(em_i2c_driver); |
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MODULE_DESCRIPTION("EMEV2 I2C bus driver"); |
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MODULE_AUTHOR("Ian Molton"); |
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MODULE_AUTHOR("Wolfram Sang <[email protected]>"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_DEVICE_TABLE(of, em_i2c_ids);
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