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367 lines
9.7 KiB
367 lines
9.7 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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// |
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// MXC GPIO support. (c) 2008 Daniel Mack <[email protected]> |
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// Copyright 2008 Juergen Beisert, [email protected] |
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// |
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// Based on code from Freescale, |
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// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
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#include <linux/err.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/module.h> |
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#define MXS_SET 0x4 |
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#define MXS_CLR 0x8 |
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#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10) |
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#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10) |
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#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10) |
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#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10) |
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#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10) |
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#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10) |
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#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10) |
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#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10) |
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#define GPIO_INT_FALL_EDGE 0x0 |
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#define GPIO_INT_LOW_LEV 0x1 |
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#define GPIO_INT_RISE_EDGE 0x2 |
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#define GPIO_INT_HIGH_LEV 0x3 |
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#define GPIO_INT_LEV_MASK (1 << 0) |
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#define GPIO_INT_POL_MASK (1 << 1) |
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enum mxs_gpio_id { |
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IMX23_GPIO, |
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IMX28_GPIO, |
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}; |
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struct mxs_gpio_port { |
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void __iomem *base; |
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int id; |
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int irq; |
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struct irq_domain *domain; |
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struct gpio_chip gc; |
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struct device *dev; |
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enum mxs_gpio_id devid; |
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u32 both_edges; |
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}; |
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static inline int is_imx23_gpio(struct mxs_gpio_port *port) |
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{ |
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return port->devid == IMX23_GPIO; |
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} |
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/* Note: This driver assumes 32 GPIOs are handled in one register */ |
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static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type) |
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{ |
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u32 val; |
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u32 pin_mask = 1 << d->hwirq; |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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struct mxs_gpio_port *port = gc->private; |
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void __iomem *pin_addr; |
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int edge; |
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if (!(ct->type & type)) |
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if (irq_setup_alt_chip(d, type)) |
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return -EINVAL; |
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port->both_edges &= ~pin_mask; |
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switch (type) { |
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case IRQ_TYPE_EDGE_BOTH: |
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val = readl(port->base + PINCTRL_DIN(port)) & pin_mask; |
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if (val) |
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edge = GPIO_INT_FALL_EDGE; |
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else |
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edge = GPIO_INT_RISE_EDGE; |
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port->both_edges |= pin_mask; |
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break; |
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case IRQ_TYPE_EDGE_RISING: |
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edge = GPIO_INT_RISE_EDGE; |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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edge = GPIO_INT_FALL_EDGE; |
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break; |
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case IRQ_TYPE_LEVEL_LOW: |
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edge = GPIO_INT_LOW_LEV; |
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break; |
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case IRQ_TYPE_LEVEL_HIGH: |
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edge = GPIO_INT_HIGH_LEV; |
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break; |
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default: |
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return -EINVAL; |
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} |
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/* set level or edge */ |
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pin_addr = port->base + PINCTRL_IRQLEV(port); |
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if (edge & GPIO_INT_LEV_MASK) { |
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writel(pin_mask, pin_addr + MXS_SET); |
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writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET); |
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} else { |
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writel(pin_mask, pin_addr + MXS_CLR); |
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writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET); |
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} |
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/* set polarity */ |
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pin_addr = port->base + PINCTRL_IRQPOL(port); |
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if (edge & GPIO_INT_POL_MASK) |
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writel(pin_mask, pin_addr + MXS_SET); |
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else |
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writel(pin_mask, pin_addr + MXS_CLR); |
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writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR); |
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return 0; |
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} |
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static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio) |
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{ |
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u32 bit, val, edge; |
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void __iomem *pin_addr; |
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bit = 1 << gpio; |
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pin_addr = port->base + PINCTRL_IRQPOL(port); |
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val = readl(pin_addr); |
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edge = val & bit; |
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if (edge) |
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writel(bit, pin_addr + MXS_CLR); |
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else |
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writel(bit, pin_addr + MXS_SET); |
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} |
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/* MXS has one interrupt *per* gpio port */ |
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static void mxs_gpio_irq_handler(struct irq_desc *desc) |
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{ |
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u32 irq_stat; |
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struct mxs_gpio_port *port = irq_desc_get_handler_data(desc); |
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desc->irq_data.chip->irq_ack(&desc->irq_data); |
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irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) & |
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readl(port->base + PINCTRL_IRQEN(port)); |
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while (irq_stat != 0) { |
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int irqoffset = fls(irq_stat) - 1; |
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if (port->both_edges & (1 << irqoffset)) |
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mxs_flip_edge(port, irqoffset); |
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generic_handle_domain_irq(port->domain, irqoffset); |
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irq_stat &= ~(1 << irqoffset); |
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} |
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} |
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/* |
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* Set interrupt number "irq" in the GPIO as a wake-up source. |
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* While system is running, all registered GPIO interrupts need to have |
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* wake-up enabled. When system is suspended, only selected GPIO interrupts |
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* need to have wake-up enabled. |
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* @param irq interrupt source number |
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* @param enable enable as wake-up if equal to non-zero |
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* @return This function returns 0 on success. |
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*/ |
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static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct mxs_gpio_port *port = gc->private; |
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if (enable) |
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enable_irq_wake(port->irq); |
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else |
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disable_irq_wake(port->irq); |
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return 0; |
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} |
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static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base) |
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{ |
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struct irq_chip_generic *gc; |
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struct irq_chip_type *ct; |
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int rv; |
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gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base, |
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port->base, handle_level_irq); |
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if (!gc) |
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return -ENOMEM; |
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gc->private = port; |
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ct = &gc->chip_types[0]; |
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ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; |
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ct->chip.irq_ack = irq_gc_ack_set_bit; |
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ct->chip.irq_mask = irq_gc_mask_disable_reg; |
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg; |
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ct->chip.irq_set_type = mxs_gpio_set_irq_type; |
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ct->chip.irq_set_wake = mxs_gpio_set_wake_irq; |
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ct->chip.flags = IRQCHIP_SET_TYPE_MASKED; |
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ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR; |
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ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET; |
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ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR; |
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ct = &gc->chip_types[1]; |
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ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
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ct->chip.irq_ack = irq_gc_ack_set_bit; |
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ct->chip.irq_mask = irq_gc_mask_disable_reg; |
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg; |
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ct->chip.irq_set_type = mxs_gpio_set_irq_type; |
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ct->chip.irq_set_wake = mxs_gpio_set_wake_irq; |
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ct->chip.flags = IRQCHIP_SET_TYPE_MASKED; |
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ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR; |
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ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET; |
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ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR; |
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ct->handler = handle_level_irq; |
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rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), |
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IRQ_GC_INIT_NESTED_LOCK, |
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IRQ_NOREQUEST, 0); |
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return rv; |
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} |
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static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) |
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{ |
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struct mxs_gpio_port *port = gpiochip_get_data(gc); |
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return irq_find_mapping(port->domain, offset); |
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} |
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static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) |
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{ |
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struct mxs_gpio_port *port = gpiochip_get_data(gc); |
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u32 mask = 1 << offset; |
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u32 dir; |
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dir = readl(port->base + PINCTRL_DOE(port)); |
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if (dir & mask) |
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return GPIO_LINE_DIRECTION_OUT; |
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return GPIO_LINE_DIRECTION_IN; |
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} |
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static const struct of_device_id mxs_gpio_dt_ids[] = { |
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{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, }, |
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{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, }, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids); |
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static int mxs_gpio_probe(struct platform_device *pdev) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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struct device_node *parent; |
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static void __iomem *base; |
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struct mxs_gpio_port *port; |
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int irq_base; |
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int err; |
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port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); |
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if (!port) |
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return -ENOMEM; |
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port->id = of_alias_get_id(np, "gpio"); |
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if (port->id < 0) |
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return port->id; |
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port->devid = (enum mxs_gpio_id)of_device_get_match_data(&pdev->dev); |
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port->dev = &pdev->dev; |
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port->irq = platform_get_irq(pdev, 0); |
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if (port->irq < 0) |
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return port->irq; |
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/* |
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* map memory region only once, as all the gpio ports |
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* share the same one |
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*/ |
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if (!base) { |
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parent = of_get_parent(np); |
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base = of_iomap(parent, 0); |
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of_node_put(parent); |
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if (!base) |
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return -EADDRNOTAVAIL; |
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} |
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port->base = base; |
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/* initially disable the interrupts */ |
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writel(0, port->base + PINCTRL_PIN2IRQ(port)); |
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writel(0, port->base + PINCTRL_IRQEN(port)); |
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/* clear address has to be used to clear IRQSTAT bits */ |
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writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR); |
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irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); |
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if (irq_base < 0) { |
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err = irq_base; |
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goto out_iounmap; |
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} |
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port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, |
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&irq_domain_simple_ops, NULL); |
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if (!port->domain) { |
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err = -ENODEV; |
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goto out_iounmap; |
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} |
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/* gpio-mxs can be a generic irq chip */ |
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err = mxs_gpio_init_gc(port, irq_base); |
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if (err < 0) |
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goto out_irqdomain_remove; |
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/* setup one handler for each entry */ |
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irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler, |
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port); |
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err = bgpio_init(&port->gc, &pdev->dev, 4, |
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port->base + PINCTRL_DIN(port), |
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port->base + PINCTRL_DOUT(port) + MXS_SET, |
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port->base + PINCTRL_DOUT(port) + MXS_CLR, |
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port->base + PINCTRL_DOE(port), NULL, 0); |
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if (err) |
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goto out_irqdomain_remove; |
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port->gc.to_irq = mxs_gpio_to_irq; |
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port->gc.get_direction = mxs_gpio_get_direction; |
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port->gc.base = port->id * 32; |
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err = gpiochip_add_data(&port->gc, port); |
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if (err) |
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goto out_irqdomain_remove; |
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return 0; |
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out_irqdomain_remove: |
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irq_domain_remove(port->domain); |
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out_iounmap: |
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iounmap(port->base); |
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return err; |
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} |
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static struct platform_driver mxs_gpio_driver = { |
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.driver = { |
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.name = "gpio-mxs", |
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.of_match_table = mxs_gpio_dt_ids, |
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.suppress_bind_attrs = true, |
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}, |
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.probe = mxs_gpio_probe, |
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}; |
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static int __init mxs_gpio_init(void) |
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{ |
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return platform_driver_register(&mxs_gpio_driver); |
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} |
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postcore_initcall(mxs_gpio_init); |
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MODULE_AUTHOR("Freescale Semiconductor, " |
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"Daniel Mack <danielncaiaq.de>, " |
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"Juergen Beisert <[email protected]>"); |
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MODULE_DESCRIPTION("Freescale MXS GPIO"); |
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MODULE_LICENSE("GPL");
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