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644 lines
16 KiB
644 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2013 Imagination Technologies |
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* Author: Paul Burton <[email protected]> |
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*/ |
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|
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#include <linux/cpu.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/sched/task_stack.h> |
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#include <linux/sched/hotplug.h> |
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#include <linux/slab.h> |
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#include <linux/smp.h> |
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#include <linux/types.h> |
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#include <linux/irq.h> |
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#include <asm/bcache.h> |
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#include <asm/mips-cps.h> |
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#include <asm/mips_mt.h> |
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#include <asm/mipsregs.h> |
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#include <asm/pm-cps.h> |
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#include <asm/r4kcache.h> |
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#include <asm/smp-cps.h> |
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#include <asm/time.h> |
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#include <asm/uasm.h> |
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static bool threads_disabled; |
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static DECLARE_BITMAP(core_power, NR_CPUS); |
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struct core_boot_config *mips_cps_core_bootcfg; |
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static int __init setup_nothreads(char *s) |
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{ |
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threads_disabled = true; |
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return 0; |
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} |
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early_param("nothreads", setup_nothreads); |
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static unsigned core_vpe_count(unsigned int cluster, unsigned core) |
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{ |
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if (threads_disabled) |
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return 1; |
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return mips_cps_numvps(cluster, core); |
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} |
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static void __init cps_smp_setup(void) |
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{ |
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unsigned int nclusters, ncores, nvpes, core_vpes; |
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unsigned long core_entry; |
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int cl, c, v; |
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|
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/* Detect & record VPE topology */ |
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nvpes = 0; |
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nclusters = mips_cps_numclusters(); |
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pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE"); |
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for (cl = 0; cl < nclusters; cl++) { |
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if (cl > 0) |
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pr_cont(","); |
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pr_cont("{"); |
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ncores = mips_cps_numcores(cl); |
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for (c = 0; c < ncores; c++) { |
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core_vpes = core_vpe_count(cl, c); |
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if (c > 0) |
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pr_cont(","); |
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pr_cont("%u", core_vpes); |
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/* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */ |
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if (!cl && !c) |
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smp_num_siblings = core_vpes; |
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for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { |
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cpu_set_cluster(&cpu_data[nvpes + v], cl); |
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cpu_set_core(&cpu_data[nvpes + v], c); |
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cpu_set_vpe_id(&cpu_data[nvpes + v], v); |
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} |
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nvpes += core_vpes; |
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} |
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pr_cont("}"); |
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} |
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pr_cont(" total %u\n", nvpes); |
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/* Indicate present CPUs (CPU being synonymous with VPE) */ |
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for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { |
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set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0); |
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set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0); |
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__cpu_number_map[v] = v; |
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__cpu_logical_map[v] = v; |
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} |
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/* Set a coherent default CCA (CWB) */ |
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change_c0_config(CONF_CM_CMASK, 0x5); |
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/* Core 0 is powered up (we're running on it) */ |
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bitmap_set(core_power, 0, 1); |
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/* Initialise core 0 */ |
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mips_cps_core_init(); |
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/* Make core 0 coherent with everything */ |
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write_gcr_cl_coherence(0xff); |
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if (mips_cm_revision() >= CM_REV_CM3) { |
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core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); |
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write_gcr_bev_base(core_entry); |
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} |
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#ifdef CONFIG_MIPS_MT_FPAFF |
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/* If we have an FPU, enroll ourselves in the FPU-full mask */ |
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if (cpu_has_fpu) |
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cpumask_set_cpu(0, &mt_fpu_cpumask); |
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#endif /* CONFIG_MIPS_MT_FPAFF */ |
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} |
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static void __init cps_prepare_cpus(unsigned int max_cpus) |
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{ |
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unsigned ncores, core_vpes, c, cca; |
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bool cca_unsuitable, cores_limited; |
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u32 *entry_code; |
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mips_mt_set_cpuoptions(); |
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/* Detect whether the CCA is unsuited to multi-core SMP */ |
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cca = read_c0_config() & CONF_CM_CMASK; |
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switch (cca) { |
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case 0x4: /* CWBE */ |
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case 0x5: /* CWB */ |
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/* The CCA is coherent, multi-core is fine */ |
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cca_unsuitable = false; |
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break; |
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default: |
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/* CCA is not coherent, multi-core is not usable */ |
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cca_unsuitable = true; |
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} |
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/* Warn the user if the CCA prevents multi-core */ |
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cores_limited = false; |
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if (cca_unsuitable || cpu_has_dc_aliases) { |
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for_each_present_cpu(c) { |
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if (cpus_are_siblings(smp_processor_id(), c)) |
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continue; |
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set_cpu_present(c, false); |
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cores_limited = true; |
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} |
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} |
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if (cores_limited) |
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pr_warn("Using only one core due to %s%s%s\n", |
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cca_unsuitable ? "unsuitable CCA" : "", |
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(cca_unsuitable && cpu_has_dc_aliases) ? " & " : "", |
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cpu_has_dc_aliases ? "dcache aliasing" : ""); |
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/* |
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* Patch the start of mips_cps_core_entry to provide: |
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* |
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* s0 = kseg0 CCA |
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*/ |
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entry_code = (u32 *)&mips_cps_core_entry; |
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uasm_i_addiu(&entry_code, 16, 0, cca); |
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blast_dcache_range((unsigned long)&mips_cps_core_entry, |
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(unsigned long)entry_code); |
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bc_wback_inv((unsigned long)&mips_cps_core_entry, |
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(void *)entry_code - (void *)&mips_cps_core_entry); |
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__sync(); |
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/* Allocate core boot configuration structs */ |
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ncores = mips_cps_numcores(0); |
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mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), |
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GFP_KERNEL); |
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if (!mips_cps_core_bootcfg) { |
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pr_err("Failed to allocate boot config for %u cores\n", ncores); |
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goto err_out; |
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} |
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/* Allocate VPE boot configuration structs */ |
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for (c = 0; c < ncores; c++) { |
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core_vpes = core_vpe_count(0, c); |
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mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes, |
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sizeof(*mips_cps_core_bootcfg[c].vpe_config), |
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GFP_KERNEL); |
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if (!mips_cps_core_bootcfg[c].vpe_config) { |
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pr_err("Failed to allocate %u VPE boot configs\n", |
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core_vpes); |
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goto err_out; |
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} |
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} |
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/* Mark this CPU as booted */ |
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atomic_set(&mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)].vpe_mask, |
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1 << cpu_vpe_id(¤t_cpu_data)); |
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return; |
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err_out: |
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/* Clean up allocations */ |
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if (mips_cps_core_bootcfg) { |
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for (c = 0; c < ncores; c++) |
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kfree(mips_cps_core_bootcfg[c].vpe_config); |
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kfree(mips_cps_core_bootcfg); |
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mips_cps_core_bootcfg = NULL; |
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} |
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/* Effectively disable SMP by declaring CPUs not present */ |
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for_each_possible_cpu(c) { |
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if (c == 0) |
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continue; |
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set_cpu_present(c, false); |
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} |
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} |
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static void boot_core(unsigned int core, unsigned int vpe_id) |
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{ |
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u32 stat, seq_state; |
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unsigned timeout; |
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/* Select the appropriate core */ |
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mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); |
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/* Set its reset vector */ |
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write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); |
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/* Ensure its coherency is disabled */ |
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write_gcr_co_coherence(0); |
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/* Start it with the legacy memory map and exception base */ |
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write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB); |
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/* Ensure the core can access the GCRs */ |
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set_gcr_access(1 << core); |
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if (mips_cpc_present()) { |
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/* Reset the core */ |
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mips_cpc_lock_other(core); |
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if (mips_cm_revision() >= CM_REV_CM3) { |
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/* Run only the requested VP following the reset */ |
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write_cpc_co_vp_stop(0xf); |
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write_cpc_co_vp_run(1 << vpe_id); |
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/* |
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* Ensure that the VP_RUN register is written before the |
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* core leaves reset. |
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*/ |
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wmb(); |
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} |
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write_cpc_co_cmd(CPC_Cx_CMD_RESET); |
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timeout = 100; |
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while (true) { |
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stat = read_cpc_co_stat_conf(); |
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seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; |
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seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); |
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/* U6 == coherent execution, ie. the core is up */ |
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if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6) |
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break; |
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/* Delay a little while before we start warning */ |
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if (timeout) { |
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timeout--; |
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mdelay(10); |
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continue; |
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} |
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pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n", |
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core, stat); |
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mdelay(1000); |
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} |
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mips_cpc_unlock_other(); |
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} else { |
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/* Take the core out of reset */ |
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write_gcr_co_reset_release(0); |
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} |
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mips_cm_unlock_other(); |
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/* The core is now powered up */ |
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bitmap_set(core_power, core, 1); |
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} |
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static void remote_vpe_boot(void *dummy) |
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{ |
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unsigned core = cpu_core(¤t_cpu_data); |
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struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; |
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mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data)); |
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} |
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static int cps_boot_secondary(int cpu, struct task_struct *idle) |
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{ |
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unsigned core = cpu_core(&cpu_data[cpu]); |
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unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); |
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struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; |
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struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; |
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unsigned long core_entry; |
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unsigned int remote; |
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int err; |
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/* We don't yet support booting CPUs in other clusters */ |
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if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data)) |
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return -ENOSYS; |
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vpe_cfg->pc = (unsigned long)&smp_bootstrap; |
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vpe_cfg->sp = __KSTK_TOS(idle); |
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vpe_cfg->gp = (unsigned long)task_thread_info(idle); |
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atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask); |
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preempt_disable(); |
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if (!test_bit(core, core_power)) { |
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/* Boot a VPE on a powered down core */ |
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boot_core(core, vpe_id); |
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goto out; |
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} |
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if (cpu_has_vp) { |
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mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); |
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core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); |
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write_gcr_co_reset_base(core_entry); |
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mips_cm_unlock_other(); |
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} |
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if (!cpus_are_siblings(cpu, smp_processor_id())) { |
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/* Boot a VPE on another powered up core */ |
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for (remote = 0; remote < NR_CPUS; remote++) { |
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if (!cpus_are_siblings(cpu, remote)) |
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continue; |
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if (cpu_online(remote)) |
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break; |
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} |
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if (remote >= NR_CPUS) { |
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pr_crit("No online CPU in core %u to start CPU%d\n", |
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core, cpu); |
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goto out; |
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} |
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err = smp_call_function_single(remote, remote_vpe_boot, |
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NULL, 1); |
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if (err) |
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panic("Failed to call remote CPU\n"); |
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goto out; |
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} |
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BUG_ON(!cpu_has_mipsmt && !cpu_has_vp); |
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/* Boot a VPE on this core */ |
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mips_cps_boot_vpes(core_cfg, vpe_id); |
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out: |
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preempt_enable(); |
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return 0; |
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} |
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static void cps_init_secondary(void) |
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{ |
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/* Disable MT - we only want to run 1 TC per VPE */ |
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if (cpu_has_mipsmt) |
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dmt(); |
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if (mips_cm_revision() >= CM_REV_CM3) { |
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unsigned int ident = read_gic_vl_ident(); |
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/* |
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* Ensure that our calculation of the VP ID matches up with |
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* what the GIC reports, otherwise we'll have configured |
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* interrupts incorrectly. |
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*/ |
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BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); |
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} |
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if (cpu_has_veic) |
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clear_c0_status(ST0_IM); |
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else |
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change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | |
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STATUSF_IP4 | STATUSF_IP5 | |
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STATUSF_IP6 | STATUSF_IP7); |
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} |
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static void cps_smp_finish(void) |
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{ |
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write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); |
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#ifdef CONFIG_MIPS_MT_FPAFF |
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/* If we have an FPU, enroll ourselves in the FPU-full mask */ |
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if (cpu_has_fpu) |
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cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask); |
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#endif /* CONFIG_MIPS_MT_FPAFF */ |
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local_irq_enable(); |
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} |
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#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC) |
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enum cpu_death { |
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CPU_DEATH_HALT, |
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CPU_DEATH_POWER, |
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}; |
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static void cps_shutdown_this_cpu(enum cpu_death death) |
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{ |
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unsigned int cpu, core, vpe_id; |
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cpu = smp_processor_id(); |
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core = cpu_core(&cpu_data[cpu]); |
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if (death == CPU_DEATH_HALT) { |
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vpe_id = cpu_vpe_id(&cpu_data[cpu]); |
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pr_debug("Halting core %d VP%d\n", core, vpe_id); |
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if (cpu_has_mipsmt) { |
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/* Halt this TC */ |
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write_c0_tchalt(TCHALT_H); |
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instruction_hazard(); |
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} else if (cpu_has_vp) { |
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write_cpc_cl_vp_stop(1 << vpe_id); |
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/* Ensure that the VP_STOP register is written */ |
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wmb(); |
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} |
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} else { |
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pr_debug("Gating power to core %d\n", core); |
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/* Power down the core */ |
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cps_pm_enter_state(CPS_PM_POWER_GATED); |
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} |
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} |
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#ifdef CONFIG_KEXEC |
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static void cps_kexec_nonboot_cpu(void) |
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{ |
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if (cpu_has_mipsmt || cpu_has_vp) |
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cps_shutdown_this_cpu(CPU_DEATH_HALT); |
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else |
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cps_shutdown_this_cpu(CPU_DEATH_POWER); |
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} |
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#endif /* CONFIG_KEXEC */ |
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#endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC */ |
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#ifdef CONFIG_HOTPLUG_CPU |
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static int cps_cpu_disable(void) |
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{ |
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unsigned cpu = smp_processor_id(); |
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struct core_boot_config *core_cfg; |
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if (!cps_pm_support_state(CPS_PM_POWER_GATED)) |
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return -EINVAL; |
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core_cfg = &mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)]; |
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atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask); |
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smp_mb__after_atomic(); |
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set_cpu_online(cpu, false); |
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calculate_cpu_foreign_map(); |
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irq_migrate_all_off_this_cpu(); |
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return 0; |
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} |
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static unsigned cpu_death_sibling; |
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static enum cpu_death cpu_death; |
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void play_dead(void) |
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{ |
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unsigned int cpu; |
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local_irq_disable(); |
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idle_task_exit(); |
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cpu = smp_processor_id(); |
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cpu_death = CPU_DEATH_POWER; |
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pr_debug("CPU%d going offline\n", cpu); |
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if (cpu_has_mipsmt || cpu_has_vp) { |
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/* Look for another online VPE within the core */ |
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for_each_online_cpu(cpu_death_sibling) { |
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if (!cpus_are_siblings(cpu, cpu_death_sibling)) |
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continue; |
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/* |
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* There is an online VPE within the core. Just halt |
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* this TC and leave the core alone. |
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*/ |
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cpu_death = CPU_DEATH_HALT; |
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break; |
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} |
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} |
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/* This CPU has chosen its way out */ |
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(void)cpu_report_death(); |
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cps_shutdown_this_cpu(cpu_death); |
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/* This should never be reached */ |
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panic("Failed to offline CPU %u", cpu); |
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} |
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static void wait_for_sibling_halt(void *ptr_cpu) |
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{ |
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unsigned cpu = (unsigned long)ptr_cpu; |
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unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); |
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unsigned halted; |
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unsigned long flags; |
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do { |
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local_irq_save(flags); |
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settc(vpe_id); |
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halted = read_tc_c0_tchalt(); |
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local_irq_restore(flags); |
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} while (!(halted & TCHALT_H)); |
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} |
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static void cps_cpu_die(unsigned int cpu) |
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{ |
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unsigned core = cpu_core(&cpu_data[cpu]); |
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unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]); |
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ktime_t fail_time; |
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unsigned stat; |
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int err; |
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/* Wait for the cpu to choose its way out */ |
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if (!cpu_wait_death(cpu, 5)) { |
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pr_err("CPU%u: didn't offline\n", cpu); |
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return; |
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} |
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|
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/* |
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* Now wait for the CPU to actually offline. Without doing this that |
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* offlining may race with one or more of: |
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* |
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* - Onlining the CPU again. |
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* - Powering down the core if another VPE within it is offlined. |
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* - A sibling VPE entering a non-coherent state. |
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* |
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* In the non-MT halt case (ie. infinite loop) the CPU is doing nothing |
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* with which we could race, so do nothing. |
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*/ |
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if (cpu_death == CPU_DEATH_POWER) { |
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/* |
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* Wait for the core to enter a powered down or clock gated |
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* state, the latter happening when a JTAG probe is connected |
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* in which case the CPC will refuse to power down the core. |
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*/ |
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fail_time = ktime_add_ms(ktime_get(), 2000); |
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do { |
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mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); |
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mips_cpc_lock_other(core); |
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stat = read_cpc_co_stat_conf(); |
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stat &= CPC_Cx_STAT_CONF_SEQSTATE; |
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stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); |
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mips_cpc_unlock_other(); |
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mips_cm_unlock_other(); |
|
|
|
if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 || |
|
stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 || |
|
stat == CPC_Cx_STAT_CONF_SEQSTATE_U2) |
|
break; |
|
|
|
/* |
|
* The core ought to have powered down, but didn't & |
|
* now we don't really know what state it's in. It's |
|
* likely that its _pwr_up pin has been wired to logic |
|
* 1 & it powered back up as soon as we powered it |
|
* down... |
|
* |
|
* The best we can do is warn the user & continue in |
|
* the hope that the core is doing nothing harmful & |
|
* might behave properly if we online it later. |
|
*/ |
|
if (WARN(ktime_after(ktime_get(), fail_time), |
|
"CPU%u hasn't powered down, seq. state %u\n", |
|
cpu, stat)) |
|
break; |
|
} while (1); |
|
|
|
/* Indicate the core is powered off */ |
|
bitmap_clear(core_power, core, 1); |
|
} else if (cpu_has_mipsmt) { |
|
/* |
|
* Have a CPU with access to the offlined CPUs registers wait |
|
* for its TC to halt. |
|
*/ |
|
err = smp_call_function_single(cpu_death_sibling, |
|
wait_for_sibling_halt, |
|
(void *)(unsigned long)cpu, 1); |
|
if (err) |
|
panic("Failed to call remote sibling CPU\n"); |
|
} else if (cpu_has_vp) { |
|
do { |
|
mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); |
|
stat = read_cpc_co_vp_running(); |
|
mips_cm_unlock_other(); |
|
} while (stat & (1 << vpe_id)); |
|
} |
|
} |
|
|
|
#endif /* CONFIG_HOTPLUG_CPU */ |
|
|
|
static const struct plat_smp_ops cps_smp_ops = { |
|
.smp_setup = cps_smp_setup, |
|
.prepare_cpus = cps_prepare_cpus, |
|
.boot_secondary = cps_boot_secondary, |
|
.init_secondary = cps_init_secondary, |
|
.smp_finish = cps_smp_finish, |
|
.send_ipi_single = mips_smp_send_ipi_single, |
|
.send_ipi_mask = mips_smp_send_ipi_mask, |
|
#ifdef CONFIG_HOTPLUG_CPU |
|
.cpu_disable = cps_cpu_disable, |
|
.cpu_die = cps_cpu_die, |
|
#endif |
|
#ifdef CONFIG_KEXEC |
|
.kexec_nonboot_cpu = cps_kexec_nonboot_cpu, |
|
#endif |
|
}; |
|
|
|
bool mips_cps_smp_in_use(void) |
|
{ |
|
extern const struct plat_smp_ops *mp_ops; |
|
return mp_ops == &cps_smp_ops; |
|
} |
|
|
|
int register_cps_smp_ops(void) |
|
{ |
|
if (!mips_cm_present()) { |
|
pr_warn("MIPS CPS SMP unable to proceed without a CM\n"); |
|
return -ENODEV; |
|
} |
|
|
|
/* check we have a GIC - we need one for IPIs */ |
|
if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) { |
|
pr_warn("MIPS CPS SMP unable to proceed without a GIC\n"); |
|
return -ENODEV; |
|
} |
|
|
|
register_smp_ops(&cps_smp_ops); |
|
return 0; |
|
}
|
|
|