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110 lines
2.8 KiB
110 lines
2.8 KiB
/* |
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* Support for MicroBlaze PVR (processor version register) |
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* |
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* Copyright (C) 2007-2009 Michal Simek <[email protected]> |
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* Copyright (C) 2007-2009 PetaLogix |
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* Copyright (C) 2007 John Williams <[email protected]> |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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*/ |
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#include <linux/init.h> |
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#include <linux/string.h> |
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#include <asm/pvr.h> |
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#include <asm/cpuinfo.h> |
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/* |
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* Helper macro to map between fields in our struct cpuinfo, and |
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* the PVR macros in pvr.h. |
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*/ |
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#define CI(c, p) { ci->c = PVR_##p(pvr); } |
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#define err_printk(x) \ |
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pr_err("ERROR: Microblaze " x "-different for PVR and DTS\n"); |
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void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu) |
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{ |
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struct pvr_s pvr; |
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u32 temp; /* for saving temp value */ |
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get_pvr(&pvr); |
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CI(ver_code, VERSION); |
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if (!ci->ver_code) { |
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pr_err("ERROR: MB has broken PVR regs -> use DTS setting\n"); |
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return; |
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} |
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temp = PVR_USE_BARREL(pvr) | PVR_USE_MSR_INSTR(pvr) | |
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PVR_USE_PCMP_INSTR(pvr) | PVR_USE_DIV(pvr); |
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if (ci->use_instr != temp) |
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err_printk("BARREL, MSR, PCMP or DIV"); |
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ci->use_instr = temp; |
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temp = PVR_USE_HW_MUL(pvr) | PVR_USE_MUL64(pvr); |
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if (ci->use_mult != temp) |
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err_printk("HW_MUL"); |
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ci->use_mult = temp; |
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temp = PVR_USE_FPU(pvr) | PVR_USE_FPU2(pvr); |
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if (ci->use_fpu != temp) |
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err_printk("HW_FPU"); |
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ci->use_fpu = temp; |
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ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) | |
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PVR_UNALIGNED_EXCEPTION(pvr) | |
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PVR_ILL_OPCODE_EXCEPTION(pvr) | |
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PVR_IOPB_BUS_EXCEPTION(pvr) | |
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PVR_DOPB_BUS_EXCEPTION(pvr) | |
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PVR_DIV_ZERO_EXCEPTION(pvr) | |
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PVR_FPU_EXCEPTION(pvr) | |
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PVR_FSL_EXCEPTION(pvr); |
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CI(pvr_user1, USER1); |
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CI(pvr_user2, USER2); |
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CI(mmu, USE_MMU); |
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CI(mmu_privins, MMU_PRIVINS); |
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CI(endian, ENDIAN); |
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CI(use_icache, USE_ICACHE); |
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CI(icache_tagbits, ICACHE_ADDR_TAG_BITS); |
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CI(icache_write, ICACHE_ALLOW_WR); |
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ci->icache_line_length = PVR_ICACHE_LINE_LEN(pvr) << 2; |
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CI(icache_size, ICACHE_BYTE_SIZE); |
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CI(icache_base, ICACHE_BASEADDR); |
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CI(icache_high, ICACHE_HIGHADDR); |
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CI(use_dcache, USE_DCACHE); |
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CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS); |
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CI(dcache_write, DCACHE_ALLOW_WR); |
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ci->dcache_line_length = PVR_DCACHE_LINE_LEN(pvr) << 2; |
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CI(dcache_size, DCACHE_BYTE_SIZE); |
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CI(dcache_base, DCACHE_BASEADDR); |
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CI(dcache_high, DCACHE_HIGHADDR); |
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temp = PVR_DCACHE_USE_WRITEBACK(pvr); |
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if (ci->dcache_wb != temp) |
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err_printk("DCACHE WB"); |
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ci->dcache_wb = temp; |
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CI(use_dopb, D_OPB); |
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CI(use_iopb, I_OPB); |
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CI(use_dlmb, D_LMB); |
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CI(use_ilmb, I_LMB); |
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CI(num_fsl, FSL_LINKS); |
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CI(irq_edge, INTERRUPT_IS_EDGE); |
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CI(irq_positive, EDGE_IS_POSITIVE); |
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CI(area_optimised, AREA_OPTIMISED); |
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CI(hw_debug, DEBUG_ENABLED); |
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CI(num_pc_brk, NUMBER_OF_PC_BRK); |
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CI(num_rd_brk, NUMBER_OF_RD_ADDR_BRK); |
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CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK); |
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CI(fpga_family_code, TARGET_FAMILY); |
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}
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