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172 lines
4.4 KiB
172 lines
4.4 KiB
/* |
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* Copyright (c) 2016, Mellanox Technologies. All rights reserved. |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the |
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* OpenIB.org BSD license below: |
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* |
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* Redistribution and use in source and binary forms, with or |
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* without modification, are permitted provided that the following |
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* conditions are met: |
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* |
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* - Redistributions of source code must retain the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer. |
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* |
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* - Redistributions in binary form must reproduce the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer in the documentation and/or other materials |
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* provided with the distribution. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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* SOFTWARE. |
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*/ |
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#ifndef SOC_NPS_COMMON_H |
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#define SOC_NPS_COMMON_H |
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#ifdef CONFIG_SMP |
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#define NPS_IPI_IRQ 5 |
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#endif |
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#define NPS_HOST_REG_BASE 0xF6000000 |
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#define NPS_MSU_BLKID 0x018 |
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#define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E |
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#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60 |
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#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422 |
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#ifndef AUX_IENABLE |
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#define AUX_IENABLE 0x40c |
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#endif |
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#define CTOP_AUX_IACK (0xFFFFF800 + 0x088) |
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#ifndef __ASSEMBLY__ |
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/* In order to increase compilation test coverage */ |
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#ifdef CONFIG_ARC |
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static inline void nps_ack_gic(void) |
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{ |
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__asm__ __volatile__ ( |
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" .word %0\n" |
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: |
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: "i"(CTOP_INST_RSPI_GIC_0_R12) |
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: "memory"); |
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} |
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#else |
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static inline void nps_ack_gic(void) { } |
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#define write_aux_reg(r, v) |
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#define read_aux_reg(r) 0 |
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#endif |
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/* CPU global ID */ |
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struct global_id { |
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union { |
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struct { |
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#ifdef CONFIG_EZNPS_MTM_EXT |
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u32 __reserved:20, cluster:4, core:4, thread:4; |
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#else |
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u32 __reserved:24, cluster:4, core:4; |
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#endif |
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}; |
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u32 value; |
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}; |
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}; |
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/* |
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* Convert logical to physical CPU IDs |
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* |
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* The conversion swap bits 1 and 2 of cluster id (out of 4 bits) |
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* Now quad of logical clusters id's are adjacent physically, |
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* and not like the id's physically came with each cluster. |
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* Below table is 4x4 mesh of core clusters as it layout on chip. |
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* Cluster ids are in format: logical (physical) |
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* |
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* ----------------- ------------------ |
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* 3 | 5 (3) 7 (7) | | 13 (11) 15 (15)| |
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* |
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* 2 | 4 (2) 6 (6) | | 12 (10) 14 (14)| |
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* ----------------- ------------------ |
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* 1 | 1 (1) 3 (5) | | 9 (9) 11 (13)| |
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* |
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* 0 | 0 (0) 2 (4) | | 8 (8) 10 (12)| |
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* ----------------- ------------------ |
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* 0 1 2 3 |
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*/ |
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static inline int nps_cluster_logic_to_phys(int cluster) |
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{ |
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#ifdef __arc__ |
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__asm__ __volatile__( |
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" mov r3,%0\n" |
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" .short %1\n" |
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" .word %2\n" |
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" mov %0,r3\n" |
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: "+r"(cluster) |
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: "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST), |
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"i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM) |
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: "r3"); |
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#endif |
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return cluster; |
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} |
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#define NPS_CPU_TO_CLUSTER_NUM(cpu) \ |
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({ struct global_id gid; gid.value = cpu; \ |
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nps_cluster_logic_to_phys(gid.cluster); }) |
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struct nps_host_reg_address { |
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union { |
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struct { |
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u32 base:8, cl_x:4, cl_y:4, |
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blkid:6, reg:8, __reserved:2; |
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}; |
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u32 value; |
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}; |
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}; |
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struct nps_host_reg_address_non_cl { |
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union { |
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struct { |
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u32 base:7, blkid:11, reg:12, __reserved:2; |
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}; |
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u32 value; |
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}; |
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}; |
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static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg) |
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{ |
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struct nps_host_reg_address_non_cl reg_address; |
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reg_address.value = NPS_HOST_REG_BASE; |
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reg_address.blkid = blkid; |
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reg_address.reg = reg; |
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return (void *)reg_address.value; |
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} |
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static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg) |
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{ |
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struct nps_host_reg_address reg_address; |
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u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu); |
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reg_address.value = NPS_HOST_REG_BASE; |
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reg_address.cl_x = (cl >> 2) & 0x3; |
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reg_address.cl_y = cl & 0x3; |
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reg_address.blkid = blkid; |
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reg_address.reg = reg; |
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return (void *)reg_address.value; |
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} |
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#endif /* __ASSEMBLY__ */ |
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#endif /* SOC_NPS_COMMON_H */
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