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595 lines
16 KiB
595 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Device State Control Registers driver |
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* |
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* Copyright (C) 2011 Texas Instruments Incorporated |
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* Author: Mark Salter <[email protected]> |
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*/ |
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|
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/* |
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* The Device State Control Registers (DSCR) provide SoC level control over |
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* a number of peripherals. Details vary considerably among the various SoC |
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* parts. In general, the DSCR block will provide one or more configuration |
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* registers often protected by a lock register. One or more key values must |
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* be written to a lock register in order to unlock the configuration register. |
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* The configuration register may be used to enable (and disable in some |
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* cases) SoC pin drivers, peripheral clock sources (internal or pin), etc. |
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* In some cases, a configuration register is write once or the individual |
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* bits are write once. That is, you may be able to enable a device, but |
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* will not be able to disable it. |
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* |
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* In addition to device configuration, the DSCR block may provide registers |
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* which are used to reset SoC peripherals, provide device ID information, |
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* provide MAC addresses, and other miscellaneous functions. |
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*/ |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_platform.h> |
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#include <linux/module.h> |
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#include <linux/io.h> |
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#include <linux/delay.h> |
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#include <asm/soc.h> |
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#include <asm/dscr.h> |
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#define MAX_DEVSTATE_IDS 32 |
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#define MAX_DEVCTL_REGS 8 |
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#define MAX_DEVSTAT_REGS 8 |
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#define MAX_LOCKED_REGS 4 |
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#define MAX_SOC_EMACS 2 |
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struct rmii_reset_reg { |
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u32 reg; |
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u32 mask; |
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}; |
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/* |
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* Some registerd may be locked. In order to write to these |
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* registers, the key value must first be written to the lockreg. |
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*/ |
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struct locked_reg { |
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u32 reg; /* offset from base */ |
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u32 lockreg; /* offset from base */ |
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u32 key; /* unlock key */ |
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}; |
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/* |
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* This describes a contiguous area of like control bits used to enable/disable |
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* SoC devices. Each controllable device is given an ID which is used by the |
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* individual device drivers to control the device state. These IDs start at |
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* zero and are assigned sequentially to the control bitfield ranges described |
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* by this structure. |
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*/ |
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struct devstate_ctl_reg { |
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u32 reg; /* register holding the control bits */ |
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u8 start_id; /* start id of this range */ |
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u8 num_ids; /* number of devices in this range */ |
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u8 enable_only; /* bits are write-once to enable only */ |
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u8 enable; /* value used to enable device */ |
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u8 disable; /* value used to disable device */ |
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u8 shift; /* starting (rightmost) bit in range */ |
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u8 nbits; /* number of bits per device */ |
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}; |
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/* |
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* This describes a region of status bits indicating the state of |
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* various devices. This is used internally to wait for status |
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* change completion when enabling/disabling a device. Status is |
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* optional and not all device controls will have a corresponding |
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* status. |
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*/ |
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struct devstate_stat_reg { |
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u32 reg; /* register holding the status bits */ |
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u8 start_id; /* start id of this range */ |
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u8 num_ids; /* number of devices in this range */ |
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u8 enable; /* value indicating enabled state */ |
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u8 disable; /* value indicating disabled state */ |
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u8 shift; /* starting (rightmost) bit in range */ |
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u8 nbits; /* number of bits per device */ |
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}; |
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struct devstate_info { |
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struct devstate_ctl_reg *ctl; |
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struct devstate_stat_reg *stat; |
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}; |
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/* These are callbacks to SOC-specific code. */ |
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struct dscr_ops { |
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void (*init)(struct device_node *node); |
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}; |
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struct dscr_regs { |
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spinlock_t lock; |
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void __iomem *base; |
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u32 kick_reg[2]; |
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u32 kick_key[2]; |
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struct locked_reg locked[MAX_LOCKED_REGS]; |
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struct devstate_info devstate_info[MAX_DEVSTATE_IDS]; |
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struct rmii_reset_reg rmii_resets[MAX_SOC_EMACS]; |
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struct devstate_ctl_reg devctl[MAX_DEVCTL_REGS]; |
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struct devstate_stat_reg devstat[MAX_DEVSTAT_REGS]; |
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}; |
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static struct dscr_regs dscr; |
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static struct locked_reg *find_locked_reg(u32 reg) |
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{ |
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int i; |
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for (i = 0; i < MAX_LOCKED_REGS; i++) |
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if (dscr.locked[i].key && reg == dscr.locked[i].reg) |
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return &dscr.locked[i]; |
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return NULL; |
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} |
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/* |
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* Write to a register with one lock |
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*/ |
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static void dscr_write_locked1(u32 reg, u32 val, |
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u32 lock, u32 key) |
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{ |
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void __iomem *reg_addr = dscr.base + reg; |
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void __iomem *lock_addr = dscr.base + lock; |
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/* |
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* For some registers, the lock is relocked after a short number |
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* of cycles. We have to put the lock write and register write in |
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* the same fetch packet to meet this timing. The .align ensures |
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* the two stw instructions are in the same fetch packet. |
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*/ |
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asm volatile ("b .s2 0f\n" |
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"nop 5\n" |
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" .align 5\n" |
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"0:\n" |
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"stw .D1T2 %3,*%2\n" |
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"stw .D1T2 %1,*%0\n" |
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: |
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: "a"(reg_addr), "b"(val), "a"(lock_addr), "b"(key) |
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); |
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/* in case the hw doesn't reset the lock */ |
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soc_writel(0, lock_addr); |
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} |
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/* |
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* Write to a register protected by two lock registers |
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*/ |
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static void dscr_write_locked2(u32 reg, u32 val, |
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u32 lock0, u32 key0, |
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u32 lock1, u32 key1) |
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{ |
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soc_writel(key0, dscr.base + lock0); |
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soc_writel(key1, dscr.base + lock1); |
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soc_writel(val, dscr.base + reg); |
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soc_writel(0, dscr.base + lock0); |
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soc_writel(0, dscr.base + lock1); |
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} |
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static void dscr_write(u32 reg, u32 val) |
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{ |
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struct locked_reg *lock; |
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lock = find_locked_reg(reg); |
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if (lock) |
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dscr_write_locked1(reg, val, lock->lockreg, lock->key); |
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else if (dscr.kick_key[0]) |
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dscr_write_locked2(reg, val, dscr.kick_reg[0], dscr.kick_key[0], |
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dscr.kick_reg[1], dscr.kick_key[1]); |
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else |
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soc_writel(val, dscr.base + reg); |
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} |
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/* |
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* Drivers can use this interface to enable/disable SoC IP blocks. |
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*/ |
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void dscr_set_devstate(int id, enum dscr_devstate_t state) |
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{ |
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struct devstate_ctl_reg *ctl; |
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struct devstate_stat_reg *stat; |
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struct devstate_info *info; |
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u32 ctl_val, val; |
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int ctl_shift, ctl_mask; |
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unsigned long flags; |
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if (!dscr.base) |
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return; |
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if (id < 0 || id >= MAX_DEVSTATE_IDS) |
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return; |
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info = &dscr.devstate_info[id]; |
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ctl = info->ctl; |
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stat = info->stat; |
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if (ctl == NULL) |
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return; |
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ctl_shift = ctl->shift + ctl->nbits * (id - ctl->start_id); |
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ctl_mask = ((1 << ctl->nbits) - 1) << ctl_shift; |
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switch (state) { |
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case DSCR_DEVSTATE_ENABLED: |
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ctl_val = ctl->enable << ctl_shift; |
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break; |
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case DSCR_DEVSTATE_DISABLED: |
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if (ctl->enable_only) |
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return; |
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ctl_val = ctl->disable << ctl_shift; |
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break; |
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default: |
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return; |
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} |
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spin_lock_irqsave(&dscr.lock, flags); |
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val = soc_readl(dscr.base + ctl->reg); |
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val &= ~ctl_mask; |
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val |= ctl_val; |
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dscr_write(ctl->reg, val); |
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spin_unlock_irqrestore(&dscr.lock, flags); |
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if (!stat) |
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return; |
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ctl_shift = stat->shift + stat->nbits * (id - stat->start_id); |
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if (state == DSCR_DEVSTATE_ENABLED) |
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ctl_val = stat->enable; |
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else |
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ctl_val = stat->disable; |
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do { |
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val = soc_readl(dscr.base + stat->reg); |
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val >>= ctl_shift; |
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val &= ((1 << stat->nbits) - 1); |
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} while (val != ctl_val); |
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} |
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EXPORT_SYMBOL(dscr_set_devstate); |
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/* |
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* Drivers can use this to reset RMII module. |
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*/ |
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void dscr_rmii_reset(int id, int assert) |
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{ |
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struct rmii_reset_reg *r; |
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unsigned long flags; |
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u32 val; |
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if (id < 0 || id >= MAX_SOC_EMACS) |
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return; |
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r = &dscr.rmii_resets[id]; |
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if (r->mask == 0) |
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return; |
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spin_lock_irqsave(&dscr.lock, flags); |
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val = soc_readl(dscr.base + r->reg); |
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if (assert) |
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dscr_write(r->reg, val | r->mask); |
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else |
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dscr_write(r->reg, val & ~(r->mask)); |
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spin_unlock_irqrestore(&dscr.lock, flags); |
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} |
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EXPORT_SYMBOL(dscr_rmii_reset); |
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static void __init dscr_parse_devstat(struct device_node *node, |
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void __iomem *base) |
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{ |
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u32 val; |
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int err; |
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err = of_property_read_u32_array(node, "ti,dscr-devstat", &val, 1); |
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if (!err) |
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c6x_devstat = soc_readl(base + val); |
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printk(KERN_INFO "DEVSTAT: %08x\n", c6x_devstat); |
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} |
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static void __init dscr_parse_silicon_rev(struct device_node *node, |
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void __iomem *base) |
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{ |
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u32 vals[3]; |
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int err; |
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err = of_property_read_u32_array(node, "ti,dscr-silicon-rev", vals, 3); |
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if (!err) { |
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c6x_silicon_rev = soc_readl(base + vals[0]); |
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c6x_silicon_rev >>= vals[1]; |
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c6x_silicon_rev &= vals[2]; |
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} |
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} |
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/* |
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* Some SoCs will have a pair of fuse registers which hold |
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* an ethernet MAC address. The "ti,dscr-mac-fuse-regs" |
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* property is a mapping from fuse register bytes to MAC |
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* address bytes. The expected format is: |
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* |
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* ti,dscr-mac-fuse-regs = <reg0 b3 b2 b1 b0 |
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* reg1 b3 b2 b1 b0> |
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* |
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* reg0 and reg1 are the offsets of the two fuse registers. |
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* b3-b0 positionally represent bytes within the fuse register. |
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* b3 is the most significant byte and b0 is the least. |
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* Allowable values for b3-b0 are: |
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* |
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* 0 = fuse register byte not used in MAC address |
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* 1-6 = index+1 into c6x_fuse_mac[] |
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*/ |
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static void __init dscr_parse_mac_fuse(struct device_node *node, |
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void __iomem *base) |
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{ |
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u32 vals[10], fuse; |
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int f, i, j, err; |
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err = of_property_read_u32_array(node, "ti,dscr-mac-fuse-regs", |
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vals, 10); |
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if (err) |
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return; |
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for (f = 0; f < 2; f++) { |
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fuse = soc_readl(base + vals[f * 5]); |
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for (j = (f * 5) + 1, i = 24; i >= 0; i -= 8, j++) |
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if (vals[j] && vals[j] <= 6) |
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c6x_fuse_mac[vals[j] - 1] = fuse >> i; |
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} |
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} |
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static void __init dscr_parse_rmii_resets(struct device_node *node, |
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void __iomem *base) |
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{ |
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const __be32 *p; |
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int i, size; |
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/* look for RMII reset registers */ |
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p = of_get_property(node, "ti,dscr-rmii-resets", &size); |
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if (p) { |
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/* parse all the reg/mask pairs we can handle */ |
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size /= (sizeof(*p) * 2); |
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if (size > MAX_SOC_EMACS) |
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size = MAX_SOC_EMACS; |
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for (i = 0; i < size; i++) { |
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dscr.rmii_resets[i].reg = be32_to_cpup(p++); |
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dscr.rmii_resets[i].mask = be32_to_cpup(p++); |
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} |
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} |
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} |
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static void __init dscr_parse_privperm(struct device_node *node, |
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void __iomem *base) |
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{ |
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u32 vals[2]; |
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int err; |
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err = of_property_read_u32_array(node, "ti,dscr-privperm", vals, 2); |
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if (err) |
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return; |
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dscr_write(vals[0], vals[1]); |
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} |
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/* |
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* SoCs may have "locked" DSCR registers which can only be written |
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* to only after writing a key value to a lock registers. These |
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* regisers can be described with the "ti,dscr-locked-regs" property. |
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* This property provides a list of register descriptions with each |
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* description consisting of three values. |
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* |
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* ti,dscr-locked-regs = <reg0 lockreg0 key0 |
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* ... |
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* regN lockregN keyN>; |
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* |
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* reg is the offset of the locked register |
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* lockreg is the offset of the lock register |
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* key is the unlock key written to lockreg |
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* |
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*/ |
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static void __init dscr_parse_locked_regs(struct device_node *node, |
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void __iomem *base) |
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{ |
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struct locked_reg *r; |
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const __be32 *p; |
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int i, size; |
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p = of_get_property(node, "ti,dscr-locked-regs", &size); |
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if (p) { |
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/* parse all the register descriptions we can handle */ |
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size /= (sizeof(*p) * 3); |
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if (size > MAX_LOCKED_REGS) |
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size = MAX_LOCKED_REGS; |
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for (i = 0; i < size; i++) { |
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r = &dscr.locked[i]; |
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r->reg = be32_to_cpup(p++); |
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r->lockreg = be32_to_cpup(p++); |
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r->key = be32_to_cpup(p++); |
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} |
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} |
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} |
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/* |
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* SoCs may have DSCR registers which are only write enabled after |
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* writing specific key values to two registers. The two key registers |
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* and the key values can be parsed from a "ti,dscr-kick-regs" |
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* propety with the following layout: |
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* |
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* ti,dscr-kick-regs = <kickreg0 key0 kickreg1 key1> |
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* |
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* kickreg is the offset of the "kick" register |
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* key is the value which unlocks writing for protected regs |
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*/ |
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static void __init dscr_parse_kick_regs(struct device_node *node, |
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void __iomem *base) |
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{ |
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u32 vals[4]; |
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int err; |
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err = of_property_read_u32_array(node, "ti,dscr-kick-regs", vals, 4); |
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if (!err) { |
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dscr.kick_reg[0] = vals[0]; |
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dscr.kick_key[0] = vals[1]; |
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dscr.kick_reg[1] = vals[2]; |
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dscr.kick_key[1] = vals[3]; |
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} |
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} |
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/* |
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* SoCs may provide controls to enable/disable individual IP blocks. These |
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* controls in the DSCR usually control pin drivers but also may control |
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* clocking and or resets. The device tree is used to describe the bitfields |
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* in registers used to control device state. The number of bits and their |
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* values may vary even within the same register. |
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* |
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* The layout of these bitfields is described by the ti,dscr-devstate-ctl-regs |
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* property. This property is a list where each element describes a contiguous |
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* range of control fields with like properties. Each element of the list |
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* consists of 7 cells with the following values: |
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* |
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* start_id num_ids reg enable disable start_bit nbits |
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* |
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* start_id is device id for the first device control in the range |
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* num_ids is the number of device controls in the range |
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* reg is the offset of the register holding the control bits |
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* enable is the value to enable a device |
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* disable is the value to disable a device (0xffffffff if cannot disable) |
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* start_bit is the bit number of the first bit in the range |
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* nbits is the number of bits per device control |
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*/ |
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static void __init dscr_parse_devstate_ctl_regs(struct device_node *node, |
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void __iomem *base) |
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{ |
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struct devstate_ctl_reg *r; |
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const __be32 *p; |
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int i, j, size; |
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p = of_get_property(node, "ti,dscr-devstate-ctl-regs", &size); |
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if (p) { |
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/* parse all the ranges we can handle */ |
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size /= (sizeof(*p) * 7); |
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if (size > MAX_DEVCTL_REGS) |
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size = MAX_DEVCTL_REGS; |
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for (i = 0; i < size; i++) { |
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r = &dscr.devctl[i]; |
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r->start_id = be32_to_cpup(p++); |
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r->num_ids = be32_to_cpup(p++); |
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r->reg = be32_to_cpup(p++); |
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r->enable = be32_to_cpup(p++); |
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r->disable = be32_to_cpup(p++); |
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if (r->disable == 0xffffffff) |
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r->enable_only = 1; |
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r->shift = be32_to_cpup(p++); |
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r->nbits = be32_to_cpup(p++); |
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for (j = r->start_id; |
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j < (r->start_id + r->num_ids); |
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j++) |
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dscr.devstate_info[j].ctl = r; |
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} |
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} |
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} |
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/* |
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* SoCs may provide status registers indicating the state (enabled/disabled) of |
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* devices on the SoC. The device tree is used to describe the bitfields in |
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* registers used to provide device status. The number of bits and their |
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* values used to provide status may vary even within the same register. |
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* |
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* The layout of these bitfields is described by the ti,dscr-devstate-stat-regs |
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* property. This property is a list where each element describes a contiguous |
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* range of status fields with like properties. Each element of the list |
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* consists of 7 cells with the following values: |
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* |
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* start_id num_ids reg enable disable start_bit nbits |
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* |
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* start_id is device id for the first device status in the range |
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* num_ids is the number of devices covered by the range |
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* reg is the offset of the register holding the status bits |
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* enable is the value indicating device is enabled |
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* disable is the value indicating device is disabled |
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* start_bit is the bit number of the first bit in the range |
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* nbits is the number of bits per device status |
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*/ |
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static void __init dscr_parse_devstate_stat_regs(struct device_node *node, |
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void __iomem *base) |
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{ |
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struct devstate_stat_reg *r; |
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const __be32 *p; |
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int i, j, size; |
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p = of_get_property(node, "ti,dscr-devstate-stat-regs", &size); |
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if (p) { |
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/* parse all the ranges we can handle */ |
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size /= (sizeof(*p) * 7); |
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if (size > MAX_DEVSTAT_REGS) |
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size = MAX_DEVSTAT_REGS; |
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for (i = 0; i < size; i++) { |
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r = &dscr.devstat[i]; |
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r->start_id = be32_to_cpup(p++); |
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r->num_ids = be32_to_cpup(p++); |
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r->reg = be32_to_cpup(p++); |
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r->enable = be32_to_cpup(p++); |
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r->disable = be32_to_cpup(p++); |
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r->shift = be32_to_cpup(p++); |
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r->nbits = be32_to_cpup(p++); |
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for (j = r->start_id; |
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j < (r->start_id + r->num_ids); |
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j++) |
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dscr.devstate_info[j].stat = r; |
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} |
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} |
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} |
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|
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static struct of_device_id dscr_ids[] __initdata = { |
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{ .compatible = "ti,c64x+dscr" }, |
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{} |
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}; |
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|
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/* |
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* Probe for DSCR area. |
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* |
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* This has to be done early on in case timer or interrupt controller |
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* needs something. e.g. On C6455 SoC, timer must be enabled through |
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* DSCR before it is functional. |
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*/ |
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void __init dscr_probe(void) |
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{ |
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struct device_node *node; |
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void __iomem *base; |
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spin_lock_init(&dscr.lock); |
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node = of_find_matching_node(NULL, dscr_ids); |
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if (!node) |
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return; |
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base = of_iomap(node, 0); |
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if (!base) { |
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of_node_put(node); |
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return; |
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} |
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dscr.base = base; |
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dscr_parse_devstat(node, base); |
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dscr_parse_silicon_rev(node, base); |
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dscr_parse_mac_fuse(node, base); |
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dscr_parse_rmii_resets(node, base); |
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dscr_parse_locked_regs(node, base); |
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dscr_parse_kick_regs(node, base); |
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dscr_parse_devstate_ctl_regs(node, base); |
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dscr_parse_devstate_stat_regs(node, base); |
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dscr_parse_privperm(node, base); |
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}
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