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764 lines
26 KiB
764 lines
26 KiB
/* |
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* Copyright © 2008 Keith Packard |
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* |
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* Permission to use, copy, modify, distribute, and sell this software and its |
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* documentation for any purpose is hereby granted without fee, provided that |
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* the above copyright notice appear in all copies and that both that copyright |
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* notice and this permission notice appear in supporting documentation, and |
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* that the name of the copyright holders not be used in advertising or |
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* publicity pertaining to distribution of the software without specific, |
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* written prior permission. The copyright holders make no representations |
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* about the suitability of this software for any purpose. It is provided "as |
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* is" without express or implied warranty. |
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* |
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, |
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO |
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR |
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, |
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE |
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* OF THIS SOFTWARE. |
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*/ |
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#ifndef _DRM_DP_HELPER_H_ |
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#define _DRM_DP_HELPER_H_ |
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#include <linux/delay.h> |
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#include <linux/i2c.h> |
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#include <drm/display/drm_dp.h> |
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#include <drm/drm_connector.h> |
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struct drm_device; |
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struct drm_dp_aux; |
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struct drm_panel; |
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bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
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int lane_count); |
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bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
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int lane_count); |
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u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
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int lane); |
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u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
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int lane); |
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u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], |
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int lane); |
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int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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enum drm_dp_phy dp_phy, bool uhbr); |
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int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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enum drm_dp_phy dp_phy, bool uhbr); |
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void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, |
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const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
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void drm_dp_lttpr_link_train_clock_recovery_delay(void); |
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void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, |
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const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
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void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, |
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const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); |
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int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux); |
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bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], |
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int lane_count); |
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bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], |
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int lane_count); |
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bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); |
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bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); |
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bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]); |
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u8 drm_dp_link_rate_to_bw_code(int link_rate); |
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int drm_dp_bw_code_to_link_rate(u8 link_bw); |
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/** |
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* struct drm_dp_vsc_sdp - drm DP VSC SDP |
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* |
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* This structure represents a DP VSC SDP of drm |
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* It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and |
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* [Table 2-117: VSC SDP Payload for DB16 through DB18] |
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* |
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* @sdp_type: secondary-data packet type |
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* @revision: revision number |
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* @length: number of valid data bytes |
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* @pixelformat: pixel encoding format |
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* @colorimetry: colorimetry format |
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* @bpc: bit per color |
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* @dynamic_range: dynamic range information |
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* @content_type: CTA-861-G defines content types and expected processing by a sink device |
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*/ |
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struct drm_dp_vsc_sdp { |
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unsigned char sdp_type; |
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unsigned char revision; |
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unsigned char length; |
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enum dp_pixelformat pixelformat; |
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enum dp_colorimetry colorimetry; |
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int bpc; |
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enum dp_dynamic_range dynamic_range; |
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enum dp_content_type content_type; |
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}; |
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void drm_dp_vsc_sdp_log(const char *level, struct device *dev, |
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const struct drm_dp_vsc_sdp *vsc); |
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int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); |
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static inline int |
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drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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{ |
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return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); |
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} |
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static inline u8 |
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drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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{ |
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return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
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} |
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static inline bool |
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drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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{ |
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return dpcd[DP_DPCD_REV] >= 0x11 && |
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(dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); |
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} |
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static inline bool |
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drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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{ |
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return dpcd[DP_DPCD_REV] >= 0x11 && |
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(dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); |
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} |
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static inline bool |
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drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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{ |
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return dpcd[DP_DPCD_REV] >= 0x12 && |
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dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; |
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} |
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static inline bool |
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drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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{ |
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return dpcd[DP_DPCD_REV] >= 0x11 || |
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dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; |
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} |
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static inline bool |
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drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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{ |
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return dpcd[DP_DPCD_REV] >= 0x14 && |
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dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; |
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} |
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static inline u8 |
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drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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{ |
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return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : |
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DP_TRAINING_PATTERN_MASK; |
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} |
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static inline bool |
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drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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{ |
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return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; |
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} |
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/* DP/eDP DSC support */ |
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u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], |
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bool is_edp); |
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u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); |
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int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], |
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u8 dsc_bpc[3]); |
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static inline bool |
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drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) |
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{ |
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return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & |
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DP_DSC_DECOMPRESSION_IS_SUPPORTED; |
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} |
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static inline u16 |
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drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) |
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{ |
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return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | |
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(dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & |
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DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK << |
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DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT); |
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} |
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static inline u32 |
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drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) |
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{ |
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/* Max Slicewidth = Number of Pixels * 320 */ |
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return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * |
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DP_DSC_SLICE_WIDTH_MULTIPLIER; |
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} |
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/* Forward Error Correction Support on DP 1.4 */ |
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static inline bool |
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drm_dp_sink_supports_fec(const u8 fec_capable) |
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{ |
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return fec_capable & DP_FEC_CAPABLE; |
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} |
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static inline bool |
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drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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{ |
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return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; |
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} |
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static inline bool |
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drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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{ |
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return dpcd[DP_EDP_CONFIGURATION_CAP] & |
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DP_ALTERNATE_SCRAMBLER_RESET_CAP; |
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} |
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/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ |
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static inline bool |
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drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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{ |
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return dpcd[DP_DOWN_STREAM_PORT_COUNT] & |
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DP_MSA_TIMING_PAR_IGNORED; |
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} |
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/** |
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* drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support |
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* @edp_dpcd: The DPCD to check |
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* |
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* Note that currently this function will return %false for panels which support various DPCD |
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* backlight features but which require the brightness be set through PWM, and don't support setting |
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* the brightness level via the DPCD. |
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* |
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* Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false |
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* otherwise |
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*/ |
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static inline bool |
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drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) |
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{ |
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return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); |
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} |
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/* |
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* DisplayPort AUX channel |
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*/ |
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/** |
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* struct drm_dp_aux_msg - DisplayPort AUX channel transaction |
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* @address: address of the (first) register to access |
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* @request: contains the type of transaction (see DP_AUX_* macros) |
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* @reply: upon completion, contains the reply type of the transaction |
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* @buffer: pointer to a transmission or reception buffer |
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* @size: size of @buffer |
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*/ |
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struct drm_dp_aux_msg { |
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unsigned int address; |
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u8 request; |
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u8 reply; |
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void *buffer; |
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size_t size; |
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}; |
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struct cec_adapter; |
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struct edid; |
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struct drm_connector; |
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/** |
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* struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX |
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* @lock: mutex protecting this struct |
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* @adap: the CEC adapter for CEC-Tunneling-over-AUX support. |
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* @connector: the connector this CEC adapter is associated with |
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* @unregister_work: unregister the CEC adapter |
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*/ |
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struct drm_dp_aux_cec { |
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struct mutex lock; |
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struct cec_adapter *adap; |
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struct drm_connector *connector; |
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struct delayed_work unregister_work; |
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}; |
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/** |
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* struct drm_dp_aux - DisplayPort AUX channel |
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* |
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* An AUX channel can also be used to transport I2C messages to a sink. A |
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* typical application of that is to access an EDID that's present in the sink |
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* device. The @transfer() function can also be used to execute such |
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* transactions. The drm_dp_aux_register() function registers an I2C adapter |
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* that can be passed to drm_probe_ddc(). Upon removal, drivers should call |
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* drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long |
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* transfers by default; if a partial response is received, the adapter will |
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* drop down to the size given by the partial response for this transaction |
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* only. |
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*/ |
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struct drm_dp_aux { |
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/** |
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* @name: user-visible name of this AUX channel and the |
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* I2C-over-AUX adapter. |
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* |
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* It's also used to specify the name of the I2C adapter. If set |
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* to %NULL, dev_name() of @dev will be used. |
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*/ |
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const char *name; |
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/** |
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* @ddc: I2C adapter that can be used for I2C-over-AUX |
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* communication |
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*/ |
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struct i2c_adapter ddc; |
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/** |
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* @dev: pointer to struct device that is the parent for this |
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* AUX channel. |
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*/ |
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struct device *dev; |
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/** |
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* @drm_dev: pointer to the &drm_device that owns this AUX channel. |
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* Beware, this may be %NULL before drm_dp_aux_register() has been |
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* called. |
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* |
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* It should be set to the &drm_device that will be using this AUX |
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* channel as early as possible. For many graphics drivers this should |
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* happen before drm_dp_aux_init(), however it's perfectly fine to set |
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* this field later so long as it's assigned before calling |
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* drm_dp_aux_register(). |
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*/ |
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struct drm_device *drm_dev; |
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/** |
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* @crtc: backpointer to the crtc that is currently using this |
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* AUX channel |
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*/ |
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struct drm_crtc *crtc; |
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/** |
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* @hw_mutex: internal mutex used for locking transfers. |
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* |
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* Note that if the underlying hardware is shared among multiple |
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* channels, the driver needs to do additional locking to |
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* prevent concurrent access. |
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*/ |
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struct mutex hw_mutex; |
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/** |
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* @crc_work: worker that captures CRCs for each frame |
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*/ |
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struct work_struct crc_work; |
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/** |
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* @crc_count: counter of captured frame CRCs |
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*/ |
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u8 crc_count; |
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/** |
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* @transfer: transfers a message representing a single AUX |
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* transaction. |
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* |
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* This is a hardware-specific implementation of how |
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* transactions are executed that the drivers must provide. |
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* |
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* A pointer to a &drm_dp_aux_msg structure describing the |
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* transaction is passed into this function. Upon success, the |
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* implementation should return the number of payload bytes that |
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* were transferred, or a negative error-code on failure. |
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* |
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* Helpers will propagate these errors, with the exception of |
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* the %-EBUSY error, which causes a transaction to be retried. |
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* On a short, helpers will return %-EPROTO to make it simpler |
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* to check for failure. |
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* |
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* The @transfer() function must only modify the reply field of |
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* the &drm_dp_aux_msg structure. The retry logic and i2c |
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* helpers assume this is the case. |
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* |
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* Also note that this callback can be called no matter the |
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* state @dev is in and also no matter what state the panel is |
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* in. It's expected: |
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* |
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* - If the @dev providing the AUX bus is currently unpowered then |
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* it will power itself up for the transfer. |
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* |
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* - If we're on eDP (using a drm_panel) and the panel is not in a |
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* state where it can respond (it's not powered or it's in a |
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* low power state) then this function may return an error, but |
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* not crash. It's up to the caller of this code to make sure that |
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* the panel is powered on if getting an error back is not OK. If a |
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* drm_panel driver is initiating a DP AUX transfer it may power |
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* itself up however it wants. All other code should ensure that |
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* the pre_enable() bridge chain (which eventually calls the |
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* drm_panel prepare function) has powered the panel. |
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*/ |
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ssize_t (*transfer)(struct drm_dp_aux *aux, |
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struct drm_dp_aux_msg *msg); |
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|
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/** |
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* @wait_hpd_asserted: wait for HPD to be asserted |
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* |
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* This is mainly useful for eDP panels drivers to wait for an eDP |
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* panel to finish powering on. This is an optional function. |
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* |
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* This function will efficiently wait for the HPD signal to be |
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* asserted. The `wait_us` parameter that is passed in says that we |
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* know that the HPD signal is expected to be asserted within `wait_us` |
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* microseconds. This function could wait for longer than `wait_us` if |
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* the logic in the DP controller has a long debouncing time. The |
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* important thing is that if this function returns success that the |
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* DP controller is ready to send AUX transactions. |
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* |
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* This function returns 0 if HPD was asserted or -ETIMEDOUT if time |
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* expired and HPD wasn't asserted. This function should not print |
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* timeout errors to the log. |
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* |
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* The semantics of this function are designed to match the |
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* readx_poll_timeout() function. That means a `wait_us` of 0 means |
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* to wait forever. Like readx_poll_timeout(), this function may sleep. |
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* |
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* NOTE: this function specifically reports the state of the HPD pin |
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* that's associated with the DP AUX channel. This is different from |
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* the HPD concept in much of the rest of DRM which is more about |
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* physical presence of a display. For eDP, for instance, a display is |
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* assumed always present even if the HPD pin is deasserted. |
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*/ |
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int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us); |
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|
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/** |
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* @i2c_nack_count: Counts I2C NACKs, used for DP validation. |
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*/ |
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unsigned i2c_nack_count; |
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/** |
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* @i2c_defer_count: Counts I2C DEFERs, used for DP validation. |
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*/ |
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unsigned i2c_defer_count; |
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/** |
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* @cec: struct containing fields used for CEC-Tunneling-over-AUX. |
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*/ |
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struct drm_dp_aux_cec cec; |
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/** |
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* @is_remote: Is this AUX CH actually using sideband messaging. |
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*/ |
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bool is_remote; |
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}; |
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|
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int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset); |
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ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, |
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void *buffer, size_t size); |
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ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, |
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void *buffer, size_t size); |
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|
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/** |
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* drm_dp_dpcd_readb() - read a single byte from the DPCD |
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* @aux: DisplayPort AUX channel |
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* @offset: address of the register to read |
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* @valuep: location where the value of the register will be stored |
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* |
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* Returns the number of bytes transferred (1) on success, or a negative |
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* error code on failure. |
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*/ |
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static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, |
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unsigned int offset, u8 *valuep) |
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{ |
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return drm_dp_dpcd_read(aux, offset, valuep, 1); |
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} |
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|
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/** |
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* drm_dp_dpcd_writeb() - write a single byte to the DPCD |
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* @aux: DisplayPort AUX channel |
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* @offset: address of the register to write |
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* @value: value to write to the register |
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* |
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* Returns the number of bytes transferred (1) on success, or a negative |
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* error code on failure. |
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*/ |
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static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, |
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unsigned int offset, u8 value) |
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{ |
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return drm_dp_dpcd_write(aux, offset, &value, 1); |
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} |
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|
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int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, |
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u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
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|
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int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, |
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u8 status[DP_LINK_STATUS_SIZE]); |
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|
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int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, |
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enum drm_dp_phy dp_phy, |
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u8 link_status[DP_LINK_STATUS_SIZE]); |
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|
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bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, |
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u8 real_edid_checksum); |
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|
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int drm_dp_read_downstream_info(struct drm_dp_aux *aux, |
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const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); |
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bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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const u8 port_cap[4], u8 type); |
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bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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const u8 port_cap[4], |
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const struct edid *edid); |
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int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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const u8 port_cap[4]); |
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int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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const u8 port_cap[4], |
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const struct edid *edid); |
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int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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const u8 port_cap[4], |
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const struct edid *edid); |
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int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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const u8 port_cap[4], |
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const struct edid *edid); |
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bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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const u8 port_cap[4]); |
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bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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const u8 port_cap[4]); |
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struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, |
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const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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const u8 port_cap[4]); |
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int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); |
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void drm_dp_downstream_debug(struct seq_file *m, |
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const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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const u8 port_cap[4], |
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const struct edid *edid, |
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struct drm_dp_aux *aux); |
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enum drm_mode_subconnector |
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drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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const u8 port_cap[4]); |
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void drm_dp_set_subconnector_property(struct drm_connector *connector, |
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enum drm_connector_status status, |
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const u8 *dpcd, |
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const u8 port_cap[4]); |
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|
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struct drm_dp_desc; |
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bool drm_dp_read_sink_count_cap(struct drm_connector *connector, |
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const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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const struct drm_dp_desc *desc); |
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int drm_dp_read_sink_count(struct drm_dp_aux *aux); |
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|
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int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, |
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const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); |
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int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, |
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const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
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enum drm_dp_phy dp_phy, |
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u8 caps[DP_LTTPR_PHY_CAP_SIZE]); |
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int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); |
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int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); |
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int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); |
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bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); |
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bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); |
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|
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void drm_dp_remote_aux_init(struct drm_dp_aux *aux); |
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void drm_dp_aux_init(struct drm_dp_aux *aux); |
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int drm_dp_aux_register(struct drm_dp_aux *aux); |
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void drm_dp_aux_unregister(struct drm_dp_aux *aux); |
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|
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int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); |
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int drm_dp_stop_crc(struct drm_dp_aux *aux); |
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|
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struct drm_dp_dpcd_ident { |
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u8 oui[3]; |
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u8 device_id[6]; |
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u8 hw_rev; |
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u8 sw_major_rev; |
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u8 sw_minor_rev; |
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} __packed; |
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|
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/** |
|
* struct drm_dp_desc - DP branch/sink device descriptor |
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* @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). |
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* @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. |
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*/ |
|
struct drm_dp_desc { |
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struct drm_dp_dpcd_ident ident; |
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u32 quirks; |
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}; |
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|
|
int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, |
|
bool is_branch); |
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|
|
/** |
|
* enum drm_dp_quirk - Display Port sink/branch device specific quirks |
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* |
|
* Display Port sink and branch devices in the wild have a variety of bugs, try |
|
* to collect them here. The quirks are shared, but it's up to the drivers to |
|
* implement workarounds for them. |
|
*/ |
|
enum drm_dp_quirk { |
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/** |
|
* @DP_DPCD_QUIRK_CONSTANT_N: |
|
* |
|
* The device requires main link attributes Mvid and Nvid to be limited |
|
* to 16 bits. So will give a constant value (0x8000) for compatability. |
|
*/ |
|
DP_DPCD_QUIRK_CONSTANT_N, |
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/** |
|
* @DP_DPCD_QUIRK_NO_PSR: |
|
* |
|
* The device does not support PSR even if reports that it supports or |
|
* driver still need to implement proper handling for such device. |
|
*/ |
|
DP_DPCD_QUIRK_NO_PSR, |
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/** |
|
* @DP_DPCD_QUIRK_NO_SINK_COUNT: |
|
* |
|
* The device does not set SINK_COUNT to a non-zero value. |
|
* The driver should ignore SINK_COUNT during detection. Note that |
|
* drm_dp_read_sink_count_cap() automatically checks for this quirk. |
|
*/ |
|
DP_DPCD_QUIRK_NO_SINK_COUNT, |
|
/** |
|
* @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: |
|
* |
|
* The device supports MST DSC despite not supporting Virtual DPCD. |
|
* The DSC caps can be read from the physical aux instead. |
|
*/ |
|
DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, |
|
/** |
|
* @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: |
|
* |
|
* The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite |
|
* the DP_MAX_LINK_RATE register reporting a lower max multiplier. |
|
*/ |
|
DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, |
|
}; |
|
|
|
/** |
|
* drm_dp_has_quirk() - does the DP device have a specific quirk |
|
* @desc: Device descriptor filled by drm_dp_read_desc() |
|
* @quirk: Quirk to query for |
|
* |
|
* Return true if DP device identified by @desc has @quirk. |
|
*/ |
|
static inline bool |
|
drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) |
|
{ |
|
return desc->quirks & BIT(quirk); |
|
} |
|
|
|
/** |
|
* struct drm_edp_backlight_info - Probed eDP backlight info struct |
|
* @pwmgen_bit_count: The pwmgen bit count |
|
* @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any |
|
* @max: The maximum backlight level that may be set |
|
* @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register? |
|
* @aux_enable: Does the panel support the AUX enable cap? |
|
* @aux_set: Does the panel support setting the brightness through AUX? |
|
* |
|
* This structure contains various data about an eDP backlight, which can be populated by using |
|
* drm_edp_backlight_init(). |
|
*/ |
|
struct drm_edp_backlight_info { |
|
u8 pwmgen_bit_count; |
|
u8 pwm_freq_pre_divider; |
|
u16 max; |
|
|
|
bool lsb_reg_used : 1; |
|
bool aux_enable : 1; |
|
bool aux_set : 1; |
|
}; |
|
|
|
int |
|
drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, |
|
u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], |
|
u16 *current_level, u8 *current_mode); |
|
int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, |
|
u16 level); |
|
int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, |
|
u16 level); |
|
int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl); |
|
|
|
#if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ |
|
(IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))) |
|
|
|
int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux); |
|
|
|
#else |
|
|
|
static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel, |
|
struct drm_dp_aux *aux) |
|
{ |
|
return 0; |
|
} |
|
|
|
#endif |
|
|
|
#ifdef CONFIG_DRM_DP_CEC |
|
void drm_dp_cec_irq(struct drm_dp_aux *aux); |
|
void drm_dp_cec_register_connector(struct drm_dp_aux *aux, |
|
struct drm_connector *connector); |
|
void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); |
|
void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); |
|
void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); |
|
#else |
|
static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) |
|
{ |
|
} |
|
|
|
static inline void |
|
drm_dp_cec_register_connector(struct drm_dp_aux *aux, |
|
struct drm_connector *connector) |
|
{ |
|
} |
|
|
|
static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) |
|
{ |
|
} |
|
|
|
static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, |
|
const struct edid *edid) |
|
{ |
|
} |
|
|
|
static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) |
|
{ |
|
} |
|
|
|
#endif |
|
|
|
/** |
|
* struct drm_dp_phy_test_params - DP Phy Compliance parameters |
|
* @link_rate: Requested Link rate from DPCD 0x219 |
|
* @num_lanes: Number of lanes requested by sing through DPCD 0x220 |
|
* @phy_pattern: DP Phy test pattern from DPCD 0x248 |
|
* @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B |
|
* @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 |
|
* @enhanced_frame_cap: flag for enhanced frame capability. |
|
*/ |
|
struct drm_dp_phy_test_params { |
|
int link_rate; |
|
u8 num_lanes; |
|
u8 phy_pattern; |
|
u8 hbr2_reset[2]; |
|
u8 custom80[10]; |
|
bool enhanced_frame_cap; |
|
}; |
|
|
|
int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, |
|
struct drm_dp_phy_test_params *data); |
|
int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, |
|
struct drm_dp_phy_test_params *data, u8 dp_rev); |
|
int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
|
const u8 port_cap[4]); |
|
int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); |
|
bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); |
|
int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, |
|
u8 frl_mode); |
|
int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, |
|
u8 frl_type); |
|
int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); |
|
int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); |
|
|
|
bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); |
|
int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask); |
|
void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, |
|
struct drm_connector *connector); |
|
bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); |
|
int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); |
|
int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); |
|
int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); |
|
int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); |
|
int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]); |
|
int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]); |
|
bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
|
const u8 port_cap[4], u8 color_spc); |
|
int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); |
|
|
|
#endif /* _DRM_DP_HELPER_H_ */
|
|
|