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687 lines
18 KiB
687 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. |
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*/ |
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|
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#include <soc/tegra/ivc.h> |
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|
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#define TEGRA_IVC_ALIGN 64 |
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|
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/* |
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* IVC channel reset protocol. |
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* |
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* Each end uses its tx_channel.state to indicate its synchronization state. |
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*/ |
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enum tegra_ivc_state { |
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/* |
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* This value is zero for backwards compatibility with services that |
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* assume channels to be initially zeroed. Such channels are in an |
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* initially valid state, but cannot be asynchronously reset, and must |
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* maintain a valid state at all times. |
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* |
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* The transmitting end can enter the established state from the sync or |
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* ack state when it observes the receiving endpoint in the ack or |
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* established state, indicating that has cleared the counters in our |
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* rx_channel. |
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*/ |
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TEGRA_IVC_STATE_ESTABLISHED = 0, |
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|
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/* |
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* If an endpoint is observed in the sync state, the remote endpoint is |
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* allowed to clear the counters it owns asynchronously with respect to |
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* the current endpoint. Therefore, the current endpoint is no longer |
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* allowed to communicate. |
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*/ |
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TEGRA_IVC_STATE_SYNC, |
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|
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/* |
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* When the transmitting end observes the receiving end in the sync |
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* state, it can clear the w_count and r_count and transition to the ack |
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* state. If the remote endpoint observes us in the ack state, it can |
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* return to the established state once it has cleared its counters. |
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*/ |
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TEGRA_IVC_STATE_ACK |
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}; |
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/* |
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* This structure is divided into two-cache aligned parts, the first is only |
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* written through the tx.channel pointer, while the second is only written |
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* through the rx.channel pointer. This delineates ownership of the cache |
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* lines, which is critical to performance and necessary in non-cache coherent |
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* implementations. |
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*/ |
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struct tegra_ivc_header { |
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union { |
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struct { |
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/* fields owned by the transmitting end */ |
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u32 count; |
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u32 state; |
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}; |
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u8 pad[TEGRA_IVC_ALIGN]; |
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} tx; |
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union { |
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/* fields owned by the receiving end */ |
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u32 count; |
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u8 pad[TEGRA_IVC_ALIGN]; |
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} rx; |
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}; |
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static inline void tegra_ivc_invalidate(struct tegra_ivc *ivc, dma_addr_t phys) |
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{ |
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if (!ivc->peer) |
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return; |
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dma_sync_single_for_cpu(ivc->peer, phys, TEGRA_IVC_ALIGN, |
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DMA_FROM_DEVICE); |
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} |
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static inline void tegra_ivc_flush(struct tegra_ivc *ivc, dma_addr_t phys) |
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{ |
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if (!ivc->peer) |
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return; |
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dma_sync_single_for_device(ivc->peer, phys, TEGRA_IVC_ALIGN, |
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DMA_TO_DEVICE); |
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} |
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static inline bool tegra_ivc_empty(struct tegra_ivc *ivc, |
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struct tegra_ivc_header *header) |
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{ |
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/* |
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* This function performs multiple checks on the same values with |
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* security implications, so create snapshots with READ_ONCE() to |
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* ensure that these checks use the same values. |
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*/ |
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u32 tx = READ_ONCE(header->tx.count); |
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u32 rx = READ_ONCE(header->rx.count); |
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/* |
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* Perform an over-full check to prevent denial of service attacks |
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* where a server could be easily fooled into believing that there's |
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* an extremely large number of frames ready, since receivers are not |
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* expected to check for full or over-full conditions. |
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* |
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* Although the channel isn't empty, this is an invalid case caused by |
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* a potentially malicious peer, so returning empty is safer, because |
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* it gives the impression that the channel has gone silent. |
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*/ |
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if (tx - rx > ivc->num_frames) |
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return true; |
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return tx == rx; |
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} |
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static inline bool tegra_ivc_full(struct tegra_ivc *ivc, |
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struct tegra_ivc_header *header) |
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{ |
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u32 tx = READ_ONCE(header->tx.count); |
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u32 rx = READ_ONCE(header->rx.count); |
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|
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/* |
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* Invalid cases where the counters indicate that the queue is over |
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* capacity also appear full. |
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*/ |
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return tx - rx >= ivc->num_frames; |
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} |
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static inline u32 tegra_ivc_available(struct tegra_ivc *ivc, |
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struct tegra_ivc_header *header) |
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{ |
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u32 tx = READ_ONCE(header->tx.count); |
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u32 rx = READ_ONCE(header->rx.count); |
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/* |
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* This function isn't expected to be used in scenarios where an |
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* over-full situation can lead to denial of service attacks. See the |
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* comment in tegra_ivc_empty() for an explanation about special |
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* over-full considerations. |
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*/ |
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return tx - rx; |
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} |
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static inline void tegra_ivc_advance_tx(struct tegra_ivc *ivc) |
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{ |
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WRITE_ONCE(ivc->tx.channel->tx.count, |
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READ_ONCE(ivc->tx.channel->tx.count) + 1); |
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if (ivc->tx.position == ivc->num_frames - 1) |
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ivc->tx.position = 0; |
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else |
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ivc->tx.position++; |
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} |
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static inline void tegra_ivc_advance_rx(struct tegra_ivc *ivc) |
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{ |
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WRITE_ONCE(ivc->rx.channel->rx.count, |
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READ_ONCE(ivc->rx.channel->rx.count) + 1); |
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if (ivc->rx.position == ivc->num_frames - 1) |
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ivc->rx.position = 0; |
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else |
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ivc->rx.position++; |
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} |
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static inline int tegra_ivc_check_read(struct tegra_ivc *ivc) |
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{ |
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unsigned int offset = offsetof(struct tegra_ivc_header, tx.count); |
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/* |
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* tx.channel->state is set locally, so it is not synchronized with |
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* state from the remote peer. The remote peer cannot reset its |
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* transmit counters until we've acknowledged its synchronization |
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* request, so no additional synchronization is required because an |
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* asynchronous transition of rx.channel->state to |
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* TEGRA_IVC_STATE_ACK is not allowed. |
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*/ |
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if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED) |
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return -ECONNRESET; |
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/* |
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* Avoid unnecessary invalidations when performing repeated accesses |
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* to an IVC channel by checking the old queue pointers first. |
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* |
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* Synchronization is only necessary when these pointers indicate |
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* empty or full. |
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*/ |
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if (!tegra_ivc_empty(ivc, ivc->rx.channel)) |
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return 0; |
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tegra_ivc_invalidate(ivc, ivc->rx.phys + offset); |
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if (tegra_ivc_empty(ivc, ivc->rx.channel)) |
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return -ENOSPC; |
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return 0; |
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} |
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static inline int tegra_ivc_check_write(struct tegra_ivc *ivc) |
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{ |
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unsigned int offset = offsetof(struct tegra_ivc_header, rx.count); |
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if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED) |
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return -ECONNRESET; |
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if (!tegra_ivc_full(ivc, ivc->tx.channel)) |
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return 0; |
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tegra_ivc_invalidate(ivc, ivc->tx.phys + offset); |
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if (tegra_ivc_full(ivc, ivc->tx.channel)) |
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return -ENOSPC; |
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return 0; |
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} |
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static void *tegra_ivc_frame_virt(struct tegra_ivc *ivc, |
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struct tegra_ivc_header *header, |
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unsigned int frame) |
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{ |
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if (WARN_ON(frame >= ivc->num_frames)) |
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return ERR_PTR(-EINVAL); |
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return (void *)(header + 1) + ivc->frame_size * frame; |
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} |
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static inline dma_addr_t tegra_ivc_frame_phys(struct tegra_ivc *ivc, |
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dma_addr_t phys, |
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unsigned int frame) |
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{ |
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unsigned long offset; |
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offset = sizeof(struct tegra_ivc_header) + ivc->frame_size * frame; |
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return phys + offset; |
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} |
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static inline void tegra_ivc_invalidate_frame(struct tegra_ivc *ivc, |
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dma_addr_t phys, |
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unsigned int frame, |
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unsigned int offset, |
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size_t size) |
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{ |
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if (!ivc->peer || WARN_ON(frame >= ivc->num_frames)) |
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return; |
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phys = tegra_ivc_frame_phys(ivc, phys, frame) + offset; |
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dma_sync_single_for_cpu(ivc->peer, phys, size, DMA_FROM_DEVICE); |
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} |
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static inline void tegra_ivc_flush_frame(struct tegra_ivc *ivc, |
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dma_addr_t phys, |
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unsigned int frame, |
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unsigned int offset, |
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size_t size) |
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{ |
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if (!ivc->peer || WARN_ON(frame >= ivc->num_frames)) |
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return; |
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phys = tegra_ivc_frame_phys(ivc, phys, frame) + offset; |
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dma_sync_single_for_device(ivc->peer, phys, size, DMA_TO_DEVICE); |
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} |
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/* directly peek at the next frame rx'ed */ |
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void *tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc) |
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{ |
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int err; |
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if (WARN_ON(ivc == NULL)) |
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return ERR_PTR(-EINVAL); |
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err = tegra_ivc_check_read(ivc); |
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if (err < 0) |
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return ERR_PTR(err); |
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/* |
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* Order observation of ivc->rx.position potentially indicating new |
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* data before data read. |
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*/ |
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smp_rmb(); |
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tegra_ivc_invalidate_frame(ivc, ivc->rx.phys, ivc->rx.position, 0, |
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ivc->frame_size); |
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return tegra_ivc_frame_virt(ivc, ivc->rx.channel, ivc->rx.position); |
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} |
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EXPORT_SYMBOL(tegra_ivc_read_get_next_frame); |
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int tegra_ivc_read_advance(struct tegra_ivc *ivc) |
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{ |
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unsigned int rx = offsetof(struct tegra_ivc_header, rx.count); |
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unsigned int tx = offsetof(struct tegra_ivc_header, tx.count); |
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int err; |
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/* |
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* No read barriers or synchronization here: the caller is expected to |
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* have already observed the channel non-empty. This check is just to |
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* catch programming errors. |
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*/ |
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err = tegra_ivc_check_read(ivc); |
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if (err < 0) |
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return err; |
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tegra_ivc_advance_rx(ivc); |
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tegra_ivc_flush(ivc, ivc->rx.phys + rx); |
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/* |
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* Ensure our write to ivc->rx.position occurs before our read from |
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* ivc->tx.position. |
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*/ |
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smp_mb(); |
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/* |
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* Notify only upon transition from full to non-full. The available |
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* count can only asynchronously increase, so the worst possible |
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* side-effect will be a spurious notification. |
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*/ |
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tegra_ivc_invalidate(ivc, ivc->rx.phys + tx); |
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if (tegra_ivc_available(ivc, ivc->rx.channel) == ivc->num_frames - 1) |
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ivc->notify(ivc, ivc->notify_data); |
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return 0; |
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} |
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EXPORT_SYMBOL(tegra_ivc_read_advance); |
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/* directly poke at the next frame to be tx'ed */ |
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void *tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc) |
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{ |
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int err; |
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err = tegra_ivc_check_write(ivc); |
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if (err < 0) |
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return ERR_PTR(err); |
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return tegra_ivc_frame_virt(ivc, ivc->tx.channel, ivc->tx.position); |
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} |
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EXPORT_SYMBOL(tegra_ivc_write_get_next_frame); |
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/* advance the tx buffer */ |
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int tegra_ivc_write_advance(struct tegra_ivc *ivc) |
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{ |
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unsigned int tx = offsetof(struct tegra_ivc_header, tx.count); |
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unsigned int rx = offsetof(struct tegra_ivc_header, rx.count); |
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int err; |
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err = tegra_ivc_check_write(ivc); |
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if (err < 0) |
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return err; |
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tegra_ivc_flush_frame(ivc, ivc->tx.phys, ivc->tx.position, 0, |
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ivc->frame_size); |
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/* |
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* Order any possible stores to the frame before update of |
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* ivc->tx.position. |
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*/ |
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smp_wmb(); |
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tegra_ivc_advance_tx(ivc); |
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tegra_ivc_flush(ivc, ivc->tx.phys + tx); |
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/* |
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* Ensure our write to ivc->tx.position occurs before our read from |
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* ivc->rx.position. |
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*/ |
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smp_mb(); |
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/* |
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* Notify only upon transition from empty to non-empty. The available |
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* count can only asynchronously decrease, so the worst possible |
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* side-effect will be a spurious notification. |
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*/ |
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tegra_ivc_invalidate(ivc, ivc->tx.phys + rx); |
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if (tegra_ivc_available(ivc, ivc->tx.channel) == 1) |
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ivc->notify(ivc, ivc->notify_data); |
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return 0; |
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} |
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EXPORT_SYMBOL(tegra_ivc_write_advance); |
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void tegra_ivc_reset(struct tegra_ivc *ivc) |
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{ |
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unsigned int offset = offsetof(struct tegra_ivc_header, tx.count); |
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ivc->tx.channel->tx.state = TEGRA_IVC_STATE_SYNC; |
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tegra_ivc_flush(ivc, ivc->tx.phys + offset); |
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ivc->notify(ivc, ivc->notify_data); |
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} |
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EXPORT_SYMBOL(tegra_ivc_reset); |
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/* |
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* ======================================================= |
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* IVC State Transition Table - see tegra_ivc_notified() |
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* ======================================================= |
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* |
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* local remote action |
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* ----- ------ ----------------------------------- |
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* SYNC EST <none> |
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* SYNC ACK reset counters; move to EST; notify |
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* SYNC SYNC reset counters; move to ACK; notify |
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* ACK EST move to EST; notify |
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* ACK ACK move to EST; notify |
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* ACK SYNC reset counters; move to ACK; notify |
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* EST EST <none> |
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* EST ACK <none> |
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* EST SYNC reset counters; move to ACK; notify |
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* |
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* =============================================================== |
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*/ |
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int tegra_ivc_notified(struct tegra_ivc *ivc) |
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{ |
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unsigned int offset = offsetof(struct tegra_ivc_header, tx.count); |
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enum tegra_ivc_state state; |
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|
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/* Copy the receiver's state out of shared memory. */ |
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tegra_ivc_invalidate(ivc, ivc->rx.phys + offset); |
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state = READ_ONCE(ivc->rx.channel->tx.state); |
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if (state == TEGRA_IVC_STATE_SYNC) { |
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offset = offsetof(struct tegra_ivc_header, tx.count); |
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/* |
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* Order observation of TEGRA_IVC_STATE_SYNC before stores |
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* clearing tx.channel. |
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*/ |
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smp_rmb(); |
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/* |
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* Reset tx.channel counters. The remote end is in the SYNC |
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* state and won't make progress until we change our state, |
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* so the counters are not in use at this time. |
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*/ |
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ivc->tx.channel->tx.count = 0; |
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ivc->rx.channel->rx.count = 0; |
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ivc->tx.position = 0; |
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ivc->rx.position = 0; |
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/* |
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* Ensure that counters appear cleared before new state can be |
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* observed. |
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*/ |
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smp_wmb(); |
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/* |
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* Move to ACK state. We have just cleared our counters, so it |
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* is now safe for the remote end to start using these values. |
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*/ |
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ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ACK; |
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tegra_ivc_flush(ivc, ivc->tx.phys + offset); |
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/* |
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* Notify remote end to observe state transition. |
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*/ |
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ivc->notify(ivc, ivc->notify_data); |
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|
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} else if (ivc->tx.channel->tx.state == TEGRA_IVC_STATE_SYNC && |
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state == TEGRA_IVC_STATE_ACK) { |
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offset = offsetof(struct tegra_ivc_header, tx.count); |
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|
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/* |
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* Order observation of ivc_state_sync before stores clearing |
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* tx_channel. |
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*/ |
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smp_rmb(); |
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/* |
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* Reset tx.channel counters. The remote end is in the ACK |
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* state and won't make progress until we change our state, |
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* so the counters are not in use at this time. |
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*/ |
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ivc->tx.channel->tx.count = 0; |
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ivc->rx.channel->rx.count = 0; |
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ivc->tx.position = 0; |
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ivc->rx.position = 0; |
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/* |
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* Ensure that counters appear cleared before new state can be |
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* observed. |
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*/ |
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smp_wmb(); |
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|
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/* |
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* Move to ESTABLISHED state. We know that the remote end has |
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* already cleared its counters, so it is safe to start |
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* writing/reading on this channel. |
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*/ |
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ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ESTABLISHED; |
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tegra_ivc_flush(ivc, ivc->tx.phys + offset); |
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|
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/* |
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* Notify remote end to observe state transition. |
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*/ |
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ivc->notify(ivc, ivc->notify_data); |
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|
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} else if (ivc->tx.channel->tx.state == TEGRA_IVC_STATE_ACK) { |
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offset = offsetof(struct tegra_ivc_header, tx.count); |
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|
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/* |
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* At this point, we have observed the peer to be in either |
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* the ACK or ESTABLISHED state. Next, order observation of |
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* peer state before storing to tx.channel. |
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*/ |
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smp_rmb(); |
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|
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/* |
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* Move to ESTABLISHED state. We know that we have previously |
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* cleared our counters, and we know that the remote end has |
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* cleared its counters, so it is safe to start writing/reading |
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* on this channel. |
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*/ |
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ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ESTABLISHED; |
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tegra_ivc_flush(ivc, ivc->tx.phys + offset); |
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|
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/* |
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* Notify remote end to observe state transition. |
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*/ |
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ivc->notify(ivc, ivc->notify_data); |
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|
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} else { |
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/* |
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* There is no need to handle any further action. Either the |
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* channel is already fully established, or we are waiting for |
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* the remote end to catch up with our current state. Refer |
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* to the diagram in "IVC State Transition Table" above. |
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*/ |
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} |
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|
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if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED) |
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return -EAGAIN; |
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return 0; |
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} |
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EXPORT_SYMBOL(tegra_ivc_notified); |
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size_t tegra_ivc_align(size_t size) |
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{ |
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return ALIGN(size, TEGRA_IVC_ALIGN); |
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} |
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EXPORT_SYMBOL(tegra_ivc_align); |
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unsigned tegra_ivc_total_queue_size(unsigned queue_size) |
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{ |
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if (!IS_ALIGNED(queue_size, TEGRA_IVC_ALIGN)) { |
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pr_err("%s: queue_size (%u) must be %u-byte aligned\n", |
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__func__, queue_size, TEGRA_IVC_ALIGN); |
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return 0; |
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} |
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return queue_size + sizeof(struct tegra_ivc_header); |
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} |
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EXPORT_SYMBOL(tegra_ivc_total_queue_size); |
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|
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static int tegra_ivc_check_params(unsigned long rx, unsigned long tx, |
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unsigned int num_frames, size_t frame_size) |
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{ |
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BUILD_BUG_ON(!IS_ALIGNED(offsetof(struct tegra_ivc_header, tx.count), |
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TEGRA_IVC_ALIGN)); |
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BUILD_BUG_ON(!IS_ALIGNED(offsetof(struct tegra_ivc_header, rx.count), |
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TEGRA_IVC_ALIGN)); |
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BUILD_BUG_ON(!IS_ALIGNED(sizeof(struct tegra_ivc_header), |
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TEGRA_IVC_ALIGN)); |
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|
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if ((uint64_t)num_frames * (uint64_t)frame_size >= 0x100000000UL) { |
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pr_err("num_frames * frame_size overflows\n"); |
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return -EINVAL; |
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} |
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|
|
if (!IS_ALIGNED(frame_size, TEGRA_IVC_ALIGN)) { |
|
pr_err("frame size not adequately aligned: %zu\n", frame_size); |
|
return -EINVAL; |
|
} |
|
|
|
/* |
|
* The headers must at least be aligned enough for counters |
|
* to be accessed atomically. |
|
*/ |
|
if (!IS_ALIGNED(rx, TEGRA_IVC_ALIGN)) { |
|
pr_err("IVC channel start not aligned: %#lx\n", rx); |
|
return -EINVAL; |
|
} |
|
|
|
if (!IS_ALIGNED(tx, TEGRA_IVC_ALIGN)) { |
|
pr_err("IVC channel start not aligned: %#lx\n", tx); |
|
return -EINVAL; |
|
} |
|
|
|
if (rx < tx) { |
|
if (rx + frame_size * num_frames > tx) { |
|
pr_err("queue regions overlap: %#lx + %zx > %#lx\n", |
|
rx, frame_size * num_frames, tx); |
|
return -EINVAL; |
|
} |
|
} else { |
|
if (tx + frame_size * num_frames > rx) { |
|
pr_err("queue regions overlap: %#lx + %zx > %#lx\n", |
|
tx, frame_size * num_frames, rx); |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, void *rx, |
|
dma_addr_t rx_phys, void *tx, dma_addr_t tx_phys, |
|
unsigned int num_frames, size_t frame_size, |
|
void (*notify)(struct tegra_ivc *ivc, void *data), |
|
void *data) |
|
{ |
|
size_t queue_size; |
|
int err; |
|
|
|
if (WARN_ON(!ivc || !notify)) |
|
return -EINVAL; |
|
|
|
/* |
|
* All sizes that can be returned by communication functions should |
|
* fit in an int. |
|
*/ |
|
if (frame_size > INT_MAX) |
|
return -E2BIG; |
|
|
|
err = tegra_ivc_check_params((unsigned long)rx, (unsigned long)tx, |
|
num_frames, frame_size); |
|
if (err < 0) |
|
return err; |
|
|
|
queue_size = tegra_ivc_total_queue_size(num_frames * frame_size); |
|
|
|
if (peer) { |
|
ivc->rx.phys = dma_map_single(peer, rx, queue_size, |
|
DMA_BIDIRECTIONAL); |
|
if (dma_mapping_error(peer, ivc->rx.phys)) |
|
return -ENOMEM; |
|
|
|
ivc->tx.phys = dma_map_single(peer, tx, queue_size, |
|
DMA_BIDIRECTIONAL); |
|
if (dma_mapping_error(peer, ivc->tx.phys)) { |
|
dma_unmap_single(peer, ivc->rx.phys, queue_size, |
|
DMA_BIDIRECTIONAL); |
|
return -ENOMEM; |
|
} |
|
} else { |
|
ivc->rx.phys = rx_phys; |
|
ivc->tx.phys = tx_phys; |
|
} |
|
|
|
ivc->rx.channel = rx; |
|
ivc->tx.channel = tx; |
|
ivc->peer = peer; |
|
ivc->notify = notify; |
|
ivc->notify_data = data; |
|
ivc->frame_size = frame_size; |
|
ivc->num_frames = num_frames; |
|
|
|
/* |
|
* These values aren't necessarily correct until the channel has been |
|
* reset. |
|
*/ |
|
ivc->tx.position = 0; |
|
ivc->rx.position = 0; |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL(tegra_ivc_init); |
|
|
|
void tegra_ivc_cleanup(struct tegra_ivc *ivc) |
|
{ |
|
if (ivc->peer) { |
|
size_t size = tegra_ivc_total_queue_size(ivc->num_frames * |
|
ivc->frame_size); |
|
|
|
dma_unmap_single(ivc->peer, ivc->rx.phys, size, |
|
DMA_BIDIRECTIONAL); |
|
dma_unmap_single(ivc->peer, ivc->tx.phys, size, |
|
DMA_BIDIRECTIONAL); |
|
} |
|
} |
|
EXPORT_SYMBOL(tegra_ivc_cleanup);
|
|
|