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353 lines
12 KiB
353 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* OMAP3 Clock init |
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* |
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* Copyright (C) 2013 Texas Instruments, Inc |
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* Tero Kristo ([email protected]) |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/list.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/clk/ti.h> |
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#include "clock.h" |
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#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 |
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#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5 |
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#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 |
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#define OMAP34XX_CM_IDLEST_VAL 1 |
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/* |
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* In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported |
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* in the same register at a bit offset of 0x8. The EN_ACK for ICK is |
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* at an offset of 4 from ICK enable bit. |
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*/ |
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#define AM35XX_IPSS_ICK_MASK 0xF |
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#define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4 |
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#define AM35XX_IPSS_ICK_FCK_OFFSET 0x8 |
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#define AM35XX_IPSS_CLK_IDLEST_VAL 0 |
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#define AM35XX_ST_IPSS_SHIFT 5 |
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/** |
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* omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI |
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* @clk: struct clk * being enabled |
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* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
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* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
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* @idlest_val: pointer to a u8 to store the CM_IDLEST indicator |
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* |
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* The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift |
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* from the CM_{I,F}CLKEN bit. Pass back the correct info via |
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* @idlest_reg and @idlest_bit. No return value. |
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*/ |
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static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk, |
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struct clk_omap_reg *idlest_reg, |
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u8 *idlest_bit, |
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u8 *idlest_val) |
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{ |
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memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg)); |
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idlest_reg->offset &= ~0xf0; |
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idlest_reg->offset |= 0x20; |
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*idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; |
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*idlest_val = OMAP34XX_CM_IDLEST_VAL; |
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} |
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const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = { |
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.allow_idle = omap2_clkt_iclk_allow_idle, |
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.deny_idle = omap2_clkt_iclk_deny_idle, |
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.find_idlest = omap3430es2_clk_ssi_find_idlest, |
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.find_companion = omap2_clk_dflt_find_companion, |
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}; |
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/** |
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* omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST |
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* @clk: struct clk * being enabled |
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* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
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* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
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* @idlest_val: pointer to a u8 to store the CM_IDLEST indicator |
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* |
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* Some OMAP modules on OMAP3 ES2+ chips have both initiator and |
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* target IDLEST bits. For our purposes, we are concerned with the |
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* target IDLEST bits, which exist at a different bit position than |
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* the *CLKEN bit position for these modules (DSS and USBHOST) (The |
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* default find_idlest code assumes that they are at the same |
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* position.) No return value. |
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*/ |
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static void |
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omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk, |
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struct clk_omap_reg *idlest_reg, |
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u8 *idlest_bit, u8 *idlest_val) |
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{ |
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memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg)); |
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idlest_reg->offset &= ~0xf0; |
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idlest_reg->offset |= 0x20; |
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/* USBHOST_IDLE has same shift */ |
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*idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; |
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*idlest_val = OMAP34XX_CM_IDLEST_VAL; |
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} |
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const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = { |
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.find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, |
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.find_companion = omap2_clk_dflt_find_companion, |
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}; |
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const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = { |
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.allow_idle = omap2_clkt_iclk_allow_idle, |
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.deny_idle = omap2_clkt_iclk_deny_idle, |
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.find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, |
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.find_companion = omap2_clk_dflt_find_companion, |
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}; |
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/** |
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* omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB |
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* @clk: struct clk * being enabled |
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* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
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* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
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* @idlest_val: pointer to a u8 to store the CM_IDLEST indicator |
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* |
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* The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different |
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* shift from the CM_{I,F}CLKEN bit. Pass back the correct info via |
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* @idlest_reg and @idlest_bit. No return value. |
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*/ |
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static void |
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omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk, |
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struct clk_omap_reg *idlest_reg, |
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u8 *idlest_bit, |
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u8 *idlest_val) |
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{ |
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memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg)); |
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idlest_reg->offset &= ~0xf0; |
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idlest_reg->offset |= 0x20; |
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*idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; |
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*idlest_val = OMAP34XX_CM_IDLEST_VAL; |
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} |
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const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = { |
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.allow_idle = omap2_clkt_iclk_allow_idle, |
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.deny_idle = omap2_clkt_iclk_deny_idle, |
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.find_idlest = omap3430es2_clk_hsotgusb_find_idlest, |
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.find_companion = omap2_clk_dflt_find_companion, |
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}; |
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/** |
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* am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS |
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* @clk: struct clk * being enabled |
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* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
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* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
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* @idlest_val: pointer to a u8 to store the CM_IDLEST indicator |
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* |
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* The interface clocks on AM35xx IPSS reflects the clock idle status |
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* in the enable register itsel at a bit offset of 4 from the enable |
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* bit. A value of 1 indicates that clock is enabled. |
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*/ |
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static void am35xx_clk_find_idlest(struct clk_hw_omap *clk, |
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struct clk_omap_reg *idlest_reg, |
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u8 *idlest_bit, |
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u8 *idlest_val) |
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{ |
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memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg)); |
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*idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; |
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*idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL; |
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} |
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/** |
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* am35xx_clk_find_companion - find companion clock to @clk |
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* @clk: struct clk * to find the companion clock of |
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* @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in |
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* @other_bit: u8 ** to return the companion clock bit shift in |
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* |
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* Some clocks don't have companion clocks. For example, modules with |
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* only an interface clock (such as HECC) don't have a companion |
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* clock. Right now, this code relies on the hardware exporting a bit |
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* in the correct companion register that indicates that the |
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* nonexistent 'companion clock' is active. Future patches will |
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* associate this type of code with per-module data structures to |
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* avoid this issue, and remove the casts. No return value. |
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*/ |
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static void am35xx_clk_find_companion(struct clk_hw_omap *clk, |
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struct clk_omap_reg *other_reg, |
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u8 *other_bit) |
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{ |
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memcpy(other_reg, &clk->enable_reg, sizeof(*other_reg)); |
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if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) |
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*other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; |
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else |
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*other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; |
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} |
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const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = { |
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.find_idlest = am35xx_clk_find_idlest, |
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.find_companion = am35xx_clk_find_companion, |
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}; |
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/** |
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* am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS |
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* @clk: struct clk * being enabled |
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* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
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* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
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* @idlest_val: pointer to a u8 to store the CM_IDLEST indicator |
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* |
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* The IPSS target CM_IDLEST bit is at a different shift from the |
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* CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg |
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* and @idlest_bit. No return value. |
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*/ |
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static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk, |
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struct clk_omap_reg *idlest_reg, |
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u8 *idlest_bit, |
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u8 *idlest_val) |
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{ |
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memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg)); |
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idlest_reg->offset &= ~0xf0; |
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idlest_reg->offset |= 0x20; |
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*idlest_bit = AM35XX_ST_IPSS_SHIFT; |
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*idlest_val = OMAP34XX_CM_IDLEST_VAL; |
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} |
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const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = { |
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.allow_idle = omap2_clkt_iclk_allow_idle, |
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.deny_idle = omap2_clkt_iclk_deny_idle, |
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.find_idlest = am35xx_clk_ipss_find_idlest, |
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.find_companion = omap2_clk_dflt_find_companion, |
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}; |
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static struct ti_dt_clk omap3xxx_clks[] = { |
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DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"), |
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DT_CLK(NULL, "timer_sys_ck", "sys_ck"), |
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{ .node_name = NULL }, |
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}; |
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static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = { |
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DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"), |
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DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"), |
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DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"), |
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DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"), |
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{ .node_name = NULL }, |
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}; |
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static struct ti_dt_clk omap3430es1_clks[] = { |
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DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"), |
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DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"), |
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DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"), |
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DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"), |
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DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"), |
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DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"), |
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{ .node_name = NULL }, |
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}; |
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static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = { |
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DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"), |
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DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"), |
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{ .node_name = NULL }, |
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}; |
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static struct ti_dt_clk am35xx_clks[] = { |
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DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"), |
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DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"), |
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DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"), |
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DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"), |
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{ .node_name = NULL }, |
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}; |
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static const char *enable_init_clks[] = { |
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"sdrc_ick", |
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"gpmc_fck", |
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"omapctrl_ick", |
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}; |
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enum { |
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OMAP3_SOC_AM35XX, |
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OMAP3_SOC_OMAP3430_ES1, |
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OMAP3_SOC_OMAP3430_ES2_PLUS, |
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OMAP3_SOC_OMAP3630, |
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}; |
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/** |
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* omap3_clk_lock_dpll5 - locks DPLL5 |
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* |
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* Locks DPLL5 to a pre-defined frequency. This is required for proper |
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* operation of USB. |
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*/ |
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void __init omap3_clk_lock_dpll5(void) |
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{ |
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struct clk *dpll5_clk; |
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struct clk *dpll5_m2_clk; |
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/* |
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* Errata sprz319f advisory 2.1 documents a USB host clock drift issue |
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* that can be worked around using specially crafted dpll5 settings |
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* with a dpll5_m2 divider set to 8. Set the dpll5 rate to 8x the USB |
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* host clock rate, its .set_rate handler() will detect that frequency |
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* and use the errata settings. |
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*/ |
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dpll5_clk = clk_get(NULL, "dpll5_ck"); |
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clk_set_rate(dpll5_clk, OMAP3_DPLL5_FREQ_FOR_USBHOST * 8); |
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clk_prepare_enable(dpll5_clk); |
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/* Program dpll5_m2_clk divider */ |
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dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); |
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clk_prepare_enable(dpll5_m2_clk); |
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clk_set_rate(dpll5_m2_clk, OMAP3_DPLL5_FREQ_FOR_USBHOST); |
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clk_disable_unprepare(dpll5_m2_clk); |
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clk_disable_unprepare(dpll5_clk); |
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} |
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static int __init omap3xxx_dt_clk_init(int soc_type) |
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{ |
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if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 || |
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soc_type == OMAP3_SOC_OMAP3430_ES1 || |
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soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS) |
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ti_dt_clocks_register(omap3xxx_clks); |
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if (soc_type == OMAP3_SOC_AM35XX) |
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ti_dt_clocks_register(am35xx_clks); |
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if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX || |
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soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS) |
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ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks); |
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if (soc_type == OMAP3_SOC_OMAP3430_ES1) |
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ti_dt_clocks_register(omap3430es1_clks); |
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if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS || |
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soc_type == OMAP3_SOC_OMAP3630) |
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ti_dt_clocks_register(omap36xx_omap3430es2plus_clks); |
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omap2_clk_disable_autoidle_all(); |
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ti_clk_add_aliases(); |
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omap2_clk_enable_init_clocks(enable_init_clks, |
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ARRAY_SIZE(enable_init_clks)); |
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pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", |
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(clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000), |
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(clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10, |
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(clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000), |
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(clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000)); |
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if (soc_type != OMAP3_SOC_OMAP3430_ES1) |
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omap3_clk_lock_dpll5(); |
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return 0; |
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} |
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int __init omap3430_dt_clk_init(void) |
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{ |
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return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS); |
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} |
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int __init omap3630_dt_clk_init(void) |
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{ |
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return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3630); |
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} |
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int __init am35xx_dt_clk_init(void) |
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{ |
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return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX); |
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}
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