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141 lines
5.3 KiB
141 lines
5.3 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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// |
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// Copyright (c) 2021 MediaTek Inc. |
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// Author: Chun-Jie Chen <[email protected]> |
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#include "clk-gate.h" |
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#include "clk-mtk.h" |
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#include <dt-bindings/clock/mt8195-clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/platform_device.h> |
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static const struct mtk_gate_regs vdo0_0_cg_regs = { |
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.set_ofs = 0x104, |
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.clr_ofs = 0x108, |
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.sta_ofs = 0x100, |
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}; |
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static const struct mtk_gate_regs vdo0_1_cg_regs = { |
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.set_ofs = 0x114, |
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.clr_ofs = 0x118, |
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.sta_ofs = 0x110, |
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}; |
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static const struct mtk_gate_regs vdo0_2_cg_regs = { |
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.set_ofs = 0x124, |
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.clr_ofs = 0x128, |
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.sta_ofs = 0x120, |
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}; |
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#define GATE_VDO0_0(_id, _name, _parent, _shift) \ |
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GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
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#define GATE_VDO0_1(_id, _name, _parent, _shift) \ |
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GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
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#define GATE_VDO0_2(_id, _name, _parent, _shift) \ |
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GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
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static const struct mtk_gate vdo0_clks[] = { |
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/* VDO0_0 */ |
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GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0), |
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GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "top_vpp", 2), |
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GATE_VDO0_0(CLK_VDO0_DISP_COLOR1, "vdo0_disp_color1", "top_vpp", 3), |
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GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "top_vpp", 4), |
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GATE_VDO0_0(CLK_VDO0_DISP_CCORR1, "vdo0_disp_ccorr1", "top_vpp", 5), |
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GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "top_vpp", 6), |
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GATE_VDO0_0(CLK_VDO0_DISP_AAL1, "vdo0_disp_aal1", "top_vpp", 7), |
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GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "top_vpp", 8), |
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GATE_VDO0_0(CLK_VDO0_DISP_GAMMA1, "vdo0_disp_gamma1", "top_vpp", 9), |
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GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "top_vpp", 10), |
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GATE_VDO0_0(CLK_VDO0_DISP_DITHER1, "vdo0_disp_dither1", "top_vpp", 11), |
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GATE_VDO0_0(CLK_VDO0_DISP_OVL1, "vdo0_disp_ovl1", "top_vpp", 16), |
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GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "top_vpp", 17), |
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GATE_VDO0_0(CLK_VDO0_DISP_WDMA1, "vdo0_disp_wdma1", "top_vpp", 18), |
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GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "top_vpp", 19), |
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GATE_VDO0_0(CLK_VDO0_DISP_RDMA1, "vdo0_disp_rdma1", "top_vpp", 20), |
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GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21), |
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GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22), |
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GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "top_vpp", 23), |
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GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "top_vpp", 24), |
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GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp", 25), |
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GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "top_vpp", 26), |
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GATE_VDO0_0(CLK_VDO0_DISP_IL_ROT0, "vdo0_disp_il_rot0", "top_vpp", 27), |
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GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp", 28), |
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GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "top_vpp", 29), |
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GATE_VDO0_0(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "top_vpp", 30), |
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/* VDO0_1 */ |
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GATE_VDO0_1(CLK_VDO0_DL_ASYNC0, "vdo0_dl_async0", "top_vpp", 0), |
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GATE_VDO0_1(CLK_VDO0_DL_ASYNC1, "vdo0_dl_async1", "top_vpp", 1), |
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GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "top_vpp", 2), |
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GATE_VDO0_1(CLK_VDO0_DL_ASYNC3, "vdo0_dl_async3", "top_vpp", 3), |
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GATE_VDO0_1(CLK_VDO0_DL_ASYNC4, "vdo0_dl_async4", "top_vpp", 4), |
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GATE_VDO0_1(CLK_VDO0_DISP_MONITOR0, "vdo0_disp_monitor0", "top_vpp", 5), |
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GATE_VDO0_1(CLK_VDO0_DISP_MONITOR1, "vdo0_disp_monitor1", "top_vpp", 6), |
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GATE_VDO0_1(CLK_VDO0_DISP_MONITOR2, "vdo0_disp_monitor2", "top_vpp", 7), |
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GATE_VDO0_1(CLK_VDO0_DISP_MONITOR3, "vdo0_disp_monitor3", "top_vpp", 8), |
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GATE_VDO0_1(CLK_VDO0_DISP_MONITOR4, "vdo0_disp_monitor4", "top_vpp", 9), |
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GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp", 10), |
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GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "top_vpp", 11), |
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GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp", 12), |
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GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "top_vpp", 13), |
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GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp", 14), |
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GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp", 15), |
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/* VDO0_2 */ |
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GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0), |
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GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8), |
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GATE_VDO0_2(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", "top_edp", 16), |
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}; |
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static int clk_mt8195_vdo0_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *node = dev->parent->of_node; |
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struct clk_hw_onecell_data *clk_data; |
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int r; |
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clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK); |
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if (!clk_data) |
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return -ENOMEM; |
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r = mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data); |
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if (r) |
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goto free_vdo0_data; |
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); |
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if (r) |
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goto unregister_gates; |
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platform_set_drvdata(pdev, clk_data); |
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return r; |
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unregister_gates: |
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mtk_clk_unregister_gates(vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data); |
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free_vdo0_data: |
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mtk_free_clk_data(clk_data); |
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return r; |
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} |
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static int clk_mt8195_vdo0_remove(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *node = dev->parent->of_node; |
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); |
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of_clk_del_provider(node); |
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mtk_clk_unregister_gates(vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data); |
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mtk_free_clk_data(clk_data); |
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return 0; |
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} |
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static struct platform_driver clk_mt8195_vdo0_drv = { |
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.probe = clk_mt8195_vdo0_probe, |
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.remove = clk_mt8195_vdo0_remove, |
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.driver = { |
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.name = "clk-mt8195-vdo0", |
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}, |
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}; |
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builtin_platform_driver(clk_mt8195_vdo0_drv);
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