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54 lines
1.4 KiB
54 lines
1.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Copyright (c) 2018 MediaTek Inc. |
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// Author: Weiyi Lu <[email protected]> |
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#include <linux/clk-provider.h> |
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#include <linux/platform_device.h> |
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#include "clk-mtk.h" |
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#include "clk-gate.h" |
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#include <dt-bindings/clock/mt8183-clk.h> |
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static const struct mtk_gate_regs ipu_adl_cg_regs = { |
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.set_ofs = 0x204, |
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.clr_ofs = 0x204, |
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.sta_ofs = 0x204, |
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}; |
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#define GATE_IPU_ADL_I(_id, _name, _parent, _shift) \ |
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GATE_MTK(_id, _name, _parent, &ipu_adl_cg_regs, _shift, \ |
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&mtk_clk_gate_ops_no_setclr_inv) |
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static const struct mtk_gate ipu_adl_clks[] = { |
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GATE_IPU_ADL_I(CLK_IPU_ADL_CABGEN, "ipu_adl_cabgen", "dsp_sel", 24), |
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}; |
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static int clk_mt8183_ipu_adl_probe(struct platform_device *pdev) |
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{ |
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struct clk_hw_onecell_data *clk_data; |
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struct device_node *node = pdev->dev.of_node; |
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clk_data = mtk_alloc_clk_data(CLK_IPU_ADL_NR_CLK); |
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mtk_clk_register_gates(node, ipu_adl_clks, ARRAY_SIZE(ipu_adl_clks), |
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clk_data); |
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return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); |
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} |
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static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = { |
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{ .compatible = "mediatek,mt8183-ipu_adl", }, |
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{} |
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}; |
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static struct platform_driver clk_mt8183_ipu_adl_drv = { |
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.probe = clk_mt8183_ipu_adl_probe, |
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.driver = { |
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.name = "clk-mt8183-ipu_adl", |
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.of_match_table = of_match_clk_mt8183_ipu_adl, |
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}, |
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}; |
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builtin_platform_driver(clk_mt8183_ipu_adl_drv);
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