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322 lines
8.3 KiB
322 lines
8.3 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Driver for Renesas 9-series PCIe clock generator driver |
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* |
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* The following series can be supported: |
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* - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ |
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* Currently supported: |
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* - 9FGV0241 |
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* |
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* Copyright (C) 2022 Marek Vasut <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/i2c.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/regmap.h> |
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#define RS9_REG_OE 0x0 |
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#define RS9_REG_OE_DIF_OE(n) BIT((n) + 1) |
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#define RS9_REG_SS 0x1 |
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#define RS9_REG_SS_AMP_0V6 0x0 |
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#define RS9_REG_SS_AMP_0V7 0x1 |
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#define RS9_REG_SS_AMP_0V8 0x2 |
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#define RS9_REG_SS_AMP_0V9 0x3 |
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#define RS9_REG_SS_AMP_MASK 0x3 |
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#define RS9_REG_SS_SSC_100 0 |
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#define RS9_REG_SS_SSC_M025 (1 << 3) |
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#define RS9_REG_SS_SSC_M050 (3 << 3) |
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#define RS9_REG_SS_SSC_MASK (3 << 3) |
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#define RS9_REG_SS_SSC_LOCK BIT(5) |
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#define RS9_REG_SR 0x2 |
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#define RS9_REG_SR_2V0_DIF(n) 0 |
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#define RS9_REG_SR_3V0_DIF(n) BIT((n) + 1) |
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#define RS9_REG_SR_DIF_MASK(n) BIT((n) + 1) |
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#define RS9_REG_REF 0x3 |
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#define RS9_REG_REF_OE BIT(4) |
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#define RS9_REG_REF_OD BIT(5) |
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#define RS9_REG_REF_SR_SLOWEST 0 |
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#define RS9_REG_REF_SR_SLOW (1 << 6) |
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#define RS9_REG_REF_SR_FAST (2 << 6) |
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#define RS9_REG_REF_SR_FASTER (3 << 6) |
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#define RS9_REG_VID 0x5 |
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#define RS9_REG_DID 0x6 |
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#define RS9_REG_BCP 0x7 |
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/* Supported Renesas 9-series models. */ |
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enum rs9_model { |
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RENESAS_9FGV0241, |
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}; |
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/* Structure to describe features of a particular 9-series model */ |
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struct rs9_chip_info { |
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const enum rs9_model model; |
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unsigned int num_clks; |
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}; |
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struct rs9_driver_data { |
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struct i2c_client *client; |
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struct regmap *regmap; |
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const struct rs9_chip_info *chip_info; |
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struct clk *pin_xin; |
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struct clk_hw *clk_dif[2]; |
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u8 pll_amplitude; |
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u8 pll_ssc; |
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u8 clk_dif_sr; |
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}; |
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/* |
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* Renesas 9-series i2c regmap |
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*/ |
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static const struct regmap_range rs9_readable_ranges[] = { |
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regmap_reg_range(RS9_REG_OE, RS9_REG_REF), |
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regmap_reg_range(RS9_REG_VID, RS9_REG_BCP), |
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}; |
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static const struct regmap_access_table rs9_readable_table = { |
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.yes_ranges = rs9_readable_ranges, |
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.n_yes_ranges = ARRAY_SIZE(rs9_readable_ranges), |
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}; |
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static const struct regmap_range rs9_writeable_ranges[] = { |
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regmap_reg_range(RS9_REG_OE, RS9_REG_REF), |
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regmap_reg_range(RS9_REG_BCP, RS9_REG_BCP), |
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}; |
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static const struct regmap_access_table rs9_writeable_table = { |
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.yes_ranges = rs9_writeable_ranges, |
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.n_yes_ranges = ARRAY_SIZE(rs9_writeable_ranges), |
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}; |
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static const struct regmap_config rs9_regmap_config = { |
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.reg_bits = 8, |
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.val_bits = 8, |
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.cache_type = REGCACHE_FLAT, |
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.max_register = 0x8, |
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.rd_table = &rs9_readable_table, |
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.wr_table = &rs9_writeable_table, |
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}; |
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static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx) |
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{ |
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struct i2c_client *client = rs9->client; |
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unsigned char name[5] = "DIF0"; |
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struct device_node *np; |
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int ret; |
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u32 sr; |
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/* Set defaults */ |
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rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx); |
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rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx); |
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snprintf(name, 5, "DIF%d", idx); |
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np = of_get_child_by_name(client->dev.of_node, name); |
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if (!np) |
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return 0; |
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/* Output clock slew rate */ |
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ret = of_property_read_u32(np, "renesas,slew-rate", &sr); |
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of_node_put(np); |
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if (!ret) { |
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if (sr == 2000000) { /* 2V/ns */ |
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rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx); |
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rs9->clk_dif_sr |= RS9_REG_SR_2V0_DIF(idx); |
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} else if (sr == 3000000) { /* 3V/ns (default) */ |
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rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx); |
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rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx); |
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} else |
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ret = dev_err_probe(&client->dev, -EINVAL, |
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"Invalid renesas,slew-rate value\n"); |
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} |
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return ret; |
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} |
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static int rs9_get_common_config(struct rs9_driver_data *rs9) |
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{ |
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struct i2c_client *client = rs9->client; |
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struct device_node *np = client->dev.of_node; |
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unsigned int amp, ssc; |
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int ret; |
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/* Set defaults */ |
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rs9->pll_amplitude = RS9_REG_SS_AMP_0V7; |
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rs9->pll_ssc = RS9_REG_SS_SSC_100; |
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/* Output clock amplitude */ |
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ret = of_property_read_u32(np, "renesas,out-amplitude-microvolt", |
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&); |
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if (!ret) { |
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if (amp == 600000) /* 0.6V */ |
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rs9->pll_amplitude = RS9_REG_SS_AMP_0V6; |
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else if (amp == 700000) /* 0.7V (default) */ |
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rs9->pll_amplitude = RS9_REG_SS_AMP_0V7; |
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else if (amp == 800000) /* 0.8V */ |
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rs9->pll_amplitude = RS9_REG_SS_AMP_0V8; |
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else if (amp == 900000) /* 0.9V */ |
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rs9->pll_amplitude = RS9_REG_SS_AMP_0V9; |
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else |
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return dev_err_probe(&client->dev, -EINVAL, |
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"Invalid renesas,out-amplitude-microvolt value\n"); |
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} |
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/* Output clock spread spectrum */ |
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ret = of_property_read_u32(np, "renesas,out-spread-spectrum", &ssc); |
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if (!ret) { |
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if (ssc == 100000) /* 100% ... no spread (default) */ |
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rs9->pll_ssc = RS9_REG_SS_SSC_100; |
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else if (ssc == 99750) /* -0.25% ... down spread */ |
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rs9->pll_ssc = RS9_REG_SS_SSC_M025; |
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else if (ssc == 99500) /* -0.50% ... down spread */ |
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rs9->pll_ssc = RS9_REG_SS_SSC_M050; |
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else |
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return dev_err_probe(&client->dev, -EINVAL, |
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"Invalid renesas,out-spread-spectrum value\n"); |
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} |
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return 0; |
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} |
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static void rs9_update_config(struct rs9_driver_data *rs9) |
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{ |
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int i; |
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/* If amplitude is non-default, update it. */ |
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if (rs9->pll_amplitude != RS9_REG_SS_AMP_0V7) { |
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regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_AMP_MASK, |
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rs9->pll_amplitude); |
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} |
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/* If SSC is non-default, update it. */ |
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if (rs9->pll_ssc != RS9_REG_SS_SSC_100) { |
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regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_SSC_MASK, |
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rs9->pll_ssc); |
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} |
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for (i = 0; i < rs9->chip_info->num_clks; i++) { |
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if (rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i)) |
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continue; |
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regmap_update_bits(rs9->regmap, RS9_REG_SR, RS9_REG_SR_3V0_DIF(i), |
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rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i)); |
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} |
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} |
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static struct clk_hw * |
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rs9_of_clk_get(struct of_phandle_args *clkspec, void *data) |
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{ |
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struct rs9_driver_data *rs9 = data; |
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unsigned int idx = clkspec->args[0]; |
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return rs9->clk_dif[idx]; |
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} |
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static int rs9_probe(struct i2c_client *client) |
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{ |
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unsigned char name[5] = "DIF0"; |
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struct rs9_driver_data *rs9; |
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struct clk_hw *hw; |
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int i, ret; |
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rs9 = devm_kzalloc(&client->dev, sizeof(*rs9), GFP_KERNEL); |
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if (!rs9) |
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return -ENOMEM; |
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i2c_set_clientdata(client, rs9); |
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rs9->client = client; |
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rs9->chip_info = device_get_match_data(&client->dev); |
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if (!rs9->chip_info) |
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return -EINVAL; |
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/* Fetch common configuration from DT (if specified) */ |
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ret = rs9_get_common_config(rs9); |
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if (ret) |
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return ret; |
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/* Fetch DIFx output configuration from DT (if specified) */ |
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for (i = 0; i < rs9->chip_info->num_clks; i++) { |
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ret = rs9_get_output_config(rs9, i); |
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if (ret) |
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return ret; |
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} |
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rs9->regmap = devm_regmap_init_i2c(client, &rs9_regmap_config); |
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if (IS_ERR(rs9->regmap)) |
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return dev_err_probe(&client->dev, PTR_ERR(rs9->regmap), |
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"Failed to allocate register map\n"); |
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/* Register clock */ |
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for (i = 0; i < rs9->chip_info->num_clks; i++) { |
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snprintf(name, 5, "DIF%d", i); |
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hw = devm_clk_hw_register_fixed_factor_index(&client->dev, name, |
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0, 0, 4, 1); |
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if (IS_ERR(hw)) |
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return PTR_ERR(hw); |
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rs9->clk_dif[i] = hw; |
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} |
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ret = devm_of_clk_add_hw_provider(&client->dev, rs9_of_clk_get, rs9); |
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if (!ret) |
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rs9_update_config(rs9); |
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return ret; |
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} |
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static int __maybe_unused rs9_suspend(struct device *dev) |
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{ |
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struct rs9_driver_data *rs9 = dev_get_drvdata(dev); |
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regcache_cache_only(rs9->regmap, true); |
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regcache_mark_dirty(rs9->regmap); |
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return 0; |
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} |
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static int __maybe_unused rs9_resume(struct device *dev) |
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{ |
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struct rs9_driver_data *rs9 = dev_get_drvdata(dev); |
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int ret; |
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regcache_cache_only(rs9->regmap, false); |
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ret = regcache_sync(rs9->regmap); |
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if (ret) |
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dev_err(dev, "Failed to restore register map: %d\n", ret); |
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return ret; |
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} |
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static const struct rs9_chip_info renesas_9fgv0241_info = { |
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.model = RENESAS_9FGV0241, |
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.num_clks = 2, |
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}; |
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static const struct i2c_device_id rs9_id[] = { |
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{ "9fgv0241", .driver_data = RENESAS_9FGV0241 }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(i2c, rs9_id); |
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static const struct of_device_id clk_rs9_of_match[] = { |
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{ .compatible = "renesas,9fgv0241", .data = &renesas_9fgv0241_info }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, clk_rs9_of_match); |
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static SIMPLE_DEV_PM_OPS(rs9_pm_ops, rs9_suspend, rs9_resume); |
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static struct i2c_driver rs9_driver = { |
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.driver = { |
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.name = "clk-renesas-pcie-9series", |
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.pm = &rs9_pm_ops, |
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.of_match_table = clk_rs9_of_match, |
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}, |
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.probe_new = rs9_probe, |
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.id_table = rs9_id, |
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}; |
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module_i2c_driver(rs9_driver); |
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MODULE_AUTHOR("Marek Vasut <[email protected]>"); |
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MODULE_DESCRIPTION("Renesas 9-series PCIe clock generator driver"); |
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MODULE_LICENSE("GPL");
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