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548 lines
16 KiB
548 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Nuvoton NPCM7xx Clock Generator |
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* All the clocks are initialized by the bootloader, so this driver allow only |
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* reading of current settings directly from the hardware. |
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* |
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* Copyright (C) 2018 Nuvoton Technologies [email protected] |
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*/ |
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#include <linux/module.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/slab.h> |
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#include <linux/err.h> |
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#include <linux/bitfield.h> |
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#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> |
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struct npcm7xx_clk_pll { |
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struct clk_hw hw; |
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void __iomem *pllcon; |
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u8 flags; |
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}; |
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#define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw) |
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#define PLLCON_LOKI BIT(31) |
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#define PLLCON_LOKS BIT(30) |
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#define PLLCON_FBDV GENMASK(27, 16) |
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#define PLLCON_OTDV2 GENMASK(15, 13) |
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#define PLLCON_PWDEN BIT(12) |
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#define PLLCON_OTDV1 GENMASK(10, 8) |
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#define PLLCON_INDV GENMASK(5, 0) |
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static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw); |
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unsigned long fbdv, indv, otdv1, otdv2; |
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unsigned int val; |
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u64 ret; |
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if (parent_rate == 0) { |
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pr_err("%s: parent rate is zero", __func__); |
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return 0; |
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} |
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val = readl_relaxed(pll->pllcon); |
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indv = FIELD_GET(PLLCON_INDV, val); |
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fbdv = FIELD_GET(PLLCON_FBDV, val); |
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otdv1 = FIELD_GET(PLLCON_OTDV1, val); |
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otdv2 = FIELD_GET(PLLCON_OTDV2, val); |
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ret = (u64)parent_rate * fbdv; |
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do_div(ret, indv * otdv1 * otdv2); |
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return ret; |
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} |
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static const struct clk_ops npcm7xx_clk_pll_ops = { |
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.recalc_rate = npcm7xx_clk_pll_recalc_rate, |
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}; |
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static struct clk_hw * |
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npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name, |
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const char *parent_name, unsigned long flags) |
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{ |
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struct npcm7xx_clk_pll *pll; |
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struct clk_init_data init; |
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struct clk_hw *hw; |
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int ret; |
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pll = kzalloc(sizeof(*pll), GFP_KERNEL); |
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if (!pll) |
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return ERR_PTR(-ENOMEM); |
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pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name); |
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init.name = name; |
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init.ops = &npcm7xx_clk_pll_ops; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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init.flags = flags; |
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pll->pllcon = pllcon; |
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pll->hw.init = &init; |
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hw = &pll->hw; |
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ret = clk_hw_register(NULL, hw); |
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if (ret) { |
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kfree(pll); |
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hw = ERR_PTR(ret); |
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} |
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return hw; |
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} |
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#define NPCM7XX_CLKEN1 (0x00) |
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#define NPCM7XX_CLKEN2 (0x28) |
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#define NPCM7XX_CLKEN3 (0x30) |
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#define NPCM7XX_CLKSEL (0x04) |
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#define NPCM7XX_CLKDIV1 (0x08) |
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#define NPCM7XX_CLKDIV2 (0x2C) |
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#define NPCM7XX_CLKDIV3 (0x58) |
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#define NPCM7XX_PLLCON0 (0x0C) |
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#define NPCM7XX_PLLCON1 (0x10) |
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#define NPCM7XX_PLLCON2 (0x54) |
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#define NPCM7XX_SWRSTR (0x14) |
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#define NPCM7XX_IRQWAKECON (0x18) |
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#define NPCM7XX_IRQWAKEFLAG (0x1C) |
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#define NPCM7XX_IPSRST1 (0x20) |
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#define NPCM7XX_IPSRST2 (0x24) |
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#define NPCM7XX_IPSRST3 (0x34) |
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#define NPCM7XX_WD0RCR (0x38) |
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#define NPCM7XX_WD1RCR (0x3C) |
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#define NPCM7XX_WD2RCR (0x40) |
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#define NPCM7XX_SWRSTC1 (0x44) |
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#define NPCM7XX_SWRSTC2 (0x48) |
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#define NPCM7XX_SWRSTC3 (0x4C) |
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#define NPCM7XX_SWRSTC4 (0x50) |
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#define NPCM7XX_CORSTC (0x5C) |
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#define NPCM7XX_PLLCONG (0x60) |
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#define NPCM7XX_AHBCKFI (0x64) |
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#define NPCM7XX_SECCNT (0x68) |
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#define NPCM7XX_CNTR25M (0x6C) |
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struct npcm7xx_clk_gate_data { |
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u32 reg; |
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u8 bit_idx; |
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const char *name; |
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const char *parent_name; |
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unsigned long flags; |
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/* |
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* If this clock is exported via DT, set onecell_idx to constant |
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* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for |
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* this specific clock. Otherwise, set to -1. |
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*/ |
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int onecell_idx; |
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}; |
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struct npcm7xx_clk_mux_data { |
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u8 shift; |
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u8 mask; |
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u32 *table; |
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const char *name; |
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const char * const *parent_names; |
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u8 num_parents; |
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unsigned long flags; |
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/* |
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* If this clock is exported via DT, set onecell_idx to constant |
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* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for |
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* this specific clock. Otherwise, set to -1. |
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*/ |
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int onecell_idx; |
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}; |
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struct npcm7xx_clk_div_fixed_data { |
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u8 mult; |
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u8 div; |
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const char *name; |
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const char *parent_name; |
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u8 clk_divider_flags; |
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/* |
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* If this clock is exported via DT, set onecell_idx to constant |
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* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for |
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* this specific clock. Otherwise, set to -1. |
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*/ |
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int onecell_idx; |
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}; |
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struct npcm7xx_clk_div_data { |
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u32 reg; |
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u8 shift; |
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u8 width; |
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const char *name; |
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const char *parent_name; |
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u8 clk_divider_flags; |
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unsigned long flags; |
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/* |
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* If this clock is exported via DT, set onecell_idx to constant |
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* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for |
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* this specific clock. Otherwise, set to -1. |
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*/ |
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int onecell_idx; |
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}; |
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struct npcm7xx_clk_pll_data { |
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u32 reg; |
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const char *name; |
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const char *parent_name; |
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unsigned long flags; |
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/* |
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* If this clock is exported via DT, set onecell_idx to constant |
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* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for |
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* this specific clock. Otherwise, set to -1. |
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*/ |
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int onecell_idx; |
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}; |
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/* |
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* Single copy of strings used to refer to clocks within this driver indexed by |
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* above enum. |
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*/ |
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#define NPCM7XX_CLK_S_REFCLK "refclk" |
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#define NPCM7XX_CLK_S_SYSBYPCK "sysbypck" |
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#define NPCM7XX_CLK_S_MCBYPCK "mcbypck" |
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#define NPCM7XX_CLK_S_GFXBYPCK "gfxbypck" |
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#define NPCM7XX_CLK_S_PLL0 "pll0" |
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#define NPCM7XX_CLK_S_PLL1 "pll1" |
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#define NPCM7XX_CLK_S_PLL1_DIV2 "pll1_div2" |
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#define NPCM7XX_CLK_S_PLL2 "pll2" |
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#define NPCM7XX_CLK_S_PLL_GFX "pll_gfx" |
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#define NPCM7XX_CLK_S_PLL2_DIV2 "pll2_div2" |
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#define NPCM7XX_CLK_S_PIX_MUX "gfx_pixel" |
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#define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux" |
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#define NPCM7XX_CLK_S_MC_MUX "mc_phy" |
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#define NPCM7XX_CLK_S_CPU_MUX "cpu" /*AKA system clock.*/ |
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#define NPCM7XX_CLK_S_MC "mc" |
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#define NPCM7XX_CLK_S_AXI "axi" /*AKA CLK2*/ |
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#define NPCM7XX_CLK_S_AHB "ahb" /*AKA CLK4*/ |
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#define NPCM7XX_CLK_S_CLKOUT_MUX "clkout_mux" |
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#define NPCM7XX_CLK_S_UART_MUX "uart_mux" |
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#define NPCM7XX_CLK_S_TIM_MUX "timer_mux" |
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#define NPCM7XX_CLK_S_SD_MUX "sd_mux" |
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#define NPCM7XX_CLK_S_GFXM_MUX "gfxm_mux" |
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#define NPCM7XX_CLK_S_SU_MUX "serial_usb_mux" |
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#define NPCM7XX_CLK_S_DVC_MUX "dvc_mux" |
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#define NPCM7XX_CLK_S_GFX_MUX "gfx_mux" |
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#define NPCM7XX_CLK_S_GFX_PIXEL "gfx_pixel" |
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#define NPCM7XX_CLK_S_SPI0 "spi0" |
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#define NPCM7XX_CLK_S_SPI3 "spi3" |
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#define NPCM7XX_CLK_S_SPIX "spix" |
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#define NPCM7XX_CLK_S_APB1 "apb1" |
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#define NPCM7XX_CLK_S_APB2 "apb2" |
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#define NPCM7XX_CLK_S_APB3 "apb3" |
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#define NPCM7XX_CLK_S_APB4 "apb4" |
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#define NPCM7XX_CLK_S_APB5 "apb5" |
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#define NPCM7XX_CLK_S_TOCK "tock" |
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#define NPCM7XX_CLK_S_CLKOUT "clkout" |
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#define NPCM7XX_CLK_S_UART "uart" |
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#define NPCM7XX_CLK_S_TIMER "timer" |
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#define NPCM7XX_CLK_S_MMC "mmc" |
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#define NPCM7XX_CLK_S_SDHC "sdhc" |
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#define NPCM7XX_CLK_S_ADC "adc" |
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#define NPCM7XX_CLK_S_GFX "gfx0_gfx1_mem" |
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#define NPCM7XX_CLK_S_USBIF "serial_usbif" |
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#define NPCM7XX_CLK_S_USB_HOST "usb_host" |
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#define NPCM7XX_CLK_S_USB_BRIDGE "usb_bridge" |
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#define NPCM7XX_CLK_S_PCI "pci" |
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static u32 pll_mux_table[] = {0, 1, 2, 3}; |
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static const char * const pll_mux_parents[] __initconst = { |
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NPCM7XX_CLK_S_PLL0, |
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NPCM7XX_CLK_S_PLL1_DIV2, |
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NPCM7XX_CLK_S_REFCLK, |
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NPCM7XX_CLK_S_PLL2_DIV2, |
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}; |
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static u32 cpuck_mux_table[] = {0, 1, 2, 3}; |
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static const char * const cpuck_mux_parents[] __initconst = { |
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NPCM7XX_CLK_S_PLL0, |
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NPCM7XX_CLK_S_PLL1_DIV2, |
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NPCM7XX_CLK_S_REFCLK, |
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NPCM7XX_CLK_S_SYSBYPCK, |
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}; |
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static u32 pixcksel_mux_table[] = {0, 2}; |
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static const char * const pixcksel_mux_parents[] __initconst = { |
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NPCM7XX_CLK_S_PLL_GFX, |
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NPCM7XX_CLK_S_REFCLK, |
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}; |
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static u32 sucksel_mux_table[] = {2, 3}; |
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static const char * const sucksel_mux_parents[] __initconst = { |
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NPCM7XX_CLK_S_REFCLK, |
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NPCM7XX_CLK_S_PLL2_DIV2, |
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}; |
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static u32 mccksel_mux_table[] = {0, 2, 3}; |
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static const char * const mccksel_mux_parents[] __initconst = { |
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NPCM7XX_CLK_S_PLL1_DIV2, |
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NPCM7XX_CLK_S_REFCLK, |
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NPCM7XX_CLK_S_MCBYPCK, |
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}; |
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static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4}; |
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static const char * const clkoutsel_mux_parents[] __initconst = { |
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NPCM7XX_CLK_S_PLL0, |
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NPCM7XX_CLK_S_PLL1_DIV2, |
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NPCM7XX_CLK_S_REFCLK, |
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NPCM7XX_CLK_S_PLL_GFX, // divided by 2 |
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NPCM7XX_CLK_S_PLL2_DIV2, |
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}; |
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static u32 gfxmsel_mux_table[] = {2, 3}; |
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static const char * const gfxmsel_mux_parents[] __initconst = { |
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NPCM7XX_CLK_S_REFCLK, |
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NPCM7XX_CLK_S_PLL2_DIV2, |
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}; |
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static u32 dvcssel_mux_table[] = {2, 3}; |
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static const char * const dvcssel_mux_parents[] __initconst = { |
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NPCM7XX_CLK_S_REFCLK, |
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NPCM7XX_CLK_S_PLL2, |
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}; |
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static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = { |
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{NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1}, |
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{NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1, |
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NPCM7XX_CLK_S_REFCLK, 0, -1}, |
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{NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2, |
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NPCM7XX_CLK_S_REFCLK, 0, -1}, |
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{NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX, |
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NPCM7XX_CLK_S_REFCLK, 0, -1}, |
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}; |
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static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = { |
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{0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX, |
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cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL, |
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NPCM7XX_CLK_CPU}, |
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{4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX, |
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pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0, |
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NPCM7XX_CLK_GFX_PIXEL}, |
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{6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX, |
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pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, |
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{8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX, |
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pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, |
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{10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX, |
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sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1}, |
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{12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX, |
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mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1}, |
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{14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX, |
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pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, |
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{16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX, |
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pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, |
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{18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX, |
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clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1}, |
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{21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX, |
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gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1}, |
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{23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX, |
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dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1}, |
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}; |
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/* configurable dividers: */ |
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static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = { |
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{NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC, |
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NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC}, |
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/*30-28 ADCCKDIV*/ |
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{NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB, |
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NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB}, |
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/*27-26 CLK4DIV*/ |
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{NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER, |
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NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER}, |
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/*25-21 TIMCKDIV*/ |
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{NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART, |
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NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART}, |
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/*20-16 UARTDIV*/ |
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{NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC, |
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NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC}, |
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/*15-11 MMCCKDIV*/ |
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{NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3, |
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NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3}, |
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/*10-6 AHB3CKDIV*/ |
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{NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI, |
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NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI}, |
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/*5-2 PCICKDIV*/ |
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{NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI, |
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NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL, |
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NPCM7XX_CLK_AXI},/*0 CLK2DIV*/ |
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{NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4, |
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NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4}, |
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/*31-30 APB4CKDIV*/ |
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{NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3, |
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NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3}, |
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/*29-28 APB3CKDIV*/ |
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{NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2, |
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NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2}, |
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/*27-26 APB2CKDIV*/ |
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{NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1, |
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NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1}, |
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/*25-24 APB1CKDIV*/ |
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{NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5, |
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NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5}, |
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/*23-22 APB5CKDIV*/ |
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{NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT, |
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NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT}, |
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/*20-16 CLKOUTDIV*/ |
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{NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX, |
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NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX}, |
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/*15-13 GFXCKDIV*/ |
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{NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE, |
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NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU}, |
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/*12-8 SUCKDIV*/ |
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{NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST, |
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NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48}, |
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/*7-4 SU48CKDIV*/ |
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{NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC, |
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NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC} |
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,/*3-0 SD1CKDIV*/ |
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{NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0, |
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NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0}, |
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/*10-6 SPI0CKDV*/ |
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{NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX, |
|
NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX}, |
|
/*5-1 SPIXCKDV*/ |
|
|
|
}; |
|
|
|
static DEFINE_SPINLOCK(npcm7xx_clk_lock); |
|
|
|
static void __init npcm7xx_clk_init(struct device_node *clk_np) |
|
{ |
|
struct clk_hw_onecell_data *npcm7xx_clk_data; |
|
void __iomem *clk_base; |
|
struct resource res; |
|
struct clk_hw *hw; |
|
int ret; |
|
int i; |
|
|
|
ret = of_address_to_resource(clk_np, 0, &res); |
|
if (ret) { |
|
pr_err("%pOFn: failed to get resource, ret %d\n", clk_np, |
|
ret); |
|
return; |
|
} |
|
|
|
clk_base = ioremap(res.start, resource_size(&res)); |
|
if (!clk_base) |
|
goto npcm7xx_init_error; |
|
|
|
npcm7xx_clk_data = kzalloc(struct_size(npcm7xx_clk_data, hws, |
|
NPCM7XX_NUM_CLOCKS), GFP_KERNEL); |
|
if (!npcm7xx_clk_data) |
|
goto npcm7xx_init_np_err; |
|
|
|
npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS; |
|
|
|
for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++) |
|
npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); |
|
|
|
/* Register plls */ |
|
for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) { |
|
const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i]; |
|
|
|
hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg, |
|
pll_data->name, pll_data->parent_name, pll_data->flags); |
|
if (IS_ERR(hw)) { |
|
pr_err("npcm7xx_clk: Can't register pll\n"); |
|
goto npcm7xx_init_fail; |
|
} |
|
|
|
if (pll_data->onecell_idx >= 0) |
|
npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw; |
|
} |
|
|
|
/* Register fixed dividers */ |
|
hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2, |
|
NPCM7XX_CLK_S_PLL1, 0, 1, 2); |
|
if (IS_ERR(hw)) { |
|
pr_err("npcm7xx_clk: Can't register fixed div\n"); |
|
goto npcm7xx_init_fail; |
|
} |
|
|
|
hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2, |
|
NPCM7XX_CLK_S_PLL2, 0, 1, 2); |
|
if (IS_ERR(hw)) { |
|
pr_err("npcm7xx_clk: Can't register div2\n"); |
|
goto npcm7xx_init_fail; |
|
} |
|
|
|
/* Register muxes */ |
|
for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) { |
|
const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i]; |
|
|
|
hw = clk_hw_register_mux_table(NULL, |
|
mux_data->name, |
|
mux_data->parent_names, mux_data->num_parents, |
|
mux_data->flags, clk_base + NPCM7XX_CLKSEL, |
|
mux_data->shift, mux_data->mask, 0, |
|
mux_data->table, &npcm7xx_clk_lock); |
|
|
|
if (IS_ERR(hw)) { |
|
pr_err("npcm7xx_clk: Can't register mux\n"); |
|
goto npcm7xx_init_fail; |
|
} |
|
|
|
if (mux_data->onecell_idx >= 0) |
|
npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw; |
|
} |
|
|
|
/* Register clock dividers specified in npcm7xx_divs */ |
|
for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) { |
|
const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i]; |
|
|
|
hw = clk_hw_register_divider(NULL, div_data->name, |
|
div_data->parent_name, |
|
div_data->flags, |
|
clk_base + div_data->reg, |
|
div_data->shift, div_data->width, |
|
div_data->clk_divider_flags, &npcm7xx_clk_lock); |
|
if (IS_ERR(hw)) { |
|
pr_err("npcm7xx_clk: Can't register div table\n"); |
|
goto npcm7xx_init_fail; |
|
} |
|
|
|
if (div_data->onecell_idx >= 0) |
|
npcm7xx_clk_data->hws[div_data->onecell_idx] = hw; |
|
} |
|
|
|
ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, |
|
npcm7xx_clk_data); |
|
if (ret) |
|
pr_err("failed to add DT provider: %d\n", ret); |
|
|
|
of_node_put(clk_np); |
|
|
|
return; |
|
|
|
npcm7xx_init_fail: |
|
kfree(npcm7xx_clk_data->hws); |
|
npcm7xx_init_np_err: |
|
iounmap(clk_base); |
|
npcm7xx_init_error: |
|
of_node_put(clk_np); |
|
} |
|
CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init);
|
|
|