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673 lines
17 KiB
673 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Tegra30 SoC Thermal Sensor driver |
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* |
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* Based on downstream HWMON driver from NVIDIA. |
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* Copyright (C) 2011 NVIDIA Corporation |
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* |
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* Author: Dmitry Osipenko <[email protected]> |
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* Copyright (C) 2021 GRATE-DRIVER project |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/errno.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/math.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm.h> |
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#include <linux/reset.h> |
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#include <linux/slab.h> |
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#include <linux/thermal.h> |
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#include <linux/types.h> |
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#include <soc/tegra/fuse.h> |
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#include "../thermal_core.h" |
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#include "../thermal_hwmon.h" |
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#define TSENSOR_SENSOR0_CONFIG0 0x0 |
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#define TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP BIT(0) |
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#define TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN BIT(1) |
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#define TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN BIT(2) |
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#define TSENSOR_SENSOR0_CONFIG0_DVFS_EN BIT(3) |
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#define TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN BIT(4) |
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#define TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN BIT(5) |
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#define TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN BIT(6) |
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#define TSENSOR_SENSOR0_CONFIG0_M GENMASK(23, 8) |
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#define TSENSOR_SENSOR0_CONFIG0_N GENMASK(31, 24) |
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#define TSENSOR_SENSOR0_CONFIG1 0x8 |
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#define TSENSOR_SENSOR0_CONFIG1_TH1 GENMASK(15, 0) |
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#define TSENSOR_SENSOR0_CONFIG1_TH2 GENMASK(31, 16) |
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#define TSENSOR_SENSOR0_CONFIG2 0xc |
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#define TSENSOR_SENSOR0_CONFIG2_TH3 GENMASK(15, 0) |
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#define TSENSOR_SENSOR0_STATUS0 0x18 |
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#define TSENSOR_SENSOR0_STATUS0_STATE GENMASK(2, 0) |
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#define TSENSOR_SENSOR0_STATUS0_INTR BIT(8) |
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#define TSENSOR_SENSOR0_STATUS0_CURRENT_VALID BIT(9) |
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#define TSENSOR_SENSOR0_TS_STATUS1 0x1c |
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#define TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT GENMASK(31, 16) |
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#define TEGRA30_FUSE_TEST_PROG_VER 0x28 |
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#define TEGRA30_FUSE_TSENSOR_CALIB 0x98 |
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#define TEGRA30_FUSE_TSENSOR_CALIB_LOW GENMASK(15, 0) |
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#define TEGRA30_FUSE_TSENSOR_CALIB_HIGH GENMASK(31, 16) |
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#define TEGRA30_FUSE_SPARE_BIT 0x144 |
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struct tegra_tsensor; |
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struct tegra_tsensor_calibration_data { |
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int a, b, m, n, p, r; |
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}; |
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struct tegra_tsensor_channel { |
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void __iomem *regs; |
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unsigned int id; |
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struct tegra_tsensor *ts; |
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struct thermal_zone_device *tzd; |
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}; |
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struct tegra_tsensor { |
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void __iomem *regs; |
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bool swap_channels; |
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struct clk *clk; |
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struct device *dev; |
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struct reset_control *rst; |
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struct tegra_tsensor_channel ch[2]; |
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struct tegra_tsensor_calibration_data calib; |
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}; |
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static int tegra_tsensor_hw_enable(const struct tegra_tsensor *ts) |
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{ |
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u32 val; |
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int err; |
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err = reset_control_assert(ts->rst); |
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if (err) { |
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dev_err(ts->dev, "failed to assert hardware reset: %d\n", err); |
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return err; |
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} |
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err = clk_prepare_enable(ts->clk); |
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if (err) { |
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dev_err(ts->dev, "failed to enable clock: %d\n", err); |
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return err; |
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} |
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fsleep(1000); |
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err = reset_control_deassert(ts->rst); |
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if (err) { |
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dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err); |
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goto disable_clk; |
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} |
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/* |
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* Sensors are enabled after reset by default, but not gauging |
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* until clock counter is programmed. |
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* |
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* M: number of reference clock pulses after which every |
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* temperature / voltage measurement is made |
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* |
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* N: number of reference clock counts for which the counter runs |
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*/ |
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val = FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_M, 12500); |
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val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_N, 255); |
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/* apply the same configuration to both channels */ |
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writel_relaxed(val, ts->regs + 0x40 + TSENSOR_SENSOR0_CONFIG0); |
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writel_relaxed(val, ts->regs + 0x80 + TSENSOR_SENSOR0_CONFIG0); |
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return 0; |
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disable_clk: |
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clk_disable_unprepare(ts->clk); |
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return err; |
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} |
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static int tegra_tsensor_hw_disable(const struct tegra_tsensor *ts) |
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{ |
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int err; |
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err = reset_control_assert(ts->rst); |
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if (err) { |
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dev_err(ts->dev, "failed to assert hardware reset: %d\n", err); |
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return err; |
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} |
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clk_disable_unprepare(ts->clk); |
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return 0; |
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} |
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static void devm_tegra_tsensor_hw_disable(void *data) |
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{ |
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const struct tegra_tsensor *ts = data; |
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tegra_tsensor_hw_disable(ts); |
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} |
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static int tegra_tsensor_get_temp(void *data, int *temp) |
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{ |
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const struct tegra_tsensor_channel *tsc = data; |
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const struct tegra_tsensor *ts = tsc->ts; |
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int err, c1, c2, c3, c4, counter; |
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u32 val; |
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/* |
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* Counter will be invalid if hardware is misprogrammed or not enough |
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* time passed since the time when sensor was enabled. |
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*/ |
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err = readl_relaxed_poll_timeout(tsc->regs + TSENSOR_SENSOR0_STATUS0, val, |
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val & TSENSOR_SENSOR0_STATUS0_CURRENT_VALID, |
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21 * USEC_PER_MSEC, |
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21 * USEC_PER_MSEC * 50); |
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if (err) { |
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dev_err_once(ts->dev, "ch%u: counter invalid\n", tsc->id); |
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return err; |
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} |
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val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_TS_STATUS1); |
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counter = FIELD_GET(TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT, val); |
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/* |
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* This shouldn't happen with a valid counter status, nevertheless |
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* lets verify the value since it's in a separate (from status) |
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* register. |
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*/ |
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if (counter == 0xffff) { |
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dev_err_once(ts->dev, "ch%u: counter overflow\n", tsc->id); |
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return -EINVAL; |
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} |
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/* |
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* temperature = a * counter + b |
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* temperature = m * (temperature ^ 2) + n * temperature + p |
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*/ |
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c1 = DIV_ROUND_CLOSEST(ts->calib.a * counter + ts->calib.b, 1000000); |
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c1 = c1 ?: 1; |
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c2 = DIV_ROUND_CLOSEST(ts->calib.p, c1); |
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c3 = c1 * ts->calib.m; |
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c4 = ts->calib.n; |
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*temp = DIV_ROUND_CLOSEST(c1 * (c2 + c3 + c4), 1000); |
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return 0; |
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} |
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static int tegra_tsensor_temp_to_counter(const struct tegra_tsensor *ts, int temp) |
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{ |
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int c1, c2; |
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c1 = DIV_ROUND_CLOSEST(ts->calib.p - temp * 1000, ts->calib.m); |
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c2 = -ts->calib.r - int_sqrt(ts->calib.r * ts->calib.r - c1); |
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return DIV_ROUND_CLOSEST(c2 * 1000000 - ts->calib.b, ts->calib.a); |
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} |
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static int tegra_tsensor_set_trips(void *data, int low, int high) |
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{ |
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const struct tegra_tsensor_channel *tsc = data; |
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const struct tegra_tsensor *ts = tsc->ts; |
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u32 val; |
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/* |
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* TSENSOR doesn't trigger interrupt on the "low" temperature breach, |
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* hence bail out if high temperature is unspecified. |
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*/ |
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if (high == INT_MAX) |
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return 0; |
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val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1); |
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val &= ~TSENSOR_SENSOR0_CONFIG1_TH1; |
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high = tegra_tsensor_temp_to_counter(ts, high); |
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val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH1, high); |
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writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1); |
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return 0; |
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} |
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static const struct thermal_zone_of_device_ops ops = { |
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.get_temp = tegra_tsensor_get_temp, |
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.set_trips = tegra_tsensor_set_trips, |
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}; |
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static bool |
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tegra_tsensor_handle_channel_interrupt(const struct tegra_tsensor *ts, |
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unsigned int id) |
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{ |
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const struct tegra_tsensor_channel *tsc = &ts->ch[id]; |
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u32 val; |
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val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_STATUS0); |
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writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_STATUS0); |
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if (FIELD_GET(TSENSOR_SENSOR0_STATUS0_STATE, val) == 5) |
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dev_err_ratelimited(ts->dev, "ch%u: counter overflowed\n", id); |
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if (!FIELD_GET(TSENSOR_SENSOR0_STATUS0_INTR, val)) |
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return false; |
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thermal_zone_device_update(tsc->tzd, THERMAL_EVENT_UNSPECIFIED); |
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return true; |
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} |
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static irqreturn_t tegra_tsensor_isr(int irq, void *data) |
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{ |
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const struct tegra_tsensor *ts = data; |
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bool handled = false; |
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unsigned int i; |
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for (i = 0; i < ARRAY_SIZE(ts->ch); i++) |
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handled |= tegra_tsensor_handle_channel_interrupt(ts, i); |
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return handled ? IRQ_HANDLED : IRQ_NONE; |
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} |
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static int tegra_tsensor_disable_hw_channel(const struct tegra_tsensor *ts, |
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unsigned int id) |
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{ |
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const struct tegra_tsensor_channel *tsc = &ts->ch[id]; |
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struct thermal_zone_device *tzd = tsc->tzd; |
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u32 val; |
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int err; |
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if (!tzd) |
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goto stop_channel; |
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err = thermal_zone_device_disable(tzd); |
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if (err) { |
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dev_err(ts->dev, "ch%u: failed to disable zone: %d\n", id, err); |
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return err; |
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} |
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stop_channel: |
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/* stop channel gracefully */ |
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val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0); |
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val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP, 1); |
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writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0); |
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return 0; |
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} |
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static void tegra_tsensor_get_hw_channel_trips(struct thermal_zone_device *tzd, |
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int *hot_trip, int *crit_trip) |
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{ |
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unsigned int i; |
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/* |
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* 90C is the maximal critical temperature of all Tegra30 SoC variants, |
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* use it for the default trip if unspecified in a device-tree. |
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*/ |
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*hot_trip = 85000; |
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*crit_trip = 90000; |
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for (i = 0; i < tzd->trips; i++) { |
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enum thermal_trip_type type; |
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int trip_temp; |
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tzd->ops->get_trip_temp(tzd, i, &trip_temp); |
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tzd->ops->get_trip_type(tzd, i, &type); |
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if (type == THERMAL_TRIP_HOT) |
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*hot_trip = trip_temp; |
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if (type == THERMAL_TRIP_CRITICAL) |
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*crit_trip = trip_temp; |
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} |
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/* clamp hardware trips to the calibration limits */ |
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*hot_trip = clamp(*hot_trip, 25000, 90000); |
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/* |
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* Kernel will perform a normal system shut down if it will |
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* see that critical temperature is breached, hence set the |
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* hardware limit by 5C higher in order to allow system to |
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* shut down gracefully before sending signal to the Power |
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* Management controller. |
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*/ |
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*crit_trip = clamp(*crit_trip + 5000, 25000, 90000); |
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} |
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static int tegra_tsensor_enable_hw_channel(const struct tegra_tsensor *ts, |
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unsigned int id) |
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{ |
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const struct tegra_tsensor_channel *tsc = &ts->ch[id]; |
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struct thermal_zone_device *tzd = tsc->tzd; |
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int err, hot_trip = 0, crit_trip = 0; |
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u32 val; |
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if (!tzd) { |
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val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0); |
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val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP; |
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writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0); |
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return 0; |
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} |
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tegra_tsensor_get_hw_channel_trips(tzd, &hot_trip, &crit_trip); |
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/* prevent potential racing with tegra_tsensor_set_trips() */ |
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mutex_lock(&tzd->lock); |
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dev_info_once(ts->dev, "ch%u: PMC emergency shutdown trip set to %dC\n", |
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id, DIV_ROUND_CLOSEST(crit_trip, 1000)); |
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hot_trip = tegra_tsensor_temp_to_counter(ts, hot_trip); |
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crit_trip = tegra_tsensor_temp_to_counter(ts, crit_trip); |
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/* program LEVEL2 counter threshold */ |
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val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1); |
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val &= ~TSENSOR_SENSOR0_CONFIG1_TH2; |
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val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH2, hot_trip); |
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writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1); |
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/* program LEVEL3 counter threshold */ |
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val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG2); |
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val &= ~TSENSOR_SENSOR0_CONFIG2_TH3; |
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val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG2_TH3, crit_trip); |
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writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG2); |
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/* |
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* Enable sensor, emergency shutdown, interrupts for level 1/2/3 |
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* breaches and counter overflow condition. |
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* |
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* Disable DIV2 throttle for now since we need to figure out how |
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* to integrate it properly with the thermal framework. |
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* |
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* Thermal levels supported by hardware: |
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* |
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* Level 0 = cold |
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* Level 1 = passive cooling (cpufreq DVFS) |
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* Level 2 = passive cooling assisted by hardware (DIV2) |
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* Level 3 = emergency shutdown assisted by hardware (PMC) |
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*/ |
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val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0); |
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val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP; |
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val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_DVFS_EN, 1); |
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val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN, 0); |
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val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN, 1); |
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val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN, 1); |
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val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN, 1); |
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val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN, 1); |
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writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0); |
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mutex_unlock(&tzd->lock); |
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err = thermal_zone_device_enable(tzd); |
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if (err) { |
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dev_err(ts->dev, "ch%u: failed to enable zone: %d\n", id, err); |
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return err; |
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} |
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return 0; |
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} |
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static bool tegra_tsensor_fuse_read_spare(unsigned int spare) |
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{ |
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u32 val = 0; |
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tegra_fuse_readl(TEGRA30_FUSE_SPARE_BIT + spare * 4, &val); |
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return !!val; |
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} |
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static int tegra_tsensor_nvmem_setup(struct tegra_tsensor *ts) |
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{ |
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u32 i, ate_ver = 0, cal = 0, t1_25C = 0, t2_90C = 0; |
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int err, c1_25C, c2_90C; |
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err = tegra_fuse_readl(TEGRA30_FUSE_TEST_PROG_VER, &ate_ver); |
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if (err) { |
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dev_err_probe(ts->dev, err, "failed to get ATE version\n"); |
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return err; |
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} |
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if (ate_ver < 8) { |
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dev_info(ts->dev, "unsupported ATE version: %u\n", ate_ver); |
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return -ENODEV; |
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} |
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/* |
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* We have two TSENSOR channels in a two different spots on SoC. |
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* Second channel provides more accurate data on older SoC versions, |
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* use it as a primary channel. |
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*/ |
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if (ate_ver <= 21) { |
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dev_info_once(ts->dev, |
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"older ATE version detected, channels remapped\n"); |
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ts->swap_channels = true; |
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} |
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err = tegra_fuse_readl(TEGRA30_FUSE_TSENSOR_CALIB, &cal); |
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if (err) { |
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dev_err(ts->dev, "failed to get calibration data: %d\n", err); |
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return err; |
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} |
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/* get calibrated counter values for 25C/90C thresholds */ |
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c1_25C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_LOW, cal); |
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c2_90C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_HIGH, cal); |
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/* and calibrated temperatures corresponding to the counter values */ |
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for (i = 0; i < 7; i++) { |
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t1_25C |= tegra_tsensor_fuse_read_spare(14 + i) << i; |
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t1_25C |= tegra_tsensor_fuse_read_spare(21 + i) << i; |
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t2_90C |= tegra_tsensor_fuse_read_spare(0 + i) << i; |
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t2_90C |= tegra_tsensor_fuse_read_spare(7 + i) << i; |
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} |
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if (c2_90C - c1_25C <= t2_90C - t1_25C) { |
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dev_err(ts->dev, "invalid calibration data: %d %d %u %u\n", |
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c2_90C, c1_25C, t2_90C, t1_25C); |
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return -EINVAL; |
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} |
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/* all calibration coefficients are premultiplied by 1000000 */ |
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ts->calib.a = DIV_ROUND_CLOSEST((t2_90C - t1_25C) * 1000000, |
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(c2_90C - c1_25C)); |
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ts->calib.b = t1_25C * 1000000 - ts->calib.a * c1_25C; |
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if (tegra_sku_info.revision == TEGRA_REVISION_A01) { |
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ts->calib.m = -2775; |
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ts->calib.n = 1338811; |
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ts->calib.p = -7300000; |
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} else { |
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ts->calib.m = -3512; |
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ts->calib.n = 1528943; |
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ts->calib.p = -11100000; |
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} |
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/* except the coefficient of a reduced quadratic equation */ |
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ts->calib.r = DIV_ROUND_CLOSEST(ts->calib.n, ts->calib.m * 2); |
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dev_info_once(ts->dev, |
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"calibration: %d %d %u %u ATE ver: %u SoC rev: %u\n", |
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c2_90C, c1_25C, t2_90C, t1_25C, ate_ver, |
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tegra_sku_info.revision); |
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return 0; |
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} |
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static int tegra_tsensor_register_channel(struct tegra_tsensor *ts, |
|
unsigned int id) |
|
{ |
|
struct tegra_tsensor_channel *tsc = &ts->ch[id]; |
|
unsigned int hw_id = ts->swap_channels ? !id : id; |
|
|
|
tsc->ts = ts; |
|
tsc->id = id; |
|
tsc->regs = ts->regs + 0x40 * (hw_id + 1); |
|
|
|
tsc->tzd = devm_thermal_zone_of_sensor_register(ts->dev, id, tsc, &ops); |
|
if (IS_ERR(tsc->tzd)) { |
|
if (PTR_ERR(tsc->tzd) != -ENODEV) |
|
return dev_err_probe(ts->dev, PTR_ERR(tsc->tzd), |
|
"failed to register thermal zone\n"); |
|
|
|
/* |
|
* It's okay if sensor isn't assigned to any thermal zone |
|
* in a device-tree. |
|
*/ |
|
tsc->tzd = NULL; |
|
return 0; |
|
} |
|
|
|
if (devm_thermal_add_hwmon_sysfs(tsc->tzd)) |
|
dev_warn(ts->dev, "failed to add hwmon sysfs attributes\n"); |
|
|
|
return 0; |
|
} |
|
|
|
static int tegra_tsensor_probe(struct platform_device *pdev) |
|
{ |
|
struct tegra_tsensor *ts; |
|
unsigned int i; |
|
int err, irq; |
|
|
|
ts = devm_kzalloc(&pdev->dev, sizeof(*ts), GFP_KERNEL); |
|
if (!ts) |
|
return -ENOMEM; |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) |
|
return irq; |
|
|
|
ts->dev = &pdev->dev; |
|
platform_set_drvdata(pdev, ts); |
|
|
|
ts->regs = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(ts->regs)) |
|
return PTR_ERR(ts->regs); |
|
|
|
ts->clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(ts->clk)) |
|
return dev_err_probe(&pdev->dev, PTR_ERR(ts->clk), |
|
"failed to get clock\n"); |
|
|
|
ts->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); |
|
if (IS_ERR(ts->rst)) |
|
return dev_err_probe(&pdev->dev, PTR_ERR(ts->rst), |
|
"failed to get reset control\n"); |
|
|
|
err = tegra_tsensor_nvmem_setup(ts); |
|
if (err) |
|
return err; |
|
|
|
err = tegra_tsensor_hw_enable(ts); |
|
if (err) |
|
return err; |
|
|
|
err = devm_add_action_or_reset(&pdev->dev, |
|
devm_tegra_tsensor_hw_disable, |
|
ts); |
|
if (err) |
|
return err; |
|
|
|
for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { |
|
err = tegra_tsensor_register_channel(ts, i); |
|
if (err) |
|
return err; |
|
} |
|
|
|
err = devm_request_threaded_irq(&pdev->dev, irq, NULL, |
|
tegra_tsensor_isr, IRQF_ONESHOT, |
|
"tegra_tsensor", ts); |
|
if (err) |
|
return dev_err_probe(&pdev->dev, err, |
|
"failed to request interrupt\n"); |
|
|
|
for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { |
|
err = tegra_tsensor_enable_hw_channel(ts, i); |
|
if (err) |
|
return err; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused tegra_tsensor_suspend(struct device *dev) |
|
{ |
|
struct tegra_tsensor *ts = dev_get_drvdata(dev); |
|
unsigned int i; |
|
int err; |
|
|
|
for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { |
|
err = tegra_tsensor_disable_hw_channel(ts, i); |
|
if (err) |
|
goto enable_channel; |
|
} |
|
|
|
err = tegra_tsensor_hw_disable(ts); |
|
if (err) |
|
goto enable_channel; |
|
|
|
return 0; |
|
|
|
enable_channel: |
|
while (i--) |
|
tegra_tsensor_enable_hw_channel(ts, i); |
|
|
|
return err; |
|
} |
|
|
|
static int __maybe_unused tegra_tsensor_resume(struct device *dev) |
|
{ |
|
struct tegra_tsensor *ts = dev_get_drvdata(dev); |
|
unsigned int i; |
|
int err; |
|
|
|
err = tegra_tsensor_hw_enable(ts); |
|
if (err) |
|
return err; |
|
|
|
for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { |
|
err = tegra_tsensor_enable_hw_channel(ts, i); |
|
if (err) |
|
return err; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops tegra_tsensor_pm_ops = { |
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_tsensor_suspend, |
|
tegra_tsensor_resume) |
|
}; |
|
|
|
static const struct of_device_id tegra_tsensor_of_match[] = { |
|
{ .compatible = "nvidia,tegra30-tsensor", }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, tegra_tsensor_of_match); |
|
|
|
static struct platform_driver tegra_tsensor_driver = { |
|
.probe = tegra_tsensor_probe, |
|
.driver = { |
|
.name = "tegra30-tsensor", |
|
.of_match_table = tegra_tsensor_of_match, |
|
.pm = &tegra_tsensor_pm_ops, |
|
}, |
|
}; |
|
module_platform_driver(tegra_tsensor_driver); |
|
|
|
MODULE_DESCRIPTION("NVIDIA Tegra30 Thermal Sensor driver"); |
|
MODULE_AUTHOR("Dmitry Osipenko <[email protected]>"); |
|
MODULE_LICENSE("GPL");
|
|
|