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583 lines
15 KiB
583 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* EHRPWM PWM driver |
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* |
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* Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/ |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/pwm.h> |
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#include <linux/io.h> |
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#include <linux/err.h> |
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#include <linux/clk.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/of_device.h> |
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|
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/* EHRPWM registers and bits definitions */ |
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|
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/* Time base module registers */ |
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#define TBCTL 0x00 |
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#define TBPRD 0x0A |
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|
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#define TBCTL_PRDLD_MASK BIT(3) |
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#define TBCTL_PRDLD_SHDW 0 |
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#define TBCTL_PRDLD_IMDT BIT(3) |
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#define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \ |
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BIT(8) | BIT(7)) |
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#define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0)) |
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#define TBCTL_CTRMODE_UP 0 |
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#define TBCTL_CTRMODE_DOWN BIT(0) |
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#define TBCTL_CTRMODE_UPDOWN BIT(1) |
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#define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0)) |
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|
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#define TBCTL_HSPCLKDIV_SHIFT 7 |
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#define TBCTL_CLKDIV_SHIFT 10 |
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|
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#define CLKDIV_MAX 7 |
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#define HSPCLKDIV_MAX 7 |
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#define PERIOD_MAX 0xFFFF |
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|
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/* compare module registers */ |
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#define CMPA 0x12 |
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#define CMPB 0x14 |
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|
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/* Action qualifier module registers */ |
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#define AQCTLA 0x16 |
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#define AQCTLB 0x18 |
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#define AQSFRC 0x1A |
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#define AQCSFRC 0x1C |
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|
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#define AQCTL_CBU_MASK (BIT(9) | BIT(8)) |
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#define AQCTL_CBU_FRCLOW BIT(8) |
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#define AQCTL_CBU_FRCHIGH BIT(9) |
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#define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8)) |
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#define AQCTL_CAU_MASK (BIT(5) | BIT(4)) |
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#define AQCTL_CAU_FRCLOW BIT(4) |
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#define AQCTL_CAU_FRCHIGH BIT(5) |
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#define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4)) |
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#define AQCTL_PRD_MASK (BIT(3) | BIT(2)) |
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#define AQCTL_PRD_FRCLOW BIT(2) |
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#define AQCTL_PRD_FRCHIGH BIT(3) |
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#define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2)) |
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#define AQCTL_ZRO_MASK (BIT(1) | BIT(0)) |
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#define AQCTL_ZRO_FRCLOW BIT(0) |
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#define AQCTL_ZRO_FRCHIGH BIT(1) |
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#define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0)) |
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|
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#define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \ |
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AQCTL_ZRO_FRCHIGH) |
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#define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | \ |
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AQCTL_ZRO_FRCLOW) |
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#define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | \ |
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AQCTL_ZRO_FRCHIGH) |
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#define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \ |
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AQCTL_ZRO_FRCLOW) |
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|
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#define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6)) |
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#define AQSFRC_RLDCSF_ZRO 0 |
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#define AQSFRC_RLDCSF_PRD BIT(6) |
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#define AQSFRC_RLDCSF_ZROPRD BIT(7) |
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#define AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6)) |
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|
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#define AQCSFRC_CSFB_MASK (BIT(3) | BIT(2)) |
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#define AQCSFRC_CSFB_FRCDIS 0 |
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#define AQCSFRC_CSFB_FRCLOW BIT(2) |
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#define AQCSFRC_CSFB_FRCHIGH BIT(3) |
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#define AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2)) |
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#define AQCSFRC_CSFA_MASK (BIT(1) | BIT(0)) |
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#define AQCSFRC_CSFA_FRCDIS 0 |
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#define AQCSFRC_CSFA_FRCLOW BIT(0) |
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#define AQCSFRC_CSFA_FRCHIGH BIT(1) |
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#define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0)) |
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|
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#define NUM_PWM_CHANNEL 2 /* EHRPWM channels */ |
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|
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struct ehrpwm_context { |
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u16 tbctl; |
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u16 tbprd; |
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u16 cmpa; |
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u16 cmpb; |
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u16 aqctla; |
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u16 aqctlb; |
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u16 aqsfrc; |
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u16 aqcsfrc; |
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}; |
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|
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struct ehrpwm_pwm_chip { |
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struct pwm_chip chip; |
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unsigned long clk_rate; |
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void __iomem *mmio_base; |
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unsigned long period_cycles[NUM_PWM_CHANNEL]; |
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enum pwm_polarity polarity[NUM_PWM_CHANNEL]; |
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struct clk *tbclk; |
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struct ehrpwm_context ctx; |
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}; |
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|
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static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip) |
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{ |
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return container_of(chip, struct ehrpwm_pwm_chip, chip); |
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} |
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|
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static inline u16 ehrpwm_read(void __iomem *base, unsigned int offset) |
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{ |
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return readw(base + offset); |
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} |
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|
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static inline void ehrpwm_write(void __iomem *base, unsigned int offset, |
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u16 value) |
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{ |
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writew(value, base + offset); |
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} |
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|
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static void ehrpwm_modify(void __iomem *base, unsigned int offset, u16 mask, |
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u16 value) |
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{ |
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unsigned short val; |
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|
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val = readw(base + offset); |
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val &= ~mask; |
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val |= value & mask; |
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writew(val, base + offset); |
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} |
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|
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/** |
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* set_prescale_div - Set up the prescaler divider function |
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* @rqst_prescaler: prescaler value min |
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* @prescale_div: prescaler value set |
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* @tb_clk_div: Time Base Control prescaler bits |
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*/ |
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static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div, |
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u16 *tb_clk_div) |
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{ |
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unsigned int clkdiv, hspclkdiv; |
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|
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for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) { |
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for (hspclkdiv = 0; hspclkdiv <= HSPCLKDIV_MAX; hspclkdiv++) { |
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/* |
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* calculations for prescaler value : |
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* prescale_div = HSPCLKDIVIDER * CLKDIVIDER. |
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* HSPCLKDIVIDER = 2 ** hspclkdiv |
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* CLKDIVIDER = (1), if clkdiv == 0 *OR* |
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* (2 * clkdiv), if clkdiv != 0 |
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* |
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* Configure prescale_div value such that period |
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* register value is less than 65535. |
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*/ |
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|
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*prescale_div = (1 << clkdiv) * |
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(hspclkdiv ? (hspclkdiv * 2) : 1); |
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if (*prescale_div > rqst_prescaler) { |
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*tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | |
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(hspclkdiv << TBCTL_HSPCLKDIV_SHIFT); |
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return 0; |
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} |
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} |
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} |
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|
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return 1; |
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} |
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static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan) |
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{ |
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u16 aqctl_val, aqctl_mask; |
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unsigned int aqctl_reg; |
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|
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/* |
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* Configure PWM output to HIGH/LOW level on counter |
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* reaches compare register value and LOW/HIGH level |
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* on counter value reaches period register value and |
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* zero value on counter |
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*/ |
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if (chan == 1) { |
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aqctl_reg = AQCTLB; |
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aqctl_mask = AQCTL_CBU_MASK; |
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if (pc->polarity[chan] == PWM_POLARITY_INVERSED) |
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aqctl_val = AQCTL_CHANB_POLINVERSED; |
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else |
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aqctl_val = AQCTL_CHANB_POLNORMAL; |
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} else { |
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aqctl_reg = AQCTLA; |
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aqctl_mask = AQCTL_CAU_MASK; |
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|
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if (pc->polarity[chan] == PWM_POLARITY_INVERSED) |
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aqctl_val = AQCTL_CHANA_POLINVERSED; |
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else |
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aqctl_val = AQCTL_CHANA_POLNORMAL; |
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} |
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aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK; |
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ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val); |
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} |
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|
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/* |
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* period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE |
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* duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE |
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*/ |
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static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
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int duty_ns, int period_ns) |
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{ |
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struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
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u32 period_cycles, duty_cycles; |
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u16 ps_divval, tb_divval; |
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unsigned int i, cmp_reg; |
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unsigned long long c; |
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if (period_ns > NSEC_PER_SEC) |
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return -ERANGE; |
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c = pc->clk_rate; |
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c = c * period_ns; |
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do_div(c, NSEC_PER_SEC); |
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period_cycles = (unsigned long)c; |
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if (period_cycles < 1) { |
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period_cycles = 1; |
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duty_cycles = 1; |
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} else { |
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c = pc->clk_rate; |
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c = c * duty_ns; |
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do_div(c, NSEC_PER_SEC); |
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duty_cycles = (unsigned long)c; |
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} |
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|
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/* |
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* Period values should be same for multiple PWM channels as IP uses |
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* same period register for multiple channels. |
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*/ |
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for (i = 0; i < NUM_PWM_CHANNEL; i++) { |
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if (pc->period_cycles[i] && |
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(pc->period_cycles[i] != period_cycles)) { |
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/* |
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* Allow channel to reconfigure period if no other |
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* channels being configured. |
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*/ |
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if (i == pwm->hwpwm) |
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continue; |
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dev_err(chip->dev, |
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"period value conflicts with channel %u\n", |
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i); |
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return -EINVAL; |
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} |
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} |
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pc->period_cycles[pwm->hwpwm] = period_cycles; |
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|
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/* Configure clock prescaler to support Low frequency PWM wave */ |
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if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval, |
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&tb_divval)) { |
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dev_err(chip->dev, "Unsupported values\n"); |
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return -EINVAL; |
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} |
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pm_runtime_get_sync(chip->dev); |
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|
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/* Update clock prescaler values */ |
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ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval); |
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|
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/* Update period & duty cycle with presacler division */ |
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period_cycles = period_cycles / ps_divval; |
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duty_cycles = duty_cycles / ps_divval; |
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|
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/* Configure shadow loading on Period register */ |
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ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW); |
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|
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ehrpwm_write(pc->mmio_base, TBPRD, period_cycles); |
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|
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/* Configure ehrpwm counter for up-count mode */ |
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ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK, |
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TBCTL_CTRMODE_UP); |
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|
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if (pwm->hwpwm == 1) |
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/* Channel 1 configured with compare B register */ |
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cmp_reg = CMPB; |
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else |
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/* Channel 0 configured with compare A register */ |
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cmp_reg = CMPA; |
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ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles); |
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|
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pm_runtime_put_sync(chip->dev); |
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|
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return 0; |
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} |
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static int ehrpwm_pwm_set_polarity(struct pwm_chip *chip, |
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struct pwm_device *pwm, |
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enum pwm_polarity polarity) |
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{ |
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struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
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|
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/* Configuration of polarity in hardware delayed, do at enable */ |
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pc->polarity[pwm->hwpwm] = polarity; |
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|
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return 0; |
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} |
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|
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static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
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u16 aqcsfrc_val, aqcsfrc_mask; |
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int ret; |
|
|
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/* Leave clock enabled on enabling PWM */ |
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pm_runtime_get_sync(chip->dev); |
|
|
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/* Disabling Action Qualifier on PWM output */ |
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if (pwm->hwpwm) { |
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aqcsfrc_val = AQCSFRC_CSFB_FRCDIS; |
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aqcsfrc_mask = AQCSFRC_CSFB_MASK; |
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} else { |
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aqcsfrc_val = AQCSFRC_CSFA_FRCDIS; |
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aqcsfrc_mask = AQCSFRC_CSFA_MASK; |
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} |
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|
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/* Changes to shadow mode */ |
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ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, |
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AQSFRC_RLDCSF_ZRO); |
|
|
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ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); |
|
|
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/* Channels polarity can be configured from action qualifier module */ |
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configure_polarity(pc, pwm->hwpwm); |
|
|
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/* Enable TBCLK */ |
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ret = clk_enable(pc->tbclk); |
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if (ret) { |
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dev_err(chip->dev, "Failed to enable TBCLK for %s: %d\n", |
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dev_name(pc->chip.dev), ret); |
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return ret; |
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} |
|
|
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return 0; |
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} |
|
|
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static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
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u16 aqcsfrc_val, aqcsfrc_mask; |
|
|
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/* Action Qualifier puts PWM output low forcefully */ |
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if (pwm->hwpwm) { |
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aqcsfrc_val = AQCSFRC_CSFB_FRCLOW; |
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aqcsfrc_mask = AQCSFRC_CSFB_MASK; |
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} else { |
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aqcsfrc_val = AQCSFRC_CSFA_FRCLOW; |
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aqcsfrc_mask = AQCSFRC_CSFA_MASK; |
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} |
|
|
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/* Update shadow register first before modifying active register */ |
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ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, |
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AQSFRC_RLDCSF_ZRO); |
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ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); |
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/* |
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* Changes to immediate action on Action Qualifier. This puts |
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* Action Qualifier control on PWM output from next TBCLK |
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*/ |
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ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, |
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AQSFRC_RLDCSF_IMDT); |
|
|
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ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); |
|
|
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/* Disabling TBCLK on PWM disable */ |
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clk_disable(pc->tbclk); |
|
|
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/* Disable clock on PWM disable */ |
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pm_runtime_put_sync(chip->dev); |
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} |
|
|
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static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
|
|
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if (pwm_is_enabled(pwm)) { |
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dev_warn(chip->dev, "Removing PWM device without disabling\n"); |
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pm_runtime_put_sync(chip->dev); |
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} |
|
|
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/* set period value to zero on free */ |
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pc->period_cycles[pwm->hwpwm] = 0; |
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} |
|
|
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static const struct pwm_ops ehrpwm_pwm_ops = { |
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.free = ehrpwm_pwm_free, |
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.config = ehrpwm_pwm_config, |
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.set_polarity = ehrpwm_pwm_set_polarity, |
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.enable = ehrpwm_pwm_enable, |
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.disable = ehrpwm_pwm_disable, |
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.owner = THIS_MODULE, |
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}; |
|
|
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static const struct of_device_id ehrpwm_of_match[] = { |
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{ .compatible = "ti,am3352-ehrpwm" }, |
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{ .compatible = "ti,am33xx-ehrpwm" }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, ehrpwm_of_match); |
|
|
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static int ehrpwm_pwm_probe(struct platform_device *pdev) |
|
{ |
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struct device_node *np = pdev->dev.of_node; |
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struct ehrpwm_pwm_chip *pc; |
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struct clk *clk; |
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int ret; |
|
|
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pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); |
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if (!pc) |
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return -ENOMEM; |
|
|
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clk = devm_clk_get(&pdev->dev, "fck"); |
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if (IS_ERR(clk)) { |
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if (of_device_is_compatible(np, "ti,am33xx-ecap")) { |
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dev_warn(&pdev->dev, "Binding is obsolete.\n"); |
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clk = devm_clk_get(pdev->dev.parent, "fck"); |
|
} |
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} |
|
|
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if (IS_ERR(clk)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(clk), "Failed to get fck\n"); |
|
|
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pc->clk_rate = clk_get_rate(clk); |
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if (!pc->clk_rate) { |
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dev_err(&pdev->dev, "failed to get clock rate\n"); |
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return -EINVAL; |
|
} |
|
|
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pc->chip.dev = &pdev->dev; |
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pc->chip.ops = &ehrpwm_pwm_ops; |
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pc->chip.npwm = NUM_PWM_CHANNEL; |
|
|
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pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(pc->mmio_base)) |
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return PTR_ERR(pc->mmio_base); |
|
|
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/* Acquire tbclk for Time Base EHRPWM submodule */ |
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pc->tbclk = devm_clk_get(&pdev->dev, "tbclk"); |
|
if (IS_ERR(pc->tbclk)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(pc->tbclk), "Failed to get tbclk\n"); |
|
|
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ret = clk_prepare(pc->tbclk); |
|
if (ret < 0) { |
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dev_err(&pdev->dev, "clk_prepare() failed: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
ret = pwmchip_add(&pc->chip); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); |
|
goto err_clk_unprepare; |
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} |
|
|
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platform_set_drvdata(pdev, pc); |
|
pm_runtime_enable(&pdev->dev); |
|
|
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return 0; |
|
|
|
err_clk_unprepare: |
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clk_unprepare(pc->tbclk); |
|
|
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return ret; |
|
} |
|
|
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static int ehrpwm_pwm_remove(struct platform_device *pdev) |
|
{ |
|
struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev); |
|
|
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pwmchip_remove(&pc->chip); |
|
|
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clk_unprepare(pc->tbclk); |
|
|
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pm_runtime_disable(&pdev->dev); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static void ehrpwm_pwm_save_context(struct ehrpwm_pwm_chip *pc) |
|
{ |
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pm_runtime_get_sync(pc->chip.dev); |
|
|
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pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL); |
|
pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD); |
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pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA); |
|
pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB); |
|
pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA); |
|
pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB); |
|
pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC); |
|
pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC); |
|
|
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pm_runtime_put_sync(pc->chip.dev); |
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} |
|
|
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static void ehrpwm_pwm_restore_context(struct ehrpwm_pwm_chip *pc) |
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{ |
|
ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd); |
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ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa); |
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ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb); |
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ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla); |
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ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb); |
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ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc); |
|
ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc); |
|
ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl); |
|
} |
|
|
|
static int ehrpwm_pwm_suspend(struct device *dev) |
|
{ |
|
struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev); |
|
unsigned int i; |
|
|
|
ehrpwm_pwm_save_context(pc); |
|
|
|
for (i = 0; i < pc->chip.npwm; i++) { |
|
struct pwm_device *pwm = &pc->chip.pwms[i]; |
|
|
|
if (!pwm_is_enabled(pwm)) |
|
continue; |
|
|
|
/* Disable explicitly if PWM is running */ |
|
pm_runtime_put_sync(dev); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int ehrpwm_pwm_resume(struct device *dev) |
|
{ |
|
struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev); |
|
unsigned int i; |
|
|
|
for (i = 0; i < pc->chip.npwm; i++) { |
|
struct pwm_device *pwm = &pc->chip.pwms[i]; |
|
|
|
if (!pwm_is_enabled(pwm)) |
|
continue; |
|
|
|
/* Enable explicitly if PWM was running */ |
|
pm_runtime_get_sync(dev); |
|
} |
|
|
|
ehrpwm_pwm_restore_context(pc); |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
static SIMPLE_DEV_PM_OPS(ehrpwm_pwm_pm_ops, ehrpwm_pwm_suspend, |
|
ehrpwm_pwm_resume); |
|
|
|
static struct platform_driver ehrpwm_pwm_driver = { |
|
.driver = { |
|
.name = "ehrpwm", |
|
.of_match_table = ehrpwm_of_match, |
|
.pm = &ehrpwm_pwm_pm_ops, |
|
}, |
|
.probe = ehrpwm_pwm_probe, |
|
.remove = ehrpwm_pwm_remove, |
|
}; |
|
module_platform_driver(ehrpwm_pwm_driver); |
|
|
|
MODULE_DESCRIPTION("EHRPWM PWM driver"); |
|
MODULE_AUTHOR("Texas Instruments"); |
|
MODULE_LICENSE("GPL");
|
|
|