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408 lines
10 KiB
408 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Intel Vendor Specific Extended Capabilities auxiliary bus driver |
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* |
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* Copyright (c) 2021, Intel Corporation. |
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* All Rights Reserved. |
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* |
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* Author: David E. Box <[email protected]> |
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* |
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* This driver discovers and creates auxiliary devices for Intel defined PCIe |
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* "Vendor Specific" and "Designated Vendor Specific" Extended Capabilities, |
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* VSEC and DVSEC respectively. The driver supports features on specific PCIe |
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* endpoints that exist primarily to expose them. |
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*/ |
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#include <linux/auxiliary_bus.h> |
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#include <linux/bits.h> |
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#include <linux/kernel.h> |
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#include <linux/idr.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/types.h> |
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#include "vsec.h" |
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/* Intel DVSEC offsets */ |
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#define INTEL_DVSEC_ENTRIES 0xA |
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#define INTEL_DVSEC_SIZE 0xB |
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#define INTEL_DVSEC_TABLE 0xC |
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#define INTEL_DVSEC_TABLE_BAR(x) ((x) & GENMASK(2, 0)) |
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#define INTEL_DVSEC_TABLE_OFFSET(x) ((x) & GENMASK(31, 3)) |
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#define TABLE_OFFSET_SHIFT 3 |
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static DEFINE_IDA(intel_vsec_ida); |
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/** |
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* struct intel_vsec_header - Common fields of Intel VSEC and DVSEC registers. |
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* @rev: Revision ID of the VSEC/DVSEC register space |
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* @length: Length of the VSEC/DVSEC register space |
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* @id: ID of the feature |
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* @num_entries: Number of instances of the feature |
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* @entry_size: Size of the discovery table for each feature |
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* @tbir: BAR containing the discovery tables |
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* @offset: BAR offset of start of the first discovery table |
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*/ |
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struct intel_vsec_header { |
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u8 rev; |
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u16 length; |
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u16 id; |
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u8 num_entries; |
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u8 entry_size; |
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u8 tbir; |
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u32 offset; |
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}; |
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/* Platform specific data */ |
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struct intel_vsec_platform_info { |
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struct intel_vsec_header **capabilities; |
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unsigned long quirks; |
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}; |
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enum intel_vsec_id { |
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VSEC_ID_TELEMETRY = 2, |
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VSEC_ID_WATCHER = 3, |
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VSEC_ID_CRASHLOG = 4, |
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}; |
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static enum intel_vsec_id intel_vsec_allow_list[] = { |
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VSEC_ID_TELEMETRY, |
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VSEC_ID_WATCHER, |
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VSEC_ID_CRASHLOG, |
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}; |
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static const char *intel_vsec_name(enum intel_vsec_id id) |
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{ |
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switch (id) { |
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case VSEC_ID_TELEMETRY: |
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return "telemetry"; |
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case VSEC_ID_WATCHER: |
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return "watcher"; |
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case VSEC_ID_CRASHLOG: |
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return "crashlog"; |
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default: |
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return NULL; |
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} |
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} |
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static bool intel_vsec_allowed(u16 id) |
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{ |
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int i; |
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for (i = 0; i < ARRAY_SIZE(intel_vsec_allow_list); i++) |
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if (intel_vsec_allow_list[i] == id) |
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return true; |
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return false; |
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} |
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static bool intel_vsec_disabled(u16 id, unsigned long quirks) |
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{ |
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switch (id) { |
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case VSEC_ID_WATCHER: |
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return !!(quirks & VSEC_QUIRK_NO_WATCHER); |
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case VSEC_ID_CRASHLOG: |
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return !!(quirks & VSEC_QUIRK_NO_CRASHLOG); |
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default: |
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return false; |
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} |
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} |
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static void intel_vsec_remove_aux(void *data) |
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{ |
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auxiliary_device_delete(data); |
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auxiliary_device_uninit(data); |
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} |
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static void intel_vsec_dev_release(struct device *dev) |
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{ |
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struct intel_vsec_device *intel_vsec_dev = dev_to_ivdev(dev); |
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ida_free(intel_vsec_dev->ida, intel_vsec_dev->auxdev.id); |
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kfree(intel_vsec_dev->resource); |
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kfree(intel_vsec_dev); |
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} |
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static int intel_vsec_add_aux(struct pci_dev *pdev, struct intel_vsec_device *intel_vsec_dev, |
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const char *name) |
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{ |
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struct auxiliary_device *auxdev = &intel_vsec_dev->auxdev; |
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int ret; |
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ret = ida_alloc(intel_vsec_dev->ida, GFP_KERNEL); |
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if (ret < 0) { |
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kfree(intel_vsec_dev); |
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return ret; |
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} |
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auxdev->id = ret; |
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auxdev->name = name; |
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auxdev->dev.parent = &pdev->dev; |
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auxdev->dev.release = intel_vsec_dev_release; |
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ret = auxiliary_device_init(auxdev); |
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if (ret < 0) { |
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ida_free(intel_vsec_dev->ida, auxdev->id); |
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kfree(intel_vsec_dev->resource); |
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kfree(intel_vsec_dev); |
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return ret; |
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} |
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ret = auxiliary_device_add(auxdev); |
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if (ret < 0) { |
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auxiliary_device_uninit(auxdev); |
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return ret; |
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} |
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return devm_add_action_or_reset(&pdev->dev, intel_vsec_remove_aux, auxdev); |
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} |
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static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *header, |
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unsigned long quirks) |
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{ |
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struct intel_vsec_device *intel_vsec_dev; |
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struct resource *res, *tmp; |
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int i; |
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if (!intel_vsec_allowed(header->id) || intel_vsec_disabled(header->id, quirks)) |
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return -EINVAL; |
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if (!header->num_entries) { |
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dev_dbg(&pdev->dev, "Invalid 0 entry count for header id %d\n", header->id); |
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return -EINVAL; |
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} |
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if (!header->entry_size) { |
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dev_dbg(&pdev->dev, "Invalid 0 entry size for header id %d\n", header->id); |
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return -EINVAL; |
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} |
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intel_vsec_dev = kzalloc(sizeof(*intel_vsec_dev), GFP_KERNEL); |
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if (!intel_vsec_dev) |
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return -ENOMEM; |
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res = kcalloc(header->num_entries, sizeof(*res), GFP_KERNEL); |
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if (!res) { |
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kfree(intel_vsec_dev); |
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return -ENOMEM; |
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} |
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if (quirks & VSEC_QUIRK_TABLE_SHIFT) |
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header->offset >>= TABLE_OFFSET_SHIFT; |
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/* |
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* The DVSEC/VSEC contains the starting offset and count for a block of |
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* discovery tables. Create a resource array of these tables to the |
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* auxiliary device driver. |
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*/ |
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for (i = 0, tmp = res; i < header->num_entries; i++, tmp++) { |
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tmp->start = pdev->resource[header->tbir].start + |
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header->offset + i * (header->entry_size * sizeof(u32)); |
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tmp->end = tmp->start + (header->entry_size * sizeof(u32)) - 1; |
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tmp->flags = IORESOURCE_MEM; |
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} |
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intel_vsec_dev->pcidev = pdev; |
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intel_vsec_dev->resource = res; |
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intel_vsec_dev->num_resources = header->num_entries; |
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intel_vsec_dev->quirks = quirks; |
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intel_vsec_dev->ida = &intel_vsec_ida; |
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return intel_vsec_add_aux(pdev, intel_vsec_dev, intel_vsec_name(header->id)); |
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} |
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static bool intel_vsec_walk_header(struct pci_dev *pdev, unsigned long quirks, |
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struct intel_vsec_header **header) |
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{ |
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bool have_devices = false; |
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int ret; |
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for ( ; *header; header++) { |
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ret = intel_vsec_add_dev(pdev, *header, quirks); |
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if (ret) |
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dev_info(&pdev->dev, "Could not add device for DVSEC id %d\n", |
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(*header)->id); |
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else |
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have_devices = true; |
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} |
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return have_devices; |
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} |
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static bool intel_vsec_walk_dvsec(struct pci_dev *pdev, unsigned long quirks) |
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{ |
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bool have_devices = false; |
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int pos = 0; |
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do { |
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struct intel_vsec_header header; |
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u32 table, hdr; |
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u16 vid; |
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int ret; |
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pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_DVSEC); |
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if (!pos) |
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break; |
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pci_read_config_dword(pdev, pos + PCI_DVSEC_HEADER1, &hdr); |
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vid = PCI_DVSEC_HEADER1_VID(hdr); |
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if (vid != PCI_VENDOR_ID_INTEL) |
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continue; |
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/* Support only revision 1 */ |
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header.rev = PCI_DVSEC_HEADER1_REV(hdr); |
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if (header.rev != 1) { |
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dev_info(&pdev->dev, "Unsupported DVSEC revision %d\n", header.rev); |
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continue; |
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} |
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header.length = PCI_DVSEC_HEADER1_LEN(hdr); |
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pci_read_config_byte(pdev, pos + INTEL_DVSEC_ENTRIES, &header.num_entries); |
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pci_read_config_byte(pdev, pos + INTEL_DVSEC_SIZE, &header.entry_size); |
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pci_read_config_dword(pdev, pos + INTEL_DVSEC_TABLE, &table); |
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header.tbir = INTEL_DVSEC_TABLE_BAR(table); |
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header.offset = INTEL_DVSEC_TABLE_OFFSET(table); |
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pci_read_config_dword(pdev, pos + PCI_DVSEC_HEADER2, &hdr); |
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header.id = PCI_DVSEC_HEADER2_ID(hdr); |
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ret = intel_vsec_add_dev(pdev, &header, quirks); |
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if (ret) |
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continue; |
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have_devices = true; |
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} while (true); |
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return have_devices; |
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} |
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static bool intel_vsec_walk_vsec(struct pci_dev *pdev, unsigned long quirks) |
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{ |
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bool have_devices = false; |
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int pos = 0; |
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do { |
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struct intel_vsec_header header; |
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u32 table, hdr; |
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int ret; |
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pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_VNDR); |
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if (!pos) |
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break; |
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pci_read_config_dword(pdev, pos + PCI_VNDR_HEADER, &hdr); |
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/* Support only revision 1 */ |
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header.rev = PCI_VNDR_HEADER_REV(hdr); |
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if (header.rev != 1) { |
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dev_info(&pdev->dev, "Unsupported VSEC revision %d\n", header.rev); |
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continue; |
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} |
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header.id = PCI_VNDR_HEADER_ID(hdr); |
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header.length = PCI_VNDR_HEADER_LEN(hdr); |
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/* entry, size, and table offset are the same as DVSEC */ |
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pci_read_config_byte(pdev, pos + INTEL_DVSEC_ENTRIES, &header.num_entries); |
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pci_read_config_byte(pdev, pos + INTEL_DVSEC_SIZE, &header.entry_size); |
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pci_read_config_dword(pdev, pos + INTEL_DVSEC_TABLE, &table); |
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header.tbir = INTEL_DVSEC_TABLE_BAR(table); |
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header.offset = INTEL_DVSEC_TABLE_OFFSET(table); |
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ret = intel_vsec_add_dev(pdev, &header, quirks); |
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if (ret) |
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continue; |
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have_devices = true; |
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} while (true); |
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return have_devices; |
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} |
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static int intel_vsec_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
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{ |
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struct intel_vsec_platform_info *info; |
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bool have_devices = false; |
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unsigned long quirks = 0; |
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int ret; |
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ret = pcim_enable_device(pdev); |
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if (ret) |
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return ret; |
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info = (struct intel_vsec_platform_info *)id->driver_data; |
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if (info) |
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quirks = info->quirks; |
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if (intel_vsec_walk_dvsec(pdev, quirks)) |
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have_devices = true; |
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if (intel_vsec_walk_vsec(pdev, quirks)) |
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have_devices = true; |
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if (info && (info->quirks & VSEC_QUIRK_NO_DVSEC) && |
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intel_vsec_walk_header(pdev, quirks, info->capabilities)) |
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have_devices = true; |
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if (!have_devices) |
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return -ENODEV; |
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return 0; |
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} |
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/* TGL info */ |
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static const struct intel_vsec_platform_info tgl_info = { |
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.quirks = VSEC_QUIRK_NO_WATCHER | VSEC_QUIRK_NO_CRASHLOG | VSEC_QUIRK_TABLE_SHIFT, |
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}; |
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/* DG1 info */ |
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static struct intel_vsec_header dg1_telemetry = { |
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.length = 0x10, |
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.id = 2, |
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.num_entries = 1, |
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.entry_size = 3, |
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.tbir = 0, |
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.offset = 0x466000, |
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}; |
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static struct intel_vsec_header *dg1_capabilities[] = { |
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&dg1_telemetry, |
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NULL |
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}; |
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static const struct intel_vsec_platform_info dg1_info = { |
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.capabilities = dg1_capabilities, |
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.quirks = VSEC_QUIRK_NO_DVSEC, |
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}; |
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#define PCI_DEVICE_ID_INTEL_VSEC_ADL 0x467d |
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#define PCI_DEVICE_ID_INTEL_VSEC_DG1 0x490e |
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#define PCI_DEVICE_ID_INTEL_VSEC_OOBMSM 0x09a7 |
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#define PCI_DEVICE_ID_INTEL_VSEC_TGL 0x9a0d |
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static const struct pci_device_id intel_vsec_pci_ids[] = { |
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{ PCI_DEVICE_DATA(INTEL, VSEC_ADL, &tgl_info) }, |
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{ PCI_DEVICE_DATA(INTEL, VSEC_DG1, &dg1_info) }, |
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{ PCI_DEVICE_DATA(INTEL, VSEC_OOBMSM, NULL) }, |
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{ PCI_DEVICE_DATA(INTEL, VSEC_TGL, &tgl_info) }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(pci, intel_vsec_pci_ids); |
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static struct pci_driver intel_vsec_pci_driver = { |
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.name = "intel_vsec", |
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.id_table = intel_vsec_pci_ids, |
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.probe = intel_vsec_pci_probe, |
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}; |
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module_pci_driver(intel_vsec_pci_driver); |
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MODULE_AUTHOR("David E. Box <[email protected]>"); |
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MODULE_DESCRIPTION("Intel Extended Capabilities auxiliary bus driver"); |
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MODULE_LICENSE("GPL v2");
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