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788 lines
21 KiB
788 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* AMD SoC Power Management Controller Driver |
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* |
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* Copyright (c) 2020, Advanced Micro Devices, Inc. |
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* All Rights Reserved. |
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* |
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* Author: Shyam Sundar S K <[email protected]> |
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*/ |
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|
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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|
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#include <linux/acpi.h> |
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#include <linux/bitfield.h> |
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#include <linux/bits.h> |
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#include <linux/debugfs.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/limits.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_qos.h> |
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#include <linux/rtc.h> |
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#include <linux/suspend.h> |
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#include <linux/seq_file.h> |
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#include <linux/uaccess.h> |
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|
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/* SMU communication registers */ |
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#define AMD_PMC_REGISTER_MESSAGE 0x538 |
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#define AMD_PMC_REGISTER_RESPONSE 0x980 |
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#define AMD_PMC_REGISTER_ARGUMENT 0x9BC |
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|
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/* PMC Scratch Registers */ |
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#define AMD_PMC_SCRATCH_REG_CZN 0x94 |
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#define AMD_PMC_SCRATCH_REG_YC 0xD14 |
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|
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/* STB Registers */ |
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#define AMD_PMC_STB_INDEX_ADDRESS 0xF8 |
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#define AMD_PMC_STB_INDEX_DATA 0xFC |
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#define AMD_PMC_STB_PMI_0 0x03E30600 |
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#define AMD_PMC_STB_PREDEF 0xC6000001 |
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|
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/* Base address of SMU for mapping physical address to virtual address */ |
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#define AMD_PMC_SMU_INDEX_ADDRESS 0xB8 |
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#define AMD_PMC_SMU_INDEX_DATA 0xBC |
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#define AMD_PMC_MAPPING_SIZE 0x01000 |
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#define AMD_PMC_BASE_ADDR_OFFSET 0x10000 |
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#define AMD_PMC_BASE_ADDR_LO 0x13B102E8 |
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#define AMD_PMC_BASE_ADDR_HI 0x13B102EC |
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#define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0) |
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#define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20) |
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|
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/* SMU Response Codes */ |
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#define AMD_PMC_RESULT_OK 0x01 |
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#define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC |
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#define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD |
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#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE |
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#define AMD_PMC_RESULT_FAILED 0xFF |
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|
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/* FCH SSC Registers */ |
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#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30 |
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#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34 |
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#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38 |
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#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C |
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#define FCH_SSC_MAPPING_SIZE 0x800 |
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#define FCH_BASE_PHY_ADDR_LOW 0xFED81100 |
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#define FCH_BASE_PHY_ADDR_HIGH 0x00000000 |
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|
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/* SMU Message Definations */ |
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#define SMU_MSG_GETSMUVERSION 0x02 |
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#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04 |
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#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05 |
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#define SMU_MSG_LOG_START 0x06 |
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#define SMU_MSG_LOG_RESET 0x07 |
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#define SMU_MSG_LOG_DUMP_DATA 0x08 |
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#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09 |
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/* List of supported CPU ids */ |
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#define AMD_CPU_ID_RV 0x15D0 |
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#define AMD_CPU_ID_RN 0x1630 |
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#define AMD_CPU_ID_PCO AMD_CPU_ID_RV |
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#define AMD_CPU_ID_CZN AMD_CPU_ID_RN |
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#define AMD_CPU_ID_YC 0x14B5 |
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|
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#define PMC_MSG_DELAY_MIN_US 50 |
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#define RESPONSE_REGISTER_LOOP_MAX 20000 |
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|
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/* QoS request for letting CPUs in idle states, but not the deepest */ |
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#define AMD_PMC_MAX_IDLE_STATE_LATENCY 3 |
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|
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#define SOC_SUBSYSTEM_IP_MAX 12 |
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#define DELAY_MIN_US 2000 |
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#define DELAY_MAX_US 3000 |
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#define FIFO_SIZE 4096 |
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enum amd_pmc_def { |
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MSG_TEST = 0x01, |
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MSG_OS_HINT_PCO, |
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MSG_OS_HINT_RN, |
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}; |
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|
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struct amd_pmc_bit_map { |
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const char *name; |
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u32 bit_mask; |
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}; |
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|
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static const struct amd_pmc_bit_map soc15_ip_blk[] = { |
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{"DISPLAY", BIT(0)}, |
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{"CPU", BIT(1)}, |
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{"GFX", BIT(2)}, |
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{"VDD", BIT(3)}, |
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{"ACP", BIT(4)}, |
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{"VCN", BIT(5)}, |
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{"ISP", BIT(6)}, |
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{"NBIO", BIT(7)}, |
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{"DF", BIT(8)}, |
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{"USB0", BIT(9)}, |
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{"USB1", BIT(10)}, |
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{"LAPIC", BIT(11)}, |
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{} |
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}; |
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|
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struct amd_pmc_dev { |
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void __iomem *regbase; |
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void __iomem *smu_virt_addr; |
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void __iomem *fch_virt_addr; |
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u32 base_addr; |
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u32 cpu_id; |
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u32 active_ips; |
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/* SMU version information */ |
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u8 smu_program; |
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u8 major; |
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u8 minor; |
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u8 rev; |
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struct device *dev; |
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struct pci_dev *rdev; |
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struct mutex lock; /* generic mutex lock */ |
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struct pm_qos_request amd_pmc_pm_qos_req; |
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#if IS_ENABLED(CONFIG_DEBUG_FS) |
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struct dentry *dbgfs_dir; |
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#endif /* CONFIG_DEBUG_FS */ |
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}; |
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|
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static bool enable_stb; |
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module_param(enable_stb, bool, 0644); |
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MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism"); |
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|
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static struct amd_pmc_dev pmc; |
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static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret); |
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static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data); |
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static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf); |
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|
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static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset) |
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{ |
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return ioread32(dev->regbase + reg_offset); |
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} |
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|
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static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val) |
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{ |
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iowrite32(val, dev->regbase + reg_offset); |
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} |
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|
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struct smu_metrics { |
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u32 table_version; |
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u32 hint_count; |
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u32 s0i3_last_entry_status; |
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u32 timein_s0i2; |
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u64 timeentering_s0i3_lastcapture; |
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u64 timeentering_s0i3_totaltime; |
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u64 timeto_resume_to_os_lastcapture; |
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u64 timeto_resume_to_os_totaltime; |
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u64 timein_s0i3_lastcapture; |
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u64 timein_s0i3_totaltime; |
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u64 timein_swdrips_lastcapture; |
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u64 timein_swdrips_totaltime; |
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u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX]; |
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u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX]; |
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} __packed; |
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|
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static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev) |
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{ |
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int rc; |
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u32 val; |
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|
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rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1); |
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if (rc) |
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return rc; |
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|
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dev->smu_program = (val >> 24) & GENMASK(7, 0); |
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dev->major = (val >> 16) & GENMASK(7, 0); |
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dev->minor = (val >> 8) & GENMASK(7, 0); |
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dev->rev = (val >> 0) & GENMASK(7, 0); |
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|
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dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n", |
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dev->smu_program, dev->major, dev->minor, dev->rev); |
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|
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return 0; |
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} |
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|
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static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp) |
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{ |
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struct amd_pmc_dev *dev = filp->f_inode->i_private; |
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u32 size = FIFO_SIZE * sizeof(u32); |
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u32 *buf; |
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int rc; |
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|
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buf = kzalloc(size, GFP_KERNEL); |
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if (!buf) |
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return -ENOMEM; |
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|
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rc = amd_pmc_read_stb(dev, buf); |
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if (rc) { |
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kfree(buf); |
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return rc; |
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} |
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|
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filp->private_data = buf; |
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return rc; |
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} |
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|
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static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, |
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loff_t *pos) |
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{ |
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if (!filp->private_data) |
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return -EINVAL; |
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|
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return simple_read_from_buffer(buf, size, pos, filp->private_data, |
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FIFO_SIZE * sizeof(u32)); |
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} |
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static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp) |
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{ |
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kfree(filp->private_data); |
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return 0; |
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} |
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|
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static const struct file_operations amd_pmc_stb_debugfs_fops = { |
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.owner = THIS_MODULE, |
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.open = amd_pmc_stb_debugfs_open, |
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.read = amd_pmc_stb_debugfs_read, |
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.release = amd_pmc_stb_debugfs_release, |
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}; |
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|
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static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev, |
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struct seq_file *s) |
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{ |
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u32 val; |
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|
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switch (pdev->cpu_id) { |
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case AMD_CPU_ID_CZN: |
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val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN); |
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break; |
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case AMD_CPU_ID_YC: |
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val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC); |
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break; |
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default: |
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return -EINVAL; |
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} |
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if (dev) |
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dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val); |
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if (s) |
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seq_printf(s, "SMU idlemask : 0x%x\n", val); |
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return 0; |
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} |
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#ifdef CONFIG_DEBUG_FS |
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static int smu_fw_info_show(struct seq_file *s, void *unused) |
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{ |
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struct amd_pmc_dev *dev = s->private; |
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struct smu_metrics table; |
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int idx; |
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|
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if (dev->cpu_id == AMD_CPU_ID_PCO) |
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return -EINVAL; |
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memcpy_fromio(&table, dev->smu_virt_addr, sizeof(struct smu_metrics)); |
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|
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seq_puts(s, "\n=== SMU Statistics ===\n"); |
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seq_printf(s, "Table Version: %d\n", table.table_version); |
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seq_printf(s, "Hint Count: %d\n", table.hint_count); |
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seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" : |
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"Unknown/Fail"); |
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seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture); |
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seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture); |
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seq_printf(s, "Time (in us) to resume from S0i3: %lld\n", |
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table.timeto_resume_to_os_lastcapture); |
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|
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seq_puts(s, "\n=== Active time (in us) ===\n"); |
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for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) { |
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if (soc15_ip_blk[idx].bit_mask & dev->active_ips) |
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seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name, |
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table.timecondition_notmet_lastcapture[idx]); |
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} |
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|
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return 0; |
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} |
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DEFINE_SHOW_ATTRIBUTE(smu_fw_info); |
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|
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static int s0ix_stats_show(struct seq_file *s, void *unused) |
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{ |
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struct amd_pmc_dev *dev = s->private; |
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u64 entry_time, exit_time, residency; |
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|
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entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET); |
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entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET); |
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|
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exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET); |
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exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET); |
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|
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/* It's in 48MHz. We need to convert it */ |
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residency = exit_time - entry_time; |
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do_div(residency, 48); |
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|
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seq_puts(s, "=== S0ix statistics ===\n"); |
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seq_printf(s, "S0ix Entry Time: %lld\n", entry_time); |
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seq_printf(s, "S0ix Exit Time: %lld\n", exit_time); |
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seq_printf(s, "Residency Time: %lld\n", residency); |
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|
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return 0; |
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} |
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DEFINE_SHOW_ATTRIBUTE(s0ix_stats); |
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|
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static int amd_pmc_idlemask_show(struct seq_file *s, void *unused) |
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{ |
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struct amd_pmc_dev *dev = s->private; |
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int rc; |
|
|
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if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) { |
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rc = amd_pmc_idlemask_read(dev, NULL, s); |
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if (rc) |
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return rc; |
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} else { |
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seq_puts(s, "Unsupported SMU version for Idlemask\n"); |
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} |
|
|
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return 0; |
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} |
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DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask); |
|
|
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static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) |
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{ |
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debugfs_remove_recursive(dev->dbgfs_dir); |
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} |
|
|
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static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) |
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{ |
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dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL); |
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debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev, |
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&smu_fw_info_fops); |
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debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev, |
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&s0ix_stats_fops); |
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debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev, |
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&amd_pmc_idlemask_fops); |
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/* Enable STB only when the module_param is set */ |
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if (enable_stb) |
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debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev, |
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&amd_pmc_stb_debugfs_fops); |
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} |
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#else |
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static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) |
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{ |
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} |
|
|
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static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) |
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{ |
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} |
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#endif /* CONFIG_DEBUG_FS */ |
|
|
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static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev) |
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{ |
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u32 phys_addr_low, phys_addr_hi; |
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u64 smu_phys_addr; |
|
|
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if (dev->cpu_id == AMD_CPU_ID_PCO) |
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return -EINVAL; |
|
|
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/* Get Active devices list from SMU */ |
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amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1); |
|
|
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/* Get dram address */ |
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amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1); |
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amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1); |
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smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low); |
|
|
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dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, sizeof(struct smu_metrics)); |
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if (!dev->smu_virt_addr) |
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return -ENOMEM; |
|
|
|
/* Start the logging */ |
|
amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0); |
|
|
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return 0; |
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} |
|
|
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static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) |
|
{ |
|
u32 value; |
|
|
|
value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_RESPONSE); |
|
dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value); |
|
|
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value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT); |
|
dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value); |
|
|
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value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_MESSAGE); |
|
dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value); |
|
} |
|
|
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static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret) |
|
{ |
|
int rc; |
|
u32 val; |
|
|
|
mutex_lock(&dev->lock); |
|
/* Wait until we get a valid response */ |
|
rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE, |
|
val, val != 0, PMC_MSG_DELAY_MIN_US, |
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PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); |
|
if (rc) { |
|
dev_err(dev->dev, "failed to talk to SMU\n"); |
|
goto out_unlock; |
|
} |
|
|
|
/* Write zero to response register */ |
|
amd_pmc_reg_write(dev, AMD_PMC_REGISTER_RESPONSE, 0); |
|
|
|
/* Write argument into response register */ |
|
amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, arg); |
|
|
|
/* Write message ID to message ID register */ |
|
amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg); |
|
|
|
/* Wait until we get a valid response */ |
|
rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE, |
|
val, val != 0, PMC_MSG_DELAY_MIN_US, |
|
PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); |
|
if (rc) { |
|
dev_err(dev->dev, "SMU response timed out\n"); |
|
goto out_unlock; |
|
} |
|
|
|
switch (val) { |
|
case AMD_PMC_RESULT_OK: |
|
if (ret) { |
|
/* PMFW may take longer time to return back the data */ |
|
usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US); |
|
*data = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT); |
|
} |
|
break; |
|
case AMD_PMC_RESULT_CMD_REJECT_BUSY: |
|
dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val); |
|
rc = -EBUSY; |
|
goto out_unlock; |
|
case AMD_PMC_RESULT_CMD_UNKNOWN: |
|
dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val); |
|
rc = -EINVAL; |
|
goto out_unlock; |
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case AMD_PMC_RESULT_CMD_REJECT_PREREQ: |
|
case AMD_PMC_RESULT_FAILED: |
|
default: |
|
dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val); |
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rc = -EIO; |
|
goto out_unlock; |
|
} |
|
|
|
out_unlock: |
|
mutex_unlock(&dev->lock); |
|
amd_pmc_dump_registers(dev); |
|
return rc; |
|
} |
|
|
|
static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev) |
|
{ |
|
switch (dev->cpu_id) { |
|
case AMD_CPU_ID_PCO: |
|
return MSG_OS_HINT_PCO; |
|
case AMD_CPU_ID_RN: |
|
case AMD_CPU_ID_YC: |
|
return MSG_OS_HINT_RN; |
|
} |
|
return -EINVAL; |
|
} |
|
|
|
static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) |
|
{ |
|
struct rtc_device *rtc_device; |
|
time64_t then, now, duration; |
|
struct rtc_wkalrm alarm; |
|
struct rtc_time tm; |
|
int rc; |
|
|
|
if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53)) |
|
return 0; |
|
|
|
rtc_device = rtc_class_open("rtc0"); |
|
if (!rtc_device) |
|
return 0; |
|
rc = rtc_read_alarm(rtc_device, &alarm); |
|
if (rc) |
|
return rc; |
|
if (!alarm.enabled) { |
|
dev_dbg(pdev->dev, "alarm not enabled\n"); |
|
return 0; |
|
} |
|
rc = rtc_read_time(rtc_device, &tm); |
|
if (rc) |
|
return rc; |
|
then = rtc_tm_to_time64(&alarm.time); |
|
now = rtc_tm_to_time64(&tm); |
|
duration = then-now; |
|
|
|
/* in the past */ |
|
if (then < now) |
|
return 0; |
|
|
|
/* will be stored in upper 16 bits of s0i3 hint argument, |
|
* so timer wakeup from s0i3 is limited to ~18 hours or less |
|
*/ |
|
if (duration <= 4 || duration > U16_MAX) |
|
return -EINVAL; |
|
|
|
*arg |= (duration << 16); |
|
rc = rtc_alarm_irq_enable(rtc_device, 0); |
|
dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration); |
|
|
|
/* |
|
* Prevent CPUs from getting into deep idle states while sending OS_HINT |
|
* which is otherwise generally safe to send when at least one of the CPUs |
|
* is not in deep idle states. |
|
*/ |
|
cpu_latency_qos_update_request(&pdev->amd_pmc_pm_qos_req, AMD_PMC_MAX_IDLE_STATE_LATENCY); |
|
wake_up_all_idle_cpus(); |
|
|
|
return rc; |
|
} |
|
|
|
static int __maybe_unused amd_pmc_suspend(struct device *dev) |
|
{ |
|
struct amd_pmc_dev *pdev = dev_get_drvdata(dev); |
|
int rc; |
|
u8 msg; |
|
u32 arg = 1; |
|
|
|
/* Reset and Start SMU logging - to monitor the s0i3 stats */ |
|
amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0); |
|
amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0); |
|
|
|
/* Activate CZN specific RTC functionality */ |
|
if (pdev->cpu_id == AMD_CPU_ID_CZN) { |
|
rc = amd_pmc_verify_czn_rtc(pdev, &arg); |
|
if (rc) |
|
goto fail; |
|
} |
|
|
|
/* Dump the IdleMask before we send hint to SMU */ |
|
amd_pmc_idlemask_read(pdev, dev, NULL); |
|
msg = amd_pmc_get_os_hint(pdev); |
|
rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0); |
|
if (rc) { |
|
dev_err(pdev->dev, "suspend failed\n"); |
|
goto fail; |
|
} |
|
|
|
if (enable_stb) |
|
rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF); |
|
if (rc) { |
|
dev_err(pdev->dev, "error writing to STB\n"); |
|
goto fail; |
|
} |
|
|
|
return 0; |
|
fail: |
|
if (pdev->cpu_id == AMD_CPU_ID_CZN) |
|
cpu_latency_qos_update_request(&pdev->amd_pmc_pm_qos_req, |
|
PM_QOS_DEFAULT_VALUE); |
|
return rc; |
|
} |
|
|
|
static int __maybe_unused amd_pmc_resume(struct device *dev) |
|
{ |
|
struct amd_pmc_dev *pdev = dev_get_drvdata(dev); |
|
int rc; |
|
u8 msg; |
|
|
|
msg = amd_pmc_get_os_hint(pdev); |
|
rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0); |
|
if (rc) |
|
dev_err(pdev->dev, "resume failed\n"); |
|
|
|
/* Let SMU know that we are looking for stats */ |
|
amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0); |
|
|
|
/* Dump the IdleMask to see the blockers */ |
|
amd_pmc_idlemask_read(pdev, dev, NULL); |
|
|
|
/* Write data incremented by 1 to distinguish in stb_read */ |
|
if (enable_stb) |
|
rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF + 1); |
|
if (rc) |
|
dev_err(pdev->dev, "error writing to STB\n"); |
|
|
|
/* Restore the QoS request back to defaults if it was set */ |
|
if (pdev->cpu_id == AMD_CPU_ID_CZN) |
|
cpu_latency_qos_update_request(&pdev->amd_pmc_pm_qos_req, |
|
PM_QOS_DEFAULT_VALUE); |
|
|
|
return rc; |
|
} |
|
|
|
static const struct dev_pm_ops amd_pmc_pm_ops = { |
|
.suspend_noirq = amd_pmc_suspend, |
|
.resume_noirq = amd_pmc_resume, |
|
}; |
|
|
|
static const struct pci_device_id pmc_pci_ids[] = { |
|
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) }, |
|
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) }, |
|
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) }, |
|
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) }, |
|
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) }, |
|
{ } |
|
}; |
|
|
|
static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data) |
|
{ |
|
int err; |
|
|
|
err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0); |
|
if (err) { |
|
dev_err(dev->dev, "failed to write addr in stb: 0x%X\n", |
|
AMD_PMC_STB_INDEX_ADDRESS); |
|
return pcibios_err_to_errno(err); |
|
} |
|
|
|
err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data); |
|
if (err) { |
|
dev_err(dev->dev, "failed to write data in stb: 0x%X\n", |
|
AMD_PMC_STB_INDEX_DATA); |
|
return pcibios_err_to_errno(err); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf) |
|
{ |
|
int i, err; |
|
|
|
err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0); |
|
if (err) { |
|
dev_err(dev->dev, "error writing addr to stb: 0x%X\n", |
|
AMD_PMC_STB_INDEX_ADDRESS); |
|
return pcibios_err_to_errno(err); |
|
} |
|
|
|
for (i = 0; i < FIFO_SIZE; i++) { |
|
err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++); |
|
if (err) { |
|
dev_err(dev->dev, "error reading data from stb: 0x%X\n", |
|
AMD_PMC_STB_INDEX_DATA); |
|
return pcibios_err_to_errno(err); |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int amd_pmc_probe(struct platform_device *pdev) |
|
{ |
|
struct amd_pmc_dev *dev = &pmc; |
|
struct pci_dev *rdev; |
|
u32 base_addr_lo, base_addr_hi; |
|
u64 base_addr, fch_phys_addr; |
|
int err; |
|
u32 val; |
|
|
|
dev->dev = &pdev->dev; |
|
|
|
rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); |
|
if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) { |
|
err = -ENODEV; |
|
goto err_pci_dev_put; |
|
} |
|
|
|
dev->cpu_id = rdev->device; |
|
dev->rdev = rdev; |
|
err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO); |
|
if (err) { |
|
dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS); |
|
err = pcibios_err_to_errno(err); |
|
goto err_pci_dev_put; |
|
} |
|
|
|
err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val); |
|
if (err) { |
|
err = pcibios_err_to_errno(err); |
|
goto err_pci_dev_put; |
|
} |
|
|
|
base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK; |
|
|
|
err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI); |
|
if (err) { |
|
dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS); |
|
err = pcibios_err_to_errno(err); |
|
goto err_pci_dev_put; |
|
} |
|
|
|
err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val); |
|
if (err) { |
|
err = pcibios_err_to_errno(err); |
|
goto err_pci_dev_put; |
|
} |
|
|
|
base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK; |
|
base_addr = ((u64)base_addr_hi << 32 | base_addr_lo); |
|
|
|
dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET, |
|
AMD_PMC_MAPPING_SIZE); |
|
if (!dev->regbase) { |
|
err = -ENOMEM; |
|
goto err_pci_dev_put; |
|
} |
|
|
|
mutex_init(&dev->lock); |
|
|
|
/* Use FCH registers to get the S0ix stats */ |
|
base_addr_lo = FCH_BASE_PHY_ADDR_LOW; |
|
base_addr_hi = FCH_BASE_PHY_ADDR_HIGH; |
|
fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo); |
|
dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE); |
|
if (!dev->fch_virt_addr) { |
|
err = -ENOMEM; |
|
goto err_pci_dev_put; |
|
} |
|
|
|
/* Use SMU to get the s0i3 debug stats */ |
|
err = amd_pmc_setup_smu_logging(dev); |
|
if (err) |
|
dev_err(dev->dev, "SMU debugging info not supported on this platform\n"); |
|
|
|
amd_pmc_get_smu_version(dev); |
|
platform_set_drvdata(pdev, dev); |
|
amd_pmc_dbgfs_register(dev); |
|
cpu_latency_qos_add_request(&dev->amd_pmc_pm_qos_req, PM_QOS_DEFAULT_VALUE); |
|
return 0; |
|
|
|
err_pci_dev_put: |
|
pci_dev_put(rdev); |
|
return err; |
|
} |
|
|
|
static int amd_pmc_remove(struct platform_device *pdev) |
|
{ |
|
struct amd_pmc_dev *dev = platform_get_drvdata(pdev); |
|
|
|
amd_pmc_dbgfs_unregister(dev); |
|
pci_dev_put(dev->rdev); |
|
mutex_destroy(&dev->lock); |
|
return 0; |
|
} |
|
|
|
static const struct acpi_device_id amd_pmc_acpi_ids[] = { |
|
{"AMDI0005", 0}, |
|
{"AMDI0006", 0}, |
|
{"AMDI0007", 0}, |
|
{"AMD0004", 0}, |
|
{"AMD0005", 0}, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids); |
|
|
|
static struct platform_driver amd_pmc_driver = { |
|
.driver = { |
|
.name = "amd_pmc", |
|
.acpi_match_table = amd_pmc_acpi_ids, |
|
.pm = &amd_pmc_pm_ops, |
|
}, |
|
.probe = amd_pmc_probe, |
|
.remove = amd_pmc_remove, |
|
}; |
|
module_platform_driver(amd_pmc_driver); |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_DESCRIPTION("AMD PMC Driver");
|
|
|