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514 lines
13 KiB
514 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* phy-uniphier-ahci.c - PHY driver for UniPhier AHCI controller |
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* Copyright 2016-2020, Socionext Inc. |
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* Author: Kunihiko Hayashi <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/iopoll.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/reset.h> |
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struct uniphier_ahciphy_priv { |
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struct device *dev; |
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void __iomem *base; |
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struct clk *clk, *clk_parent, *clk_parent_gio; |
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struct reset_control *rst, *rst_parent, *rst_parent_gio; |
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struct reset_control *rst_pm, *rst_tx, *rst_rx; |
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const struct uniphier_ahciphy_soc_data *data; |
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}; |
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struct uniphier_ahciphy_soc_data { |
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int (*init)(struct uniphier_ahciphy_priv *priv); |
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int (*power_on)(struct uniphier_ahciphy_priv *priv); |
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int (*power_off)(struct uniphier_ahciphy_priv *priv); |
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bool is_legacy; |
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bool is_ready_high; |
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bool is_phy_clk; |
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}; |
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/* for Pro4 */ |
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#define CKCTRL0 0x0 |
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#define CKCTRL0_CK_OFF BIT(9) |
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#define CKCTRL0_NCY_MASK GENMASK(8, 4) |
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#define CKCTRL0_NCY5_MASK GENMASK(3, 2) |
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#define CKCTRL0_PRESCALE_MASK GENMASK(1, 0) |
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#define CKCTRL1 0x4 |
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#define CKCTRL1_LOS_LVL_MASK GENMASK(20, 16) |
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#define CKCTRL1_TX_LVL_MASK GENMASK(12, 8) |
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#define RXTXCTRL 0x8 |
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#define RXTXCTRL_RX_EQ_VALL_MASK GENMASK(31, 29) |
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#define RXTXCTRL_RX_DPLL_MODE_MASK GENMASK(28, 26) |
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#define RXTXCTRL_TX_ATTEN_MASK GENMASK(14, 12) |
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#define RXTXCTRL_TX_BOOST_MASK GENMASK(11, 8) |
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#define RXTXCTRL_TX_EDGERATE_MASK GENMASK(3, 2) |
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#define RXTXCTRL_TX_CKO_EN BIT(0) |
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#define RSTPWR 0x30 |
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#define RSTPWR_RX_EN_VAL BIT(18) |
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/* for PXs2/PXs3 */ |
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#define CKCTRL 0x0 |
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#define CKCTRL_P0_READY BIT(15) |
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#define CKCTRL_P0_RESET BIT(10) |
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#define CKCTRL_REF_SSP_EN BIT(9) |
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#define TXCTRL0 0x4 |
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#define TXCTRL0_AMP_G3_MASK GENMASK(22, 16) |
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#define TXCTRL0_AMP_G2_MASK GENMASK(14, 8) |
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#define TXCTRL0_AMP_G1_MASK GENMASK(6, 0) |
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#define TXCTRL1 0x8 |
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#define TXCTRL1_DEEMPH_G3_MASK GENMASK(21, 16) |
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#define TXCTRL1_DEEMPH_G2_MASK GENMASK(13, 8) |
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#define TXCTRL1_DEEMPH_G1_MASK GENMASK(5, 0) |
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#define RXCTRL 0xc |
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#define RXCTRL_LOS_LVL_MASK GENMASK(20, 16) |
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#define RXCTRL_LOS_BIAS_MASK GENMASK(10, 8) |
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#define RXCTRL_RX_EQ_MASK GENMASK(2, 0) |
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static int uniphier_ahciphy_pro4_init(struct uniphier_ahciphy_priv *priv) |
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{ |
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u32 val; |
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/* set phy MPLL parameters */ |
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val = readl(priv->base + CKCTRL0); |
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val &= ~CKCTRL0_NCY_MASK; |
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val |= FIELD_PREP(CKCTRL0_NCY_MASK, 0x6); |
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val &= ~CKCTRL0_NCY5_MASK; |
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val |= FIELD_PREP(CKCTRL0_NCY5_MASK, 0x2); |
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val &= ~CKCTRL0_PRESCALE_MASK; |
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val |= FIELD_PREP(CKCTRL0_PRESCALE_MASK, 0x1); |
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writel(val, priv->base + CKCTRL0); |
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/* setup phy control parameters */ |
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val = readl(priv->base + CKCTRL1); |
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val &= ~CKCTRL1_LOS_LVL_MASK; |
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val |= FIELD_PREP(CKCTRL1_LOS_LVL_MASK, 0x10); |
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val &= ~CKCTRL1_TX_LVL_MASK; |
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val |= FIELD_PREP(CKCTRL1_TX_LVL_MASK, 0x06); |
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writel(val, priv->base + CKCTRL1); |
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val = readl(priv->base + RXTXCTRL); |
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val &= ~RXTXCTRL_RX_EQ_VALL_MASK; |
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val |= FIELD_PREP(RXTXCTRL_RX_EQ_VALL_MASK, 0x6); |
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val &= ~RXTXCTRL_RX_DPLL_MODE_MASK; |
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val |= FIELD_PREP(RXTXCTRL_RX_DPLL_MODE_MASK, 0x3); |
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val &= ~RXTXCTRL_TX_ATTEN_MASK; |
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val |= FIELD_PREP(RXTXCTRL_TX_ATTEN_MASK, 0x3); |
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val &= ~RXTXCTRL_TX_BOOST_MASK; |
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val |= FIELD_PREP(RXTXCTRL_TX_BOOST_MASK, 0x5); |
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val &= ~RXTXCTRL_TX_EDGERATE_MASK; |
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val |= FIELD_PREP(RXTXCTRL_TX_EDGERATE_MASK, 0x0); |
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writel(val, priv->base + RXTXCTRL); |
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return 0; |
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} |
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static int uniphier_ahciphy_pro4_power_on(struct uniphier_ahciphy_priv *priv) |
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{ |
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u32 val; |
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int ret; |
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/* enable reference clock for phy */ |
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val = readl(priv->base + CKCTRL0); |
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val &= ~CKCTRL0_CK_OFF; |
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writel(val, priv->base + CKCTRL0); |
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/* enable TX clock */ |
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val = readl(priv->base + RXTXCTRL); |
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val |= RXTXCTRL_TX_CKO_EN; |
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writel(val, priv->base + RXTXCTRL); |
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/* wait until RX is ready */ |
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ret = readl_poll_timeout(priv->base + RSTPWR, val, |
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!(val & RSTPWR_RX_EN_VAL), 200, 2000); |
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if (ret) { |
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dev_err(priv->dev, "Failed to check whether Rx is ready\n"); |
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goto out_disable_clock; |
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} |
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/* release all reset */ |
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ret = reset_control_deassert(priv->rst_pm); |
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if (ret) { |
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dev_err(priv->dev, "Failed to release PM reset\n"); |
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goto out_disable_clock; |
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} |
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ret = reset_control_deassert(priv->rst_tx); |
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if (ret) { |
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dev_err(priv->dev, "Failed to release Tx reset\n"); |
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goto out_reset_pm_assert; |
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} |
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ret = reset_control_deassert(priv->rst_rx); |
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if (ret) { |
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dev_err(priv->dev, "Failed to release Rx reset\n"); |
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goto out_reset_tx_assert; |
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} |
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return 0; |
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out_reset_tx_assert: |
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reset_control_assert(priv->rst_tx); |
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out_reset_pm_assert: |
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reset_control_assert(priv->rst_pm); |
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out_disable_clock: |
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/* disable TX clock */ |
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val = readl(priv->base + RXTXCTRL); |
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val &= ~RXTXCTRL_TX_CKO_EN; |
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writel(val, priv->base + RXTXCTRL); |
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/* disable reference clock for phy */ |
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val = readl(priv->base + CKCTRL0); |
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val |= CKCTRL0_CK_OFF; |
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writel(val, priv->base + CKCTRL0); |
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return ret; |
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} |
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static int uniphier_ahciphy_pro4_power_off(struct uniphier_ahciphy_priv *priv) |
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{ |
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u32 val; |
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reset_control_assert(priv->rst_rx); |
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reset_control_assert(priv->rst_tx); |
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reset_control_assert(priv->rst_pm); |
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/* disable TX clock */ |
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val = readl(priv->base + RXTXCTRL); |
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val &= ~RXTXCTRL_TX_CKO_EN; |
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writel(val, priv->base + RXTXCTRL); |
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/* disable reference clock for phy */ |
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val = readl(priv->base + CKCTRL0); |
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val |= CKCTRL0_CK_OFF; |
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writel(val, priv->base + CKCTRL0); |
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return 0; |
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} |
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static void uniphier_ahciphy_pxs2_enable(struct uniphier_ahciphy_priv *priv, |
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bool enable) |
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{ |
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u32 val; |
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val = readl(priv->base + CKCTRL); |
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if (enable) { |
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val |= CKCTRL_REF_SSP_EN; |
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writel(val, priv->base + CKCTRL); |
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val &= ~CKCTRL_P0_RESET; |
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writel(val, priv->base + CKCTRL); |
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} else { |
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val |= CKCTRL_P0_RESET; |
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writel(val, priv->base + CKCTRL); |
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val &= ~CKCTRL_REF_SSP_EN; |
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writel(val, priv->base + CKCTRL); |
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} |
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} |
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static int uniphier_ahciphy_pxs2_power_on(struct uniphier_ahciphy_priv *priv) |
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{ |
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int ret; |
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u32 val; |
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uniphier_ahciphy_pxs2_enable(priv, true); |
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/* wait until PLL is ready */ |
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if (priv->data->is_ready_high) |
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ret = readl_poll_timeout(priv->base + CKCTRL, val, |
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(val & CKCTRL_P0_READY), 200, 400); |
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else |
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ret = readl_poll_timeout(priv->base + CKCTRL, val, |
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!(val & CKCTRL_P0_READY), 200, 400); |
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if (ret) { |
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dev_err(priv->dev, "Failed to check whether PHY PLL is ready\n"); |
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uniphier_ahciphy_pxs2_enable(priv, false); |
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} |
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return ret; |
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} |
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static int uniphier_ahciphy_pxs2_power_off(struct uniphier_ahciphy_priv *priv) |
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{ |
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uniphier_ahciphy_pxs2_enable(priv, false); |
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return 0; |
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} |
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static int uniphier_ahciphy_pxs3_init(struct uniphier_ahciphy_priv *priv) |
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{ |
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int i; |
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u32 val; |
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/* setup port parameter */ |
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val = readl(priv->base + TXCTRL0); |
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val &= ~TXCTRL0_AMP_G3_MASK; |
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val |= FIELD_PREP(TXCTRL0_AMP_G3_MASK, 0x73); |
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val &= ~TXCTRL0_AMP_G2_MASK; |
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val |= FIELD_PREP(TXCTRL0_AMP_G2_MASK, 0x46); |
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val &= ~TXCTRL0_AMP_G1_MASK; |
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val |= FIELD_PREP(TXCTRL0_AMP_G1_MASK, 0x42); |
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writel(val, priv->base + TXCTRL0); |
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val = readl(priv->base + TXCTRL1); |
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val &= ~TXCTRL1_DEEMPH_G3_MASK; |
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val |= FIELD_PREP(TXCTRL1_DEEMPH_G3_MASK, 0x23); |
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val &= ~TXCTRL1_DEEMPH_G2_MASK; |
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val |= FIELD_PREP(TXCTRL1_DEEMPH_G2_MASK, 0x05); |
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val &= ~TXCTRL1_DEEMPH_G1_MASK; |
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val |= FIELD_PREP(TXCTRL1_DEEMPH_G1_MASK, 0x05); |
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val = readl(priv->base + RXCTRL); |
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val &= ~RXCTRL_LOS_LVL_MASK; |
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val |= FIELD_PREP(RXCTRL_LOS_LVL_MASK, 0x9); |
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val &= ~RXCTRL_LOS_BIAS_MASK; |
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val |= FIELD_PREP(RXCTRL_LOS_BIAS_MASK, 0x2); |
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val &= ~RXCTRL_RX_EQ_MASK; |
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val |= FIELD_PREP(RXCTRL_RX_EQ_MASK, 0x1); |
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/* dummy read 25 times to make a wait time for the phy to stabilize */ |
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for (i = 0; i < 25; i++) |
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readl(priv->base + CKCTRL); |
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return 0; |
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} |
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static int uniphier_ahciphy_init(struct phy *phy) |
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{ |
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struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy); |
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int ret; |
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ret = clk_prepare_enable(priv->clk_parent_gio); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(priv->clk_parent); |
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if (ret) |
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goto out_clk_gio_disable; |
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ret = reset_control_deassert(priv->rst_parent_gio); |
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if (ret) |
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goto out_clk_disable; |
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ret = reset_control_deassert(priv->rst_parent); |
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if (ret) |
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goto out_rst_gio_assert; |
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if (priv->data->init) { |
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ret = priv->data->init(priv); |
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if (ret) |
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goto out_rst_assert; |
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} |
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return 0; |
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out_rst_assert: |
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reset_control_assert(priv->rst_parent); |
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out_rst_gio_assert: |
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reset_control_assert(priv->rst_parent_gio); |
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out_clk_disable: |
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clk_disable_unprepare(priv->clk_parent); |
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out_clk_gio_disable: |
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clk_disable_unprepare(priv->clk_parent_gio); |
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return ret; |
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} |
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static int uniphier_ahciphy_exit(struct phy *phy) |
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{ |
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struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy); |
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reset_control_assert(priv->rst_parent); |
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reset_control_assert(priv->rst_parent_gio); |
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clk_disable_unprepare(priv->clk_parent); |
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clk_disable_unprepare(priv->clk_parent_gio); |
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return 0; |
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} |
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static int uniphier_ahciphy_power_on(struct phy *phy) |
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{ |
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struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy); |
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int ret = 0; |
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ret = clk_prepare_enable(priv->clk); |
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if (ret) |
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return ret; |
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ret = reset_control_deassert(priv->rst); |
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if (ret) |
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goto out_clk_disable; |
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if (priv->data->power_on) { |
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ret = priv->data->power_on(priv); |
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if (ret) |
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goto out_reset_assert; |
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} |
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return 0; |
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out_reset_assert: |
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reset_control_assert(priv->rst); |
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out_clk_disable: |
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clk_disable_unprepare(priv->clk); |
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return ret; |
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} |
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static int uniphier_ahciphy_power_off(struct phy *phy) |
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{ |
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struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy); |
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int ret = 0; |
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if (priv->data->power_off) |
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ret = priv->data->power_off(priv); |
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reset_control_assert(priv->rst); |
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clk_disable_unprepare(priv->clk); |
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return ret; |
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} |
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static const struct phy_ops uniphier_ahciphy_ops = { |
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.init = uniphier_ahciphy_init, |
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.exit = uniphier_ahciphy_exit, |
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.power_on = uniphier_ahciphy_power_on, |
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.power_off = uniphier_ahciphy_power_off, |
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.owner = THIS_MODULE, |
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}; |
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static int uniphier_ahciphy_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct uniphier_ahciphy_priv *priv; |
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struct phy *phy; |
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struct phy_provider *phy_provider; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->dev = dev; |
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priv->data = of_device_get_match_data(dev); |
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if (WARN_ON(!priv->data)) |
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return -EINVAL; |
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priv->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(priv->base)) |
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return PTR_ERR(priv->base); |
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priv->clk_parent = devm_clk_get(dev, "link"); |
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if (IS_ERR(priv->clk_parent)) |
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return PTR_ERR(priv->clk_parent); |
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if (priv->data->is_phy_clk) { |
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priv->clk = devm_clk_get(dev, "phy"); |
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if (IS_ERR(priv->clk)) |
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return PTR_ERR(priv->clk); |
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} |
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priv->rst_parent = devm_reset_control_get_shared(dev, "link"); |
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if (IS_ERR(priv->rst_parent)) |
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return PTR_ERR(priv->rst_parent); |
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priv->rst = devm_reset_control_get_shared(dev, "phy"); |
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if (IS_ERR(priv->rst)) |
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return PTR_ERR(priv->rst); |
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if (priv->data->is_legacy) { |
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priv->clk_parent_gio = devm_clk_get(dev, "gio"); |
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if (IS_ERR(priv->clk_parent_gio)) |
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return PTR_ERR(priv->clk_parent_gio); |
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priv->rst_parent_gio = |
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devm_reset_control_get_shared(dev, "gio"); |
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if (IS_ERR(priv->rst_parent_gio)) |
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return PTR_ERR(priv->rst_parent_gio); |
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priv->rst_pm = devm_reset_control_get_shared(dev, "pm"); |
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if (IS_ERR(priv->rst_pm)) |
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return PTR_ERR(priv->rst_pm); |
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priv->rst_tx = devm_reset_control_get_shared(dev, "tx"); |
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if (IS_ERR(priv->rst_tx)) |
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return PTR_ERR(priv->rst_tx); |
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priv->rst_rx = devm_reset_control_get_shared(dev, "rx"); |
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if (IS_ERR(priv->rst_rx)) |
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return PTR_ERR(priv->rst_rx); |
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} |
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phy = devm_phy_create(dev, dev->of_node, &uniphier_ahciphy_ops); |
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if (IS_ERR(phy)) { |
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dev_err(dev, "failed to create phy\n"); |
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return PTR_ERR(phy); |
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} |
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phy_set_drvdata(phy, priv); |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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if (IS_ERR(phy_provider)) |
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return PTR_ERR(phy_provider); |
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return 0; |
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} |
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static const struct uniphier_ahciphy_soc_data uniphier_pro4_data = { |
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.init = uniphier_ahciphy_pro4_init, |
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.power_on = uniphier_ahciphy_pro4_power_on, |
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.power_off = uniphier_ahciphy_pro4_power_off, |
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.is_legacy = true, |
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.is_phy_clk = false, |
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}; |
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static const struct uniphier_ahciphy_soc_data uniphier_pxs2_data = { |
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.power_on = uniphier_ahciphy_pxs2_power_on, |
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.power_off = uniphier_ahciphy_pxs2_power_off, |
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.is_legacy = false, |
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.is_ready_high = false, |
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.is_phy_clk = false, |
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}; |
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static const struct uniphier_ahciphy_soc_data uniphier_pxs3_data = { |
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.init = uniphier_ahciphy_pxs3_init, |
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.power_on = uniphier_ahciphy_pxs2_power_on, |
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.power_off = uniphier_ahciphy_pxs2_power_off, |
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.is_legacy = false, |
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.is_ready_high = true, |
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.is_phy_clk = true, |
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}; |
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static const struct of_device_id uniphier_ahciphy_match[] = { |
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{ |
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.compatible = "socionext,uniphier-pro4-ahci-phy", |
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.data = &uniphier_pro4_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pxs2-ahci-phy", |
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.data = &uniphier_pxs2_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pxs3-ahci-phy", |
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.data = &uniphier_pxs3_data, |
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}, |
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{ /* Sentinel */ }, |
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}; |
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MODULE_DEVICE_TABLE(of, uniphier_ahciphy_match); |
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static struct platform_driver uniphier_ahciphy_driver = { |
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.probe = uniphier_ahciphy_probe, |
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.driver = { |
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.name = "uniphier-ahci-phy", |
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.of_match_table = uniphier_ahciphy_match, |
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}, |
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}; |
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module_platform_driver(uniphier_ahciphy_driver); |
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MODULE_AUTHOR("Kunihiko Hayashi <[email protected]>"); |
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MODULE_DESCRIPTION("UniPhier PHY driver for AHCI controller"); |
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MODULE_LICENSE("GPL v2");
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