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685 lines
20 KiB
685 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2018 Rockchip Electronics Co. Ltd. |
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* |
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* Author: Wyon Bi <[email protected]> |
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*/ |
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#include <linux/bits.h> |
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#include <linux/kernel.h> |
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#include <linux/clk.h> |
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#include <linux/iopoll.h> |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/reset.h> |
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#include <linux/time64.h> |
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#include <linux/phy/phy.h> |
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#include <linux/phy/phy-mipi-dphy.h> |
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#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) |
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/* |
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* The offset address[7:0] is distributed two parts, one from the bit7 to bit5 |
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* is the first address, the other from the bit4 to bit0 is the second address. |
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* when you configure the registers, you must set both of them. The Clock Lane |
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* and Data Lane use the same registers with the same second address, but the |
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* first address is different. |
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*/ |
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#define FIRST_ADDRESS(x) (((x) & 0x7) << 5) |
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#define SECOND_ADDRESS(x) (((x) & 0x1f) << 0) |
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#define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ |
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SECOND_ADDRESS(second)) |
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/* Analog Register Part: reg00 */ |
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#define BANDGAP_POWER_MASK BIT(7) |
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#define BANDGAP_POWER_DOWN BIT(7) |
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#define BANDGAP_POWER_ON 0 |
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#define LANE_EN_MASK GENMASK(6, 2) |
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#define LANE_EN_CK BIT(6) |
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#define LANE_EN_3 BIT(5) |
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#define LANE_EN_2 BIT(4) |
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#define LANE_EN_1 BIT(3) |
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#define LANE_EN_0 BIT(2) |
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#define POWER_WORK_MASK GENMASK(1, 0) |
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#define POWER_WORK_ENABLE UPDATE(1, 1, 0) |
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#define POWER_WORK_DISABLE UPDATE(2, 1, 0) |
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/* Analog Register Part: reg01 */ |
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#define REG_SYNCRST_MASK BIT(2) |
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#define REG_SYNCRST_RESET BIT(2) |
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#define REG_SYNCRST_NORMAL 0 |
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#define REG_LDOPD_MASK BIT(1) |
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#define REG_LDOPD_POWER_DOWN BIT(1) |
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#define REG_LDOPD_POWER_ON 0 |
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#define REG_PLLPD_MASK BIT(0) |
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#define REG_PLLPD_POWER_DOWN BIT(0) |
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#define REG_PLLPD_POWER_ON 0 |
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/* Analog Register Part: reg03 */ |
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#define REG_FBDIV_HI_MASK BIT(5) |
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#define REG_FBDIV_HI(x) UPDATE((x >> 8), 5, 5) |
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#define REG_PREDIV_MASK GENMASK(4, 0) |
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#define REG_PREDIV(x) UPDATE(x, 4, 0) |
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/* Analog Register Part: reg04 */ |
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#define REG_FBDIV_LO_MASK GENMASK(7, 0) |
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#define REG_FBDIV_LO(x) UPDATE(x, 7, 0) |
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/* Analog Register Part: reg05 */ |
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#define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4) |
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#define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4) |
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#define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0) |
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#define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0) |
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/* Analog Register Part: reg06 */ |
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#define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4) |
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#define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4) |
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#define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0) |
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#define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0) |
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/* Analog Register Part: reg07 */ |
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#define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4) |
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#define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4) |
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#define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0) |
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#define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0) |
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/* Analog Register Part: reg08 */ |
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#define SAMPLE_CLOCK_DIRECTION_MASK BIT(4) |
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#define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4) |
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#define SAMPLE_CLOCK_DIRECTION_FORWARD 0 |
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/* Digital Register Part: reg00 */ |
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#define REG_DIG_RSTN_MASK BIT(0) |
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#define REG_DIG_RSTN_NORMAL BIT(0) |
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#define REG_DIG_RSTN_RESET 0 |
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/* Digital Register Part: reg01 */ |
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#define INVERT_TXCLKESC_MASK BIT(1) |
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#define INVERT_TXCLKESC_ENABLE BIT(1) |
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#define INVERT_TXCLKESC_DISABLE 0 |
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#define INVERT_TXBYTECLKHS_MASK BIT(0) |
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#define INVERT_TXBYTECLKHS_ENABLE BIT(0) |
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#define INVERT_TXBYTECLKHS_DISABLE 0 |
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/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */ |
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#define T_LPX_CNT_MASK GENMASK(5, 0) |
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#define T_LPX_CNT(x) UPDATE(x, 5, 0) |
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/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */ |
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#define T_HS_PREPARE_CNT_MASK GENMASK(6, 0) |
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#define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0) |
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/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */ |
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#define T_HS_ZERO_CNT_MASK GENMASK(5, 0) |
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#define T_HS_ZERO_CNT(x) UPDATE(x, 5, 0) |
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/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */ |
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#define T_HS_TRAIL_CNT_MASK GENMASK(6, 0) |
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#define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0) |
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/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */ |
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#define T_HS_EXIT_CNT_MASK GENMASK(4, 0) |
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#define T_HS_EXIT_CNT(x) UPDATE(x, 4, 0) |
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/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */ |
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#define T_CLK_POST_CNT_MASK GENMASK(3, 0) |
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#define T_CLK_POST_CNT(x) UPDATE(x, 3, 0) |
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/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */ |
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#define LPDT_TX_PPI_SYNC_MASK BIT(2) |
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#define LPDT_TX_PPI_SYNC_ENABLE BIT(2) |
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#define LPDT_TX_PPI_SYNC_DISABLE 0 |
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#define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0) |
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#define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0) |
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/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */ |
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#define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0) |
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#define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0) |
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/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */ |
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#define T_CLK_PRE_CNT_MASK GENMASK(3, 0) |
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#define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0) |
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/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */ |
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#define T_TA_GO_CNT_MASK GENMASK(5, 0) |
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#define T_TA_GO_CNT(x) UPDATE(x, 5, 0) |
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/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */ |
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#define T_TA_SURE_CNT_MASK GENMASK(5, 0) |
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#define T_TA_SURE_CNT(x) UPDATE(x, 5, 0) |
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/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */ |
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#define T_TA_WAIT_CNT_MASK GENMASK(5, 0) |
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#define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0) |
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/* LVDS Register Part: reg00 */ |
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#define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2) |
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#define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2) |
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#define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0 |
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/* LVDS Register Part: reg01 */ |
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#define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7) |
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#define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7) |
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#define LVDS_DIGITAL_INTERNAL_DISABLE 0 |
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/* LVDS Register Part: reg03 */ |
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#define MODE_ENABLE_MASK GENMASK(2, 0) |
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#define TTL_MODE_ENABLE BIT(2) |
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#define LVDS_MODE_ENABLE BIT(1) |
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#define MIPI_MODE_ENABLE BIT(0) |
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/* LVDS Register Part: reg0b */ |
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#define LVDS_LANE_EN_MASK GENMASK(7, 3) |
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#define LVDS_DATA_LANE0_EN BIT(7) |
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#define LVDS_DATA_LANE1_EN BIT(6) |
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#define LVDS_DATA_LANE2_EN BIT(5) |
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#define LVDS_DATA_LANE3_EN BIT(4) |
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#define LVDS_CLK_LANE_EN BIT(3) |
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#define LVDS_PLL_POWER_MASK BIT(2) |
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#define LVDS_PLL_POWER_OFF BIT(2) |
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#define LVDS_PLL_POWER_ON 0 |
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#define LVDS_BANDGAP_POWER_MASK BIT(0) |
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#define LVDS_BANDGAP_POWER_DOWN BIT(0) |
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#define LVDS_BANDGAP_POWER_ON 0 |
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#define DSI_PHY_RSTZ 0xa0 |
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#define PHY_ENABLECLK BIT(2) |
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#define DSI_PHY_STATUS 0xb0 |
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#define PHY_LOCK BIT(0) |
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struct inno_dsidphy { |
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struct device *dev; |
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struct clk *ref_clk; |
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struct clk *pclk_phy; |
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struct clk *pclk_host; |
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void __iomem *phy_base; |
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void __iomem *host_base; |
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struct reset_control *rst; |
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enum phy_mode mode; |
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struct phy_configure_opts_mipi_dphy dphy_cfg; |
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struct clk *pll_clk; |
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struct { |
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struct clk_hw hw; |
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u8 prediv; |
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u16 fbdiv; |
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unsigned long rate; |
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} pll; |
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}; |
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enum { |
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REGISTER_PART_ANALOG, |
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REGISTER_PART_DIGITAL, |
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REGISTER_PART_CLOCK_LANE, |
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REGISTER_PART_DATA0_LANE, |
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REGISTER_PART_DATA1_LANE, |
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REGISTER_PART_DATA2_LANE, |
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REGISTER_PART_DATA3_LANE, |
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REGISTER_PART_LVDS, |
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}; |
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static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw) |
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{ |
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return container_of(hw, struct inno_dsidphy, pll.hw); |
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} |
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static void phy_update_bits(struct inno_dsidphy *inno, |
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u8 first, u8 second, u8 mask, u8 val) |
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{ |
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u32 reg = PHY_REG(first, second) << 2; |
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unsigned int tmp, orig; |
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orig = readl(inno->phy_base + reg); |
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tmp = orig & ~mask; |
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tmp |= val & mask; |
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writel(tmp, inno->phy_base + reg); |
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} |
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static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno, |
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unsigned long rate) |
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{ |
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unsigned long prate = clk_get_rate(inno->ref_clk); |
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unsigned long best_freq = 0; |
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unsigned long fref, fout; |
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u8 min_prediv, max_prediv; |
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u8 _prediv, best_prediv = 1; |
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u16 _fbdiv, best_fbdiv = 1; |
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u32 min_delta = UINT_MAX; |
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/* |
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* The PLL output frequency can be calculated using a simple formula: |
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* PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2 |
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* PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 |
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*/ |
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fref = prate / 2; |
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if (rate > 1000000000UL) |
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fout = 1000000000UL; |
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else |
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fout = rate; |
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/* 5Mhz < Fref / prediv < 40MHz */ |
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min_prediv = DIV_ROUND_UP(fref, 40000000); |
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max_prediv = fref / 5000000; |
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for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { |
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u64 tmp; |
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u32 delta; |
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tmp = (u64)fout * _prediv; |
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do_div(tmp, fref); |
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_fbdiv = tmp; |
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/* |
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* The possible settings of feedback divider are |
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* 12, 13, 14, 16, ~ 511 |
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*/ |
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if (_fbdiv == 15) |
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continue; |
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if (_fbdiv < 12 || _fbdiv > 511) |
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continue; |
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tmp = (u64)_fbdiv * fref; |
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do_div(tmp, _prediv); |
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delta = abs(fout - tmp); |
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if (!delta) { |
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best_prediv = _prediv; |
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best_fbdiv = _fbdiv; |
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best_freq = tmp; |
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break; |
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} else if (delta < min_delta) { |
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best_prediv = _prediv; |
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best_fbdiv = _fbdiv; |
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best_freq = tmp; |
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min_delta = delta; |
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} |
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} |
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if (best_freq) { |
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inno->pll.prediv = best_prediv; |
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inno->pll.fbdiv = best_fbdiv; |
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inno->pll.rate = best_freq; |
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} |
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return best_freq; |
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} |
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static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) |
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{ |
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struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg; |
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const struct { |
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unsigned long rate; |
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u8 hs_prepare; |
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u8 clk_lane_hs_zero; |
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u8 data_lane_hs_zero; |
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u8 hs_trail; |
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} timings[] = { |
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{ 110000000, 0x20, 0x16, 0x02, 0x22}, |
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{ 150000000, 0x06, 0x16, 0x03, 0x45}, |
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{ 200000000, 0x18, 0x17, 0x04, 0x0b}, |
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{ 250000000, 0x05, 0x17, 0x05, 0x16}, |
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{ 300000000, 0x51, 0x18, 0x06, 0x2c}, |
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{ 400000000, 0x64, 0x19, 0x07, 0x33}, |
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{ 500000000, 0x20, 0x1b, 0x07, 0x4e}, |
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{ 600000000, 0x6a, 0x1d, 0x08, 0x3a}, |
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{ 700000000, 0x3e, 0x1e, 0x08, 0x6a}, |
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{ 800000000, 0x21, 0x1f, 0x09, 0x29}, |
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{1000000000, 0x09, 0x20, 0x09, 0x27}, |
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}; |
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u32 t_txbyteclkhs, t_txclkesc; |
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u32 txbyteclkhs, txclkesc, esc_clk_div; |
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u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; |
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u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; |
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unsigned int i; |
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inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate); |
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/* Select MIPI mode */ |
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phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, |
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MODE_ENABLE_MASK, MIPI_MODE_ENABLE); |
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/* Configure PLL */ |
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, |
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REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); |
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, |
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REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); |
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, |
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REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); |
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/* Enable PLL and LDO */ |
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, |
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REG_LDOPD_MASK | REG_PLLPD_MASK, |
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REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON); |
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/* Reset analog */ |
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, |
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REG_SYNCRST_MASK, REG_SYNCRST_RESET); |
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udelay(1); |
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, |
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REG_SYNCRST_MASK, REG_SYNCRST_NORMAL); |
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/* Reset digital */ |
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phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, |
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REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET); |
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udelay(1); |
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phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, |
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REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL); |
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txbyteclkhs = inno->pll.rate / 8; |
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t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs); |
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esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000); |
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txclkesc = txbyteclkhs / esc_clk_div; |
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t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc); |
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/* |
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* The value of counter for HS Ths-exit |
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* Ths-exit = Tpin_txbyteclkhs * value |
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*/ |
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hs_exit = DIV_ROUND_UP(cfg->hs_exit, t_txbyteclkhs); |
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/* |
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* The value of counter for HS Tclk-post |
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* Tclk-post = Tpin_txbyteclkhs * value |
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*/ |
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clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs); |
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/* |
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* The value of counter for HS Tclk-pre |
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* Tclk-pre = Tpin_txbyteclkhs * value |
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*/ |
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clk_pre = DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE); |
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/* |
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* The value of counter for HS Tlpx Time |
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* Tlpx = Tpin_txbyteclkhs * (2 + value) |
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*/ |
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lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs); |
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if (lpx >= 2) |
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lpx -= 2; |
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/* |
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* The value of counter for HS Tta-go |
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* Tta-go for turnaround |
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* Tta-go = Ttxclkesc * value |
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*/ |
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ta_go = DIV_ROUND_UP(cfg->ta_go, t_txclkesc); |
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/* |
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* The value of counter for HS Tta-sure |
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* Tta-sure for turnaround |
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* Tta-sure = Ttxclkesc * value |
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*/ |
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ta_sure = DIV_ROUND_UP(cfg->ta_sure, t_txclkesc); |
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/* |
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* The value of counter for HS Tta-wait |
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* Tta-wait for turnaround |
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* Tta-wait = Ttxclkesc * value |
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*/ |
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ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc); |
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for (i = 0; i < ARRAY_SIZE(timings); i++) |
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if (inno->pll.rate <= timings[i].rate) |
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break; |
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if (i == ARRAY_SIZE(timings)) |
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--i; |
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hs_prepare = timings[i].hs_prepare; |
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hs_trail = timings[i].hs_trail; |
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clk_lane_hs_zero = timings[i].clk_lane_hs_zero; |
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data_lane_hs_zero = timings[i].data_lane_hs_zero; |
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wakeup = 0x3ff; |
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for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) { |
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if (i == REGISTER_PART_CLOCK_LANE) |
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hs_zero = clk_lane_hs_zero; |
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else |
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hs_zero = data_lane_hs_zero; |
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phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK, |
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T_LPX_CNT(lpx)); |
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phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK, |
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T_HS_PREPARE_CNT(hs_prepare)); |
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phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK, |
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T_HS_ZERO_CNT(hs_zero)); |
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phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK, |
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T_HS_TRAIL_CNT(hs_trail)); |
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phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK, |
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T_HS_EXIT_CNT(hs_exit)); |
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phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK, |
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T_CLK_POST_CNT(clk_post)); |
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phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK, |
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T_CLK_PRE_CNT(clk_pre)); |
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phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK, |
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T_WAKEUP_CNT_HI(wakeup >> 8)); |
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phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK, |
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T_WAKEUP_CNT_LO(wakeup)); |
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phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK, |
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T_TA_GO_CNT(ta_go)); |
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phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK, |
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T_TA_SURE_CNT(ta_sure)); |
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phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK, |
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T_TA_WAIT_CNT(ta_wait)); |
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} |
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/* Enable all lanes on analog part */ |
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, |
|
LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 | |
|
LANE_EN_1 | LANE_EN_0); |
|
} |
|
|
|
static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) |
|
{ |
|
u8 prediv = 2; |
|
u16 fbdiv = 28; |
|
|
|
/* Sample clock reverse direction */ |
|
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, |
|
SAMPLE_CLOCK_DIRECTION_MASK, |
|
SAMPLE_CLOCK_DIRECTION_REVERSE); |
|
|
|
/* Select LVDS mode */ |
|
phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, |
|
MODE_ENABLE_MASK, LVDS_MODE_ENABLE); |
|
/* Configure PLL */ |
|
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, |
|
REG_PREDIV_MASK, REG_PREDIV(prediv)); |
|
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, |
|
REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv)); |
|
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, |
|
REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv)); |
|
phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc); |
|
/* Enable PLL and Bandgap */ |
|
phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, |
|
LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, |
|
LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON); |
|
|
|
msleep(20); |
|
|
|
/* Reset LVDS digital logic */ |
|
phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, |
|
LVDS_DIGITAL_INTERNAL_RESET_MASK, |
|
LVDS_DIGITAL_INTERNAL_RESET_ENABLE); |
|
udelay(1); |
|
phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, |
|
LVDS_DIGITAL_INTERNAL_RESET_MASK, |
|
LVDS_DIGITAL_INTERNAL_RESET_DISABLE); |
|
/* Enable LVDS digital logic */ |
|
phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, |
|
LVDS_DIGITAL_INTERNAL_ENABLE_MASK, |
|
LVDS_DIGITAL_INTERNAL_ENABLE); |
|
/* Enable LVDS analog driver */ |
|
phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, |
|
LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN | |
|
LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN | |
|
LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN); |
|
} |
|
|
|
static int inno_dsidphy_power_on(struct phy *phy) |
|
{ |
|
struct inno_dsidphy *inno = phy_get_drvdata(phy); |
|
|
|
clk_prepare_enable(inno->pclk_phy); |
|
clk_prepare_enable(inno->ref_clk); |
|
pm_runtime_get_sync(inno->dev); |
|
|
|
/* Bandgap power on */ |
|
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, |
|
BANDGAP_POWER_MASK, BANDGAP_POWER_ON); |
|
/* Enable power work */ |
|
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, |
|
POWER_WORK_MASK, POWER_WORK_ENABLE); |
|
|
|
switch (inno->mode) { |
|
case PHY_MODE_MIPI_DPHY: |
|
inno_dsidphy_mipi_mode_enable(inno); |
|
break; |
|
case PHY_MODE_LVDS: |
|
inno_dsidphy_lvds_mode_enable(inno); |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int inno_dsidphy_power_off(struct phy *phy) |
|
{ |
|
struct inno_dsidphy *inno = phy_get_drvdata(phy); |
|
|
|
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0); |
|
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, |
|
REG_LDOPD_MASK | REG_PLLPD_MASK, |
|
REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN); |
|
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, |
|
POWER_WORK_MASK, POWER_WORK_DISABLE); |
|
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, |
|
BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN); |
|
|
|
phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0); |
|
phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, |
|
LVDS_DIGITAL_INTERNAL_ENABLE_MASK, |
|
LVDS_DIGITAL_INTERNAL_DISABLE); |
|
phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, |
|
LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, |
|
LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN); |
|
|
|
pm_runtime_put(inno->dev); |
|
clk_disable_unprepare(inno->ref_clk); |
|
clk_disable_unprepare(inno->pclk_phy); |
|
|
|
return 0; |
|
} |
|
|
|
static int inno_dsidphy_set_mode(struct phy *phy, enum phy_mode mode, |
|
int submode) |
|
{ |
|
struct inno_dsidphy *inno = phy_get_drvdata(phy); |
|
|
|
switch (mode) { |
|
case PHY_MODE_MIPI_DPHY: |
|
case PHY_MODE_LVDS: |
|
inno->mode = mode; |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int inno_dsidphy_configure(struct phy *phy, |
|
union phy_configure_opts *opts) |
|
{ |
|
struct inno_dsidphy *inno = phy_get_drvdata(phy); |
|
int ret; |
|
|
|
if (inno->mode != PHY_MODE_MIPI_DPHY) |
|
return -EINVAL; |
|
|
|
ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); |
|
if (ret) |
|
return ret; |
|
|
|
memcpy(&inno->dphy_cfg, &opts->mipi_dphy, sizeof(inno->dphy_cfg)); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct phy_ops inno_dsidphy_ops = { |
|
.configure = inno_dsidphy_configure, |
|
.set_mode = inno_dsidphy_set_mode, |
|
.power_on = inno_dsidphy_power_on, |
|
.power_off = inno_dsidphy_power_off, |
|
.owner = THIS_MODULE, |
|
}; |
|
|
|
static int inno_dsidphy_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct inno_dsidphy *inno; |
|
struct phy_provider *phy_provider; |
|
struct phy *phy; |
|
int ret; |
|
|
|
inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL); |
|
if (!inno) |
|
return -ENOMEM; |
|
|
|
inno->dev = dev; |
|
platform_set_drvdata(pdev, inno); |
|
|
|
inno->phy_base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(inno->phy_base)) |
|
return PTR_ERR(inno->phy_base); |
|
|
|
inno->ref_clk = devm_clk_get(dev, "ref"); |
|
if (IS_ERR(inno->ref_clk)) { |
|
ret = PTR_ERR(inno->ref_clk); |
|
dev_err(dev, "failed to get ref clock: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
inno->pclk_phy = devm_clk_get(dev, "pclk"); |
|
if (IS_ERR(inno->pclk_phy)) { |
|
ret = PTR_ERR(inno->pclk_phy); |
|
dev_err(dev, "failed to get phy pclk: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
inno->rst = devm_reset_control_get(dev, "apb"); |
|
if (IS_ERR(inno->rst)) { |
|
ret = PTR_ERR(inno->rst); |
|
dev_err(dev, "failed to get system reset control: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
phy = devm_phy_create(dev, NULL, &inno_dsidphy_ops); |
|
if (IS_ERR(phy)) { |
|
ret = PTR_ERR(phy); |
|
dev_err(dev, "failed to create phy: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
phy_set_drvdata(phy, inno); |
|
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
|
if (IS_ERR(phy_provider)) { |
|
ret = PTR_ERR(phy_provider); |
|
dev_err(dev, "failed to register phy provider: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
pm_runtime_enable(dev); |
|
|
|
return 0; |
|
} |
|
|
|
static int inno_dsidphy_remove(struct platform_device *pdev) |
|
{ |
|
struct inno_dsidphy *inno = platform_get_drvdata(pdev); |
|
|
|
pm_runtime_disable(inno->dev); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id inno_dsidphy_of_match[] = { |
|
{ .compatible = "rockchip,px30-dsi-dphy", }, |
|
{ .compatible = "rockchip,rk3128-dsi-dphy", }, |
|
{ .compatible = "rockchip,rk3368-dsi-dphy", }, |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(of, inno_dsidphy_of_match); |
|
|
|
static struct platform_driver inno_dsidphy_driver = { |
|
.driver = { |
|
.name = "inno-dsidphy", |
|
.of_match_table = of_match_ptr(inno_dsidphy_of_match), |
|
}, |
|
.probe = inno_dsidphy_probe, |
|
.remove = inno_dsidphy_remove, |
|
}; |
|
module_platform_driver(inno_dsidphy_driver); |
|
|
|
MODULE_AUTHOR("Wyon Bi <[email protected]>"); |
|
MODULE_DESCRIPTION("Innosilicon MIPI/LVDS/TTL Video Combo PHY driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|