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221 lines
5.4 KiB
221 lines
5.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2019 MediaTek Inc. |
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* Author: Stanley Chu <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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/* mphy register and offsets */ |
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#define MP_GLB_DIG_8C 0x008C |
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#define FRC_PLL_ISO_EN BIT(8) |
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#define PLL_ISO_EN BIT(9) |
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#define FRC_FRC_PWR_ON BIT(10) |
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#define PLL_PWR_ON BIT(11) |
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#define MP_LN_DIG_RX_9C 0xA09C |
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#define FSM_DIFZ_FRC BIT(18) |
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#define MP_LN_DIG_RX_AC 0xA0AC |
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#define FRC_RX_SQ_EN BIT(0) |
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#define RX_SQ_EN BIT(1) |
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#define MP_LN_RX_44 0xB044 |
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#define FRC_CDR_PWR_ON BIT(17) |
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#define CDR_PWR_ON BIT(18) |
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#define FRC_CDR_ISO_EN BIT(19) |
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#define CDR_ISO_EN BIT(20) |
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#define UFSPHY_CLKS_CNT 2 |
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struct ufs_mtk_phy { |
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struct device *dev; |
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void __iomem *mmio; |
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struct clk_bulk_data clks[UFSPHY_CLKS_CNT]; |
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}; |
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static inline u32 mphy_readl(struct ufs_mtk_phy *phy, u32 reg) |
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{ |
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return readl(phy->mmio + reg); |
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} |
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static inline void mphy_writel(struct ufs_mtk_phy *phy, u32 val, u32 reg) |
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{ |
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writel(val, phy->mmio + reg); |
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} |
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static void mphy_set_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit) |
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{ |
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u32 val; |
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val = mphy_readl(phy, reg); |
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val |= bit; |
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mphy_writel(phy, val, reg); |
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} |
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static void mphy_clr_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit) |
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{ |
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u32 val; |
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val = mphy_readl(phy, reg); |
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val &= ~bit; |
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mphy_writel(phy, val, reg); |
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} |
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static struct ufs_mtk_phy *get_ufs_mtk_phy(struct phy *generic_phy) |
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{ |
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return (struct ufs_mtk_phy *)phy_get_drvdata(generic_phy); |
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} |
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static int ufs_mtk_phy_clk_init(struct ufs_mtk_phy *phy) |
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{ |
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struct device *dev = phy->dev; |
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struct clk_bulk_data *clks = phy->clks; |
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clks[0].id = "unipro"; |
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clks[1].id = "mp"; |
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return devm_clk_bulk_get(dev, UFSPHY_CLKS_CNT, clks); |
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} |
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static void ufs_mtk_phy_set_active(struct ufs_mtk_phy *phy) |
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{ |
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/* release DA_MP_PLL_PWR_ON */ |
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mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON); |
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mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON); |
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/* release DA_MP_PLL_ISO_EN */ |
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mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN); |
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mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN); |
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/* release DA_MP_CDR_PWR_ON */ |
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mphy_set_bit(phy, MP_LN_RX_44, CDR_PWR_ON); |
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mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON); |
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/* release DA_MP_CDR_ISO_EN */ |
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mphy_clr_bit(phy, MP_LN_RX_44, CDR_ISO_EN); |
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mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN); |
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/* release DA_MP_RX0_SQ_EN */ |
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mphy_set_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN); |
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mphy_clr_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); |
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/* delay 1us to wait DIFZ stable */ |
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udelay(1); |
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/* release DIFZ */ |
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mphy_clr_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); |
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} |
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static void ufs_mtk_phy_set_deep_hibern(struct ufs_mtk_phy *phy) |
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{ |
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/* force DIFZ */ |
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mphy_set_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); |
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/* force DA_MP_RX0_SQ_EN */ |
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mphy_set_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); |
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mphy_clr_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN); |
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/* force DA_MP_CDR_ISO_EN */ |
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mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN); |
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mphy_set_bit(phy, MP_LN_RX_44, CDR_ISO_EN); |
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/* force DA_MP_CDR_PWR_ON */ |
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mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON); |
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mphy_clr_bit(phy, MP_LN_RX_44, CDR_PWR_ON); |
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/* force DA_MP_PLL_ISO_EN */ |
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mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN); |
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mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN); |
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/* force DA_MP_PLL_PWR_ON */ |
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mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON); |
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mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON); |
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} |
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static int ufs_mtk_phy_power_on(struct phy *generic_phy) |
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{ |
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struct ufs_mtk_phy *phy = get_ufs_mtk_phy(generic_phy); |
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int ret; |
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ret = clk_bulk_prepare_enable(UFSPHY_CLKS_CNT, phy->clks); |
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if (ret) |
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return ret; |
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ufs_mtk_phy_set_active(phy); |
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return 0; |
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} |
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static int ufs_mtk_phy_power_off(struct phy *generic_phy) |
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{ |
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struct ufs_mtk_phy *phy = get_ufs_mtk_phy(generic_phy); |
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ufs_mtk_phy_set_deep_hibern(phy); |
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clk_bulk_disable_unprepare(UFSPHY_CLKS_CNT, phy->clks); |
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return 0; |
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} |
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static const struct phy_ops ufs_mtk_phy_ops = { |
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.power_on = ufs_mtk_phy_power_on, |
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.power_off = ufs_mtk_phy_power_off, |
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.owner = THIS_MODULE, |
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}; |
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static int ufs_mtk_phy_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct phy *generic_phy; |
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struct phy_provider *phy_provider; |
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struct ufs_mtk_phy *phy; |
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int ret; |
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); |
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if (!phy) |
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return -ENOMEM; |
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phy->mmio = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(phy->mmio)) |
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return PTR_ERR(phy->mmio); |
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phy->dev = dev; |
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ret = ufs_mtk_phy_clk_init(phy); |
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if (ret) |
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return ret; |
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generic_phy = devm_phy_create(dev, NULL, &ufs_mtk_phy_ops); |
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if (IS_ERR(generic_phy)) |
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return PTR_ERR(generic_phy); |
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phy_set_drvdata(generic_phy, phy); |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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} |
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static const struct of_device_id ufs_mtk_phy_of_match[] = { |
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{.compatible = "mediatek,mt8183-ufsphy"}, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, ufs_mtk_phy_of_match); |
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static struct platform_driver ufs_mtk_phy_driver = { |
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.probe = ufs_mtk_phy_probe, |
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.driver = { |
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.of_match_table = ufs_mtk_phy_of_match, |
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.name = "ufs_mtk_phy", |
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}, |
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}; |
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module_platform_driver(ufs_mtk_phy_driver); |
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MODULE_DESCRIPTION("Universal Flash Storage (UFS) MediaTek MPHY"); |
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MODULE_AUTHOR("Stanley Chu <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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