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1013 lines
33 KiB
1013 lines
33 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
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*/ |
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#ifndef _CORESIGHT_CORESIGHT_ETM_H |
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#define _CORESIGHT_CORESIGHT_ETM_H |
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#include <asm/local.h> |
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#include <linux/spinlock.h> |
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#include <linux/types.h> |
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#include "coresight-priv.h" |
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/* |
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* Device registers: |
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* 0x000 - 0x2FC: Trace registers |
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* 0x300 - 0x314: Management registers |
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* 0x318 - 0xEFC: Trace registers |
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* 0xF00: Management registers |
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* 0xFA0 - 0xFA4: Trace registers |
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* 0xFA8 - 0xFFC: Management registers |
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*/ |
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/* Trace registers (0x000-0x2FC) */ |
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/* Main control and configuration registers */ |
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#define TRCPRGCTLR 0x004 |
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#define TRCPROCSELR 0x008 |
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#define TRCSTATR 0x00C |
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#define TRCCONFIGR 0x010 |
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#define TRCAUXCTLR 0x018 |
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#define TRCEVENTCTL0R 0x020 |
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#define TRCEVENTCTL1R 0x024 |
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#define TRCRSR 0x028 |
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#define TRCSTALLCTLR 0x02C |
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#define TRCTSCTLR 0x030 |
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#define TRCSYNCPR 0x034 |
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#define TRCCCCTLR 0x038 |
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#define TRCBBCTLR 0x03C |
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#define TRCTRACEIDR 0x040 |
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#define TRCQCTLR 0x044 |
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/* Filtering control registers */ |
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#define TRCVICTLR 0x080 |
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#define TRCVIIECTLR 0x084 |
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#define TRCVISSCTLR 0x088 |
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#define TRCVIPCSSCTLR 0x08C |
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#define TRCVDCTLR 0x0A0 |
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#define TRCVDSACCTLR 0x0A4 |
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#define TRCVDARCCTLR 0x0A8 |
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/* Derived resources registers */ |
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#define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */ |
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#define TRCSEQRSTEVR 0x118 |
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#define TRCSEQSTR 0x11C |
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#define TRCEXTINSELR 0x120 |
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#define TRCEXTINSELRn(n) (0x120 + (n * 4)) /* n = 0-3 */ |
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#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */ |
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#define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */ |
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#define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */ |
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/* ID registers */ |
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#define TRCIDR8 0x180 |
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#define TRCIDR9 0x184 |
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#define TRCIDR10 0x188 |
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#define TRCIDR11 0x18C |
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#define TRCIDR12 0x190 |
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#define TRCIDR13 0x194 |
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#define TRCIMSPEC0 0x1C0 |
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#define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */ |
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#define TRCIDR0 0x1E0 |
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#define TRCIDR1 0x1E4 |
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#define TRCIDR2 0x1E8 |
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#define TRCIDR3 0x1EC |
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#define TRCIDR4 0x1F0 |
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#define TRCIDR5 0x1F4 |
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#define TRCIDR6 0x1F8 |
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#define TRCIDR7 0x1FC |
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/* |
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* Resource selection registers, n = 2-31. |
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* First pair (regs 0, 1) is always present and is reserved. |
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*/ |
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#define TRCRSCTLRn(n) (0x200 + (n * 4)) |
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/* Single-shot comparator registers, n = 0-7 */ |
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#define TRCSSCCRn(n) (0x280 + (n * 4)) |
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#define TRCSSCSRn(n) (0x2A0 + (n * 4)) |
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#define TRCSSPCICRn(n) (0x2C0 + (n * 4)) |
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/* Management registers (0x300-0x314) */ |
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#define TRCOSLAR 0x300 |
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#define TRCOSLSR 0x304 |
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#define TRCPDCR 0x310 |
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#define TRCPDSR 0x314 |
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/* Trace registers (0x318-0xEFC) */ |
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/* Address Comparator registers n = 0-15 */ |
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#define TRCACVRn(n) (0x400 + (n * 8)) |
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#define TRCACATRn(n) (0x480 + (n * 8)) |
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/* Data Value Comparator Value registers, n = 0-7 */ |
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#define TRCDVCVRn(n) (0x500 + (n * 16)) |
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#define TRCDVCMRn(n) (0x580 + (n * 16)) |
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/* ContextID/Virtual ContextID comparators, n = 0-7 */ |
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#define TRCCIDCVRn(n) (0x600 + (n * 8)) |
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#define TRCVMIDCVRn(n) (0x640 + (n * 8)) |
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#define TRCCIDCCTLR0 0x680 |
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#define TRCCIDCCTLR1 0x684 |
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#define TRCVMIDCCTLR0 0x688 |
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#define TRCVMIDCCTLR1 0x68C |
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/* Management register (0xF00) */ |
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/* Integration control registers */ |
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#define TRCITCTRL 0xF00 |
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/* Trace registers (0xFA0-0xFA4) */ |
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/* Claim tag registers */ |
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#define TRCCLAIMSET 0xFA0 |
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#define TRCCLAIMCLR 0xFA4 |
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/* Management registers (0xFA8-0xFFC) */ |
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#define TRCDEVAFF0 0xFA8 |
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#define TRCDEVAFF1 0xFAC |
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#define TRCLAR 0xFB0 |
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#define TRCLSR 0xFB4 |
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#define TRCAUTHSTATUS 0xFB8 |
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#define TRCDEVARCH 0xFBC |
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#define TRCDEVID 0xFC8 |
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#define TRCDEVTYPE 0xFCC |
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#define TRCPIDR4 0xFD0 |
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#define TRCPIDR5 0xFD4 |
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#define TRCPIDR6 0xFD8 |
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#define TRCPIDR7 0xFDC |
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#define TRCPIDR0 0xFE0 |
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#define TRCPIDR1 0xFE4 |
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#define TRCPIDR2 0xFE8 |
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#define TRCPIDR3 0xFEC |
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#define TRCCIDR0 0xFF0 |
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#define TRCCIDR1 0xFF4 |
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#define TRCCIDR2 0xFF8 |
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#define TRCCIDR3 0xFFC |
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#define TRCRSR_TA BIT(12) |
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/* |
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* System instructions to access ETM registers. |
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* See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions |
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*/ |
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#define ETM4x_OFFSET_TO_REG(x) ((x) >> 2) |
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#define ETM4x_CRn(n) (((n) >> 7) & 0x7) |
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#define ETM4x_Op2(n) (((n) >> 4) & 0x7) |
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#define ETM4x_CRm(n) ((n) & 0xf) |
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#include <asm/sysreg.h> |
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#define ETM4x_REG_NUM_TO_SYSREG(n) \ |
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sys_reg(2, 1, ETM4x_CRn(n), ETM4x_CRm(n), ETM4x_Op2(n)) |
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#define READ_ETM4x_REG(reg) \ |
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read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg))) |
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#define WRITE_ETM4x_REG(val, reg) \ |
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write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg))) |
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#define read_etm4x_sysreg_const_offset(offset) \ |
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READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset)) |
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#define write_etm4x_sysreg_const_offset(val, offset) \ |
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WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset)) |
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#define CASE_READ(res, x) \ |
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case (x): { (res) = read_etm4x_sysreg_const_offset((x)); break; } |
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#define CASE_WRITE(val, x) \ |
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case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; } |
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#define CASE_NOP(__unused, x) \ |
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case (x): /* fall through */ |
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#define ETE_ONLY_SYSREG_LIST(op, val) \ |
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CASE_##op((val), TRCRSR) \ |
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CASE_##op((val), TRCEXTINSELRn(1)) \ |
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CASE_##op((val), TRCEXTINSELRn(2)) \ |
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CASE_##op((val), TRCEXTINSELRn(3)) |
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/* List of registers accessible via System instructions */ |
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#define ETM4x_ONLY_SYSREG_LIST(op, val) \ |
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CASE_##op((val), TRCPROCSELR) \ |
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CASE_##op((val), TRCVDCTLR) \ |
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CASE_##op((val), TRCVDSACCTLR) \ |
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CASE_##op((val), TRCVDARCCTLR) \ |
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CASE_##op((val), TRCOSLAR) |
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#define ETM_COMMON_SYSREG_LIST(op, val) \ |
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CASE_##op((val), TRCPRGCTLR) \ |
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CASE_##op((val), TRCSTATR) \ |
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CASE_##op((val), TRCCONFIGR) \ |
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CASE_##op((val), TRCAUXCTLR) \ |
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CASE_##op((val), TRCEVENTCTL0R) \ |
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CASE_##op((val), TRCEVENTCTL1R) \ |
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CASE_##op((val), TRCSTALLCTLR) \ |
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CASE_##op((val), TRCTSCTLR) \ |
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CASE_##op((val), TRCSYNCPR) \ |
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CASE_##op((val), TRCCCCTLR) \ |
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CASE_##op((val), TRCBBCTLR) \ |
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CASE_##op((val), TRCTRACEIDR) \ |
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CASE_##op((val), TRCQCTLR) \ |
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CASE_##op((val), TRCVICTLR) \ |
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CASE_##op((val), TRCVIIECTLR) \ |
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CASE_##op((val), TRCVISSCTLR) \ |
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CASE_##op((val), TRCVIPCSSCTLR) \ |
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CASE_##op((val), TRCSEQEVRn(0)) \ |
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CASE_##op((val), TRCSEQEVRn(1)) \ |
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CASE_##op((val), TRCSEQEVRn(2)) \ |
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CASE_##op((val), TRCSEQRSTEVR) \ |
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CASE_##op((val), TRCSEQSTR) \ |
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CASE_##op((val), TRCEXTINSELR) \ |
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CASE_##op((val), TRCCNTRLDVRn(0)) \ |
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CASE_##op((val), TRCCNTRLDVRn(1)) \ |
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CASE_##op((val), TRCCNTRLDVRn(2)) \ |
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CASE_##op((val), TRCCNTRLDVRn(3)) \ |
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CASE_##op((val), TRCCNTCTLRn(0)) \ |
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CASE_##op((val), TRCCNTCTLRn(1)) \ |
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CASE_##op((val), TRCCNTCTLRn(2)) \ |
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CASE_##op((val), TRCCNTCTLRn(3)) \ |
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CASE_##op((val), TRCCNTVRn(0)) \ |
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CASE_##op((val), TRCCNTVRn(1)) \ |
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CASE_##op((val), TRCCNTVRn(2)) \ |
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CASE_##op((val), TRCCNTVRn(3)) \ |
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CASE_##op((val), TRCIDR8) \ |
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CASE_##op((val), TRCIDR9) \ |
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CASE_##op((val), TRCIDR10) \ |
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CASE_##op((val), TRCIDR11) \ |
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CASE_##op((val), TRCIDR12) \ |
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CASE_##op((val), TRCIDR13) \ |
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CASE_##op((val), TRCIMSPECn(0)) \ |
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CASE_##op((val), TRCIMSPECn(1)) \ |
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CASE_##op((val), TRCIMSPECn(2)) \ |
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CASE_##op((val), TRCIMSPECn(3)) \ |
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CASE_##op((val), TRCIMSPECn(4)) \ |
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CASE_##op((val), TRCIMSPECn(5)) \ |
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CASE_##op((val), TRCIMSPECn(6)) \ |
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CASE_##op((val), TRCIMSPECn(7)) \ |
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CASE_##op((val), TRCIDR0) \ |
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CASE_##op((val), TRCIDR1) \ |
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CASE_##op((val), TRCIDR2) \ |
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CASE_##op((val), TRCIDR3) \ |
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CASE_##op((val), TRCIDR4) \ |
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CASE_##op((val), TRCIDR5) \ |
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CASE_##op((val), TRCIDR6) \ |
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CASE_##op((val), TRCIDR7) \ |
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CASE_##op((val), TRCRSCTLRn(2)) \ |
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CASE_##op((val), TRCRSCTLRn(3)) \ |
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CASE_##op((val), TRCRSCTLRn(4)) \ |
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CASE_##op((val), TRCRSCTLRn(5)) \ |
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CASE_##op((val), TRCRSCTLRn(6)) \ |
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CASE_##op((val), TRCRSCTLRn(7)) \ |
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CASE_##op((val), TRCRSCTLRn(8)) \ |
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CASE_##op((val), TRCRSCTLRn(9)) \ |
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CASE_##op((val), TRCRSCTLRn(10)) \ |
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CASE_##op((val), TRCRSCTLRn(11)) \ |
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CASE_##op((val), TRCRSCTLRn(12)) \ |
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CASE_##op((val), TRCRSCTLRn(13)) \ |
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CASE_##op((val), TRCRSCTLRn(14)) \ |
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CASE_##op((val), TRCRSCTLRn(15)) \ |
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CASE_##op((val), TRCRSCTLRn(16)) \ |
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CASE_##op((val), TRCRSCTLRn(17)) \ |
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CASE_##op((val), TRCRSCTLRn(18)) \ |
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CASE_##op((val), TRCRSCTLRn(19)) \ |
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CASE_##op((val), TRCRSCTLRn(20)) \ |
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CASE_##op((val), TRCRSCTLRn(21)) \ |
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CASE_##op((val), TRCRSCTLRn(22)) \ |
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CASE_##op((val), TRCRSCTLRn(23)) \ |
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CASE_##op((val), TRCRSCTLRn(24)) \ |
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CASE_##op((val), TRCRSCTLRn(25)) \ |
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CASE_##op((val), TRCRSCTLRn(26)) \ |
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CASE_##op((val), TRCRSCTLRn(27)) \ |
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CASE_##op((val), TRCRSCTLRn(28)) \ |
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CASE_##op((val), TRCRSCTLRn(29)) \ |
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CASE_##op((val), TRCRSCTLRn(30)) \ |
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CASE_##op((val), TRCRSCTLRn(31)) \ |
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CASE_##op((val), TRCSSCCRn(0)) \ |
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CASE_##op((val), TRCSSCCRn(1)) \ |
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CASE_##op((val), TRCSSCCRn(2)) \ |
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CASE_##op((val), TRCSSCCRn(3)) \ |
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CASE_##op((val), TRCSSCCRn(4)) \ |
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CASE_##op((val), TRCSSCCRn(5)) \ |
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CASE_##op((val), TRCSSCCRn(6)) \ |
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CASE_##op((val), TRCSSCCRn(7)) \ |
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CASE_##op((val), TRCSSCSRn(0)) \ |
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CASE_##op((val), TRCSSCSRn(1)) \ |
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CASE_##op((val), TRCSSCSRn(2)) \ |
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CASE_##op((val), TRCSSCSRn(3)) \ |
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CASE_##op((val), TRCSSCSRn(4)) \ |
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CASE_##op((val), TRCSSCSRn(5)) \ |
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CASE_##op((val), TRCSSCSRn(6)) \ |
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CASE_##op((val), TRCSSCSRn(7)) \ |
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CASE_##op((val), TRCSSPCICRn(0)) \ |
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CASE_##op((val), TRCSSPCICRn(1)) \ |
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CASE_##op((val), TRCSSPCICRn(2)) \ |
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CASE_##op((val), TRCSSPCICRn(3)) \ |
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CASE_##op((val), TRCSSPCICRn(4)) \ |
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CASE_##op((val), TRCSSPCICRn(5)) \ |
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CASE_##op((val), TRCSSPCICRn(6)) \ |
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CASE_##op((val), TRCSSPCICRn(7)) \ |
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CASE_##op((val), TRCOSLSR) \ |
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CASE_##op((val), TRCACVRn(0)) \ |
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CASE_##op((val), TRCACVRn(1)) \ |
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CASE_##op((val), TRCACVRn(2)) \ |
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CASE_##op((val), TRCACVRn(3)) \ |
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CASE_##op((val), TRCACVRn(4)) \ |
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CASE_##op((val), TRCACVRn(5)) \ |
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CASE_##op((val), TRCACVRn(6)) \ |
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CASE_##op((val), TRCACVRn(7)) \ |
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CASE_##op((val), TRCACVRn(8)) \ |
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CASE_##op((val), TRCACVRn(9)) \ |
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CASE_##op((val), TRCACVRn(10)) \ |
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CASE_##op((val), TRCACVRn(11)) \ |
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CASE_##op((val), TRCACVRn(12)) \ |
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CASE_##op((val), TRCACVRn(13)) \ |
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CASE_##op((val), TRCACVRn(14)) \ |
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CASE_##op((val), TRCACVRn(15)) \ |
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CASE_##op((val), TRCACATRn(0)) \ |
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CASE_##op((val), TRCACATRn(1)) \ |
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CASE_##op((val), TRCACATRn(2)) \ |
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CASE_##op((val), TRCACATRn(3)) \ |
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CASE_##op((val), TRCACATRn(4)) \ |
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CASE_##op((val), TRCACATRn(5)) \ |
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CASE_##op((val), TRCACATRn(6)) \ |
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CASE_##op((val), TRCACATRn(7)) \ |
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CASE_##op((val), TRCACATRn(8)) \ |
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CASE_##op((val), TRCACATRn(9)) \ |
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CASE_##op((val), TRCACATRn(10)) \ |
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CASE_##op((val), TRCACATRn(11)) \ |
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CASE_##op((val), TRCACATRn(12)) \ |
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CASE_##op((val), TRCACATRn(13)) \ |
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CASE_##op((val), TRCACATRn(14)) \ |
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CASE_##op((val), TRCACATRn(15)) \ |
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CASE_##op((val), TRCDVCVRn(0)) \ |
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CASE_##op((val), TRCDVCVRn(1)) \ |
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CASE_##op((val), TRCDVCVRn(2)) \ |
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CASE_##op((val), TRCDVCVRn(3)) \ |
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CASE_##op((val), TRCDVCVRn(4)) \ |
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CASE_##op((val), TRCDVCVRn(5)) \ |
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CASE_##op((val), TRCDVCVRn(6)) \ |
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CASE_##op((val), TRCDVCVRn(7)) \ |
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CASE_##op((val), TRCDVCMRn(0)) \ |
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CASE_##op((val), TRCDVCMRn(1)) \ |
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CASE_##op((val), TRCDVCMRn(2)) \ |
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CASE_##op((val), TRCDVCMRn(3)) \ |
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CASE_##op((val), TRCDVCMRn(4)) \ |
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CASE_##op((val), TRCDVCMRn(5)) \ |
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CASE_##op((val), TRCDVCMRn(6)) \ |
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CASE_##op((val), TRCDVCMRn(7)) \ |
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CASE_##op((val), TRCCIDCVRn(0)) \ |
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CASE_##op((val), TRCCIDCVRn(1)) \ |
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CASE_##op((val), TRCCIDCVRn(2)) \ |
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CASE_##op((val), TRCCIDCVRn(3)) \ |
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CASE_##op((val), TRCCIDCVRn(4)) \ |
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CASE_##op((val), TRCCIDCVRn(5)) \ |
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CASE_##op((val), TRCCIDCVRn(6)) \ |
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CASE_##op((val), TRCCIDCVRn(7)) \ |
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CASE_##op((val), TRCVMIDCVRn(0)) \ |
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CASE_##op((val), TRCVMIDCVRn(1)) \ |
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CASE_##op((val), TRCVMIDCVRn(2)) \ |
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CASE_##op((val), TRCVMIDCVRn(3)) \ |
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CASE_##op((val), TRCVMIDCVRn(4)) \ |
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CASE_##op((val), TRCVMIDCVRn(5)) \ |
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CASE_##op((val), TRCVMIDCVRn(6)) \ |
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CASE_##op((val), TRCVMIDCVRn(7)) \ |
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CASE_##op((val), TRCCIDCCTLR0) \ |
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CASE_##op((val), TRCCIDCCTLR1) \ |
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CASE_##op((val), TRCVMIDCCTLR0) \ |
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CASE_##op((val), TRCVMIDCCTLR1) \ |
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CASE_##op((val), TRCCLAIMSET) \ |
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CASE_##op((val), TRCCLAIMCLR) \ |
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CASE_##op((val), TRCAUTHSTATUS) \ |
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CASE_##op((val), TRCDEVARCH) \ |
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CASE_##op((val), TRCDEVID) |
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/* List of registers only accessible via memory-mapped interface */ |
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#define ETM_MMAP_LIST(op, val) \ |
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CASE_##op((val), TRCDEVTYPE) \ |
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CASE_##op((val), TRCPDCR) \ |
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CASE_##op((val), TRCPDSR) \ |
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CASE_##op((val), TRCDEVAFF0) \ |
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CASE_##op((val), TRCDEVAFF1) \ |
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CASE_##op((val), TRCLAR) \ |
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CASE_##op((val), TRCLSR) \ |
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CASE_##op((val), TRCITCTRL) \ |
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CASE_##op((val), TRCPIDR4) \ |
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CASE_##op((val), TRCPIDR0) \ |
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CASE_##op((val), TRCPIDR1) \ |
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CASE_##op((val), TRCPIDR2) \ |
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CASE_##op((val), TRCPIDR3) |
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#define ETM4x_READ_SYSREG_CASES(res) \ |
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ETM_COMMON_SYSREG_LIST(READ, (res)) \ |
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ETM4x_ONLY_SYSREG_LIST(READ, (res)) |
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#define ETM4x_WRITE_SYSREG_CASES(val) \ |
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ETM_COMMON_SYSREG_LIST(WRITE, (val)) \ |
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ETM4x_ONLY_SYSREG_LIST(WRITE, (val)) |
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#define ETM_COMMON_SYSREG_LIST_CASES \ |
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ETM_COMMON_SYSREG_LIST(NOP, __unused) |
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#define ETM4x_ONLY_SYSREG_LIST_CASES \ |
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ETM4x_ONLY_SYSREG_LIST(NOP, __unused) |
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#define ETM4x_SYSREG_LIST_CASES \ |
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ETM_COMMON_SYSREG_LIST_CASES \ |
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ETM4x_ONLY_SYSREG_LIST(NOP, __unused) |
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#define ETM4x_MMAP_LIST_CASES ETM_MMAP_LIST(NOP, __unused) |
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/* ETE only supports system register access */ |
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#define ETE_READ_CASES(res) \ |
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ETM_COMMON_SYSREG_LIST(READ, (res)) \ |
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ETE_ONLY_SYSREG_LIST(READ, (res)) |
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#define ETE_WRITE_CASES(val) \ |
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ETM_COMMON_SYSREG_LIST(WRITE, (val)) \ |
|
ETE_ONLY_SYSREG_LIST(WRITE, (val)) |
|
|
|
#define ETE_ONLY_SYSREG_LIST_CASES \ |
|
ETE_ONLY_SYSREG_LIST(NOP, __unused) |
|
|
|
#define read_etm4x_sysreg_offset(offset, _64bit) \ |
|
({ \ |
|
u64 __val; \ |
|
\ |
|
if (__builtin_constant_p((offset))) \ |
|
__val = read_etm4x_sysreg_const_offset((offset)); \ |
|
else \ |
|
__val = etm4x_sysreg_read((offset), true, (_64bit)); \ |
|
__val; \ |
|
}) |
|
|
|
#define write_etm4x_sysreg_offset(val, offset, _64bit) \ |
|
do { \ |
|
if (__builtin_constant_p((offset))) \ |
|
write_etm4x_sysreg_const_offset((val), \ |
|
(offset)); \ |
|
else \ |
|
etm4x_sysreg_write((val), (offset), true, \ |
|
(_64bit)); \ |
|
} while (0) |
|
|
|
|
|
#define etm4x_relaxed_read32(csa, offset) \ |
|
((u32)((csa)->io_mem ? \ |
|
readl_relaxed((csa)->base + (offset)) : \ |
|
read_etm4x_sysreg_offset((offset), false))) |
|
|
|
#define etm4x_relaxed_read64(csa, offset) \ |
|
((u64)((csa)->io_mem ? \ |
|
readq_relaxed((csa)->base + (offset)) : \ |
|
read_etm4x_sysreg_offset((offset), true))) |
|
|
|
#define etm4x_read32(csa, offset) \ |
|
({ \ |
|
u32 __val = etm4x_relaxed_read32((csa), (offset)); \ |
|
__iormb(__val); \ |
|
__val; \ |
|
}) |
|
|
|
#define etm4x_read64(csa, offset) \ |
|
({ \ |
|
u64 __val = etm4x_relaxed_read64((csa), (offset)); \ |
|
__iormb(__val); \ |
|
__val; \ |
|
}) |
|
|
|
#define etm4x_relaxed_write32(csa, val, offset) \ |
|
do { \ |
|
if ((csa)->io_mem) \ |
|
writel_relaxed((val), (csa)->base + (offset)); \ |
|
else \ |
|
write_etm4x_sysreg_offset((val), (offset), \ |
|
false); \ |
|
} while (0) |
|
|
|
#define etm4x_relaxed_write64(csa, val, offset) \ |
|
do { \ |
|
if ((csa)->io_mem) \ |
|
writeq_relaxed((val), (csa)->base + (offset)); \ |
|
else \ |
|
write_etm4x_sysreg_offset((val), (offset), \ |
|
true); \ |
|
} while (0) |
|
|
|
#define etm4x_write32(csa, val, offset) \ |
|
do { \ |
|
__iowmb(); \ |
|
etm4x_relaxed_write32((csa), (val), (offset)); \ |
|
} while (0) |
|
|
|
#define etm4x_write64(csa, val, offset) \ |
|
do { \ |
|
__iowmb(); \ |
|
etm4x_relaxed_write64((csa), (val), (offset)); \ |
|
} while (0) |
|
|
|
|
|
/* ETMv4 resources */ |
|
#define ETM_MAX_NR_PE 8 |
|
#define ETMv4_MAX_CNTR 4 |
|
#define ETM_MAX_SEQ_STATES 4 |
|
#define ETM_MAX_EXT_INP_SEL 4 |
|
#define ETM_MAX_EXT_INP 256 |
|
#define ETM_MAX_EXT_OUT 4 |
|
#define ETM_MAX_SINGLE_ADDR_CMP 16 |
|
#define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2) |
|
#define ETM_MAX_DATA_VAL_CMP 8 |
|
#define ETMv4_MAX_CTXID_CMP 8 |
|
#define ETM_MAX_VMID_CMP 8 |
|
#define ETM_MAX_PE_CMP 8 |
|
#define ETM_MAX_RES_SEL 32 |
|
#define ETM_MAX_SS_CMP 8 |
|
|
|
#define ETMv4_SYNC_MASK 0x1F |
|
#define ETM_CYC_THRESHOLD_MASK 0xFFF |
|
#define ETM_CYC_THRESHOLD_DEFAULT 0x100 |
|
#define ETMv4_EVENT_MASK 0xFF |
|
#define ETM_CNTR_MAX_VAL 0xFFFF |
|
#define ETM_TRACEID_MASK 0x3f |
|
|
|
/* ETMv4 programming modes */ |
|
#define ETM_MODE_EXCLUDE BIT(0) |
|
#define ETM_MODE_LOAD BIT(1) |
|
#define ETM_MODE_STORE BIT(2) |
|
#define ETM_MODE_LOAD_STORE BIT(3) |
|
#define ETM_MODE_BB BIT(4) |
|
#define ETMv4_MODE_CYCACC BIT(5) |
|
#define ETMv4_MODE_CTXID BIT(6) |
|
#define ETM_MODE_VMID BIT(7) |
|
#define ETM_MODE_COND(val) BMVAL(val, 8, 10) |
|
#define ETMv4_MODE_TIMESTAMP BIT(11) |
|
#define ETM_MODE_RETURNSTACK BIT(12) |
|
#define ETM_MODE_QELEM(val) BMVAL(val, 13, 14) |
|
#define ETM_MODE_DATA_TRACE_ADDR BIT(15) |
|
#define ETM_MODE_DATA_TRACE_VAL BIT(16) |
|
#define ETM_MODE_ISTALL BIT(17) |
|
#define ETM_MODE_DSTALL BIT(18) |
|
#define ETM_MODE_ATB_TRIGGER BIT(19) |
|
#define ETM_MODE_LPOVERRIDE BIT(20) |
|
#define ETM_MODE_ISTALL_EN BIT(21) |
|
#define ETM_MODE_DSTALL_EN BIT(22) |
|
#define ETM_MODE_INSTPRIO BIT(23) |
|
#define ETM_MODE_NOOVERFLOW BIT(24) |
|
#define ETM_MODE_TRACE_RESET BIT(25) |
|
#define ETM_MODE_TRACE_ERR BIT(26) |
|
#define ETM_MODE_VIEWINST_STARTSTOP BIT(27) |
|
#define ETMv4_MODE_ALL (GENMASK(27, 0) | \ |
|
ETM_MODE_EXCL_KERN | \ |
|
ETM_MODE_EXCL_USER) |
|
|
|
/* |
|
* TRCOSLSR.OSLM advertises the OS Lock model. |
|
* OSLM[2:0] = TRCOSLSR[4:3,0] |
|
* |
|
* 0b000 - Trace OS Lock is not implemented. |
|
* 0b010 - Trace OS Lock is implemented. |
|
* 0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock. |
|
*/ |
|
#define ETM_OSLOCK_NI 0b000 |
|
#define ETM_OSLOCK_PRESENT 0b010 |
|
#define ETM_OSLOCK_PE 0b100 |
|
|
|
#define ETM_OSLSR_OSLM(oslsr) ((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1)) |
|
|
|
/* |
|
* TRCDEVARCH Bit field definitions |
|
* Bits[31:21] - ARCHITECT = Always Arm Ltd. |
|
* * Bits[31:28] = 0x4 |
|
* * Bits[27:21] = 0b0111011 |
|
* Bit[20] - PRESENT, Indicates the presence of this register. |
|
* |
|
* Bit[19:16] - REVISION, Revision of the architecture. |
|
* |
|
* Bit[15:0] - ARCHID, Identifies this component as an ETM |
|
* * Bits[15:12] - architecture version of ETM |
|
* * = 4 for ETMv4 |
|
* * Bits[11:0] = 0xA13, architecture part number for ETM. |
|
*/ |
|
#define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21) |
|
#define ETM_DEVARCH_ARCHITECT_ARM ((0x4 << 28) | (0b0111011 << 21)) |
|
#define ETM_DEVARCH_PRESENT BIT(20) |
|
#define ETM_DEVARCH_REVISION_SHIFT 16 |
|
#define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16) |
|
#define ETM_DEVARCH_REVISION(x) \ |
|
(((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT) |
|
#define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0) |
|
#define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT 12 |
|
#define ETM_DEVARCH_ARCHID_ARCH_VER_MASK GENMASK(15, 12) |
|
#define ETM_DEVARCH_ARCHID_ARCH_VER(x) \ |
|
(((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) |
|
|
|
#define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver) \ |
|
(((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) |
|
|
|
#define ETM_DEVARCH_ARCHID_ARCH_PART(x) ((x) & 0xfffUL) |
|
|
|
#define ETM_DEVARCH_MAKE_ARCHID(major) \ |
|
((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13)) |
|
|
|
#define ETM_DEVARCH_ARCHID_ETMv4x ETM_DEVARCH_MAKE_ARCHID(0x4) |
|
#define ETM_DEVARCH_ARCHID_ETE ETM_DEVARCH_MAKE_ARCHID(0x5) |
|
|
|
#define ETM_DEVARCH_ID_MASK \ |
|
(ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT) |
|
#define ETM_DEVARCH_ETMv4x_ARCH \ |
|
(ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT) |
|
#define ETM_DEVARCH_ETE_ARCH \ |
|
(ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT) |
|
|
|
#define TRCSTATR_IDLE_BIT 0 |
|
#define TRCSTATR_PMSTABLE_BIT 1 |
|
#define ETM_DEFAULT_ADDR_COMP 0 |
|
|
|
#define TRCSSCSRn_PC BIT(3) |
|
|
|
/* PowerDown Control Register bits */ |
|
#define TRCPDCR_PU BIT(3) |
|
|
|
#define TRCACATR_EXLEVEL_SHIFT 8 |
|
|
|
/* |
|
* Exception level mask for Secure and Non-Secure ELs. |
|
* ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn). |
|
* The Secure and Non-Secure ELs are always to gether. |
|
* Non-secure EL3 is never implemented. |
|
* We use the following generic mask as they appear in different |
|
* registers and this can be shifted for the appropriate |
|
* fields. |
|
*/ |
|
#define ETM_EXLEVEL_S_APP BIT(0) /* Secure EL0 */ |
|
#define ETM_EXLEVEL_S_OS BIT(1) /* Secure EL1 */ |
|
#define ETM_EXLEVEL_S_HYP BIT(2) /* Secure EL2 */ |
|
#define ETM_EXLEVEL_S_MON BIT(3) /* Secure EL3/Monitor */ |
|
#define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */ |
|
#define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */ |
|
#define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */ |
|
|
|
#define ETM_EXLEVEL_MASK (GENMASK(6, 0)) |
|
#define ETM_EXLEVEL_S_MASK (GENMASK(3, 0)) |
|
#define ETM_EXLEVEL_NS_MASK (GENMASK(6, 4)) |
|
|
|
/* access level controls in TRCACATRn */ |
|
#define TRCACATR_EXLEVEL_SHIFT 8 |
|
|
|
/* access level control in TRCVICTLR */ |
|
#define TRCVICTLR_EXLEVEL_SHIFT 16 |
|
#define TRCVICTLR_EXLEVEL_S_SHIFT 16 |
|
#define TRCVICTLR_EXLEVEL_NS_SHIFT 20 |
|
|
|
/* secure / non secure masks - TRCVICTLR, IDR3 */ |
|
#define TRCVICTLR_EXLEVEL_MASK (ETM_EXLEVEL_MASK << TRCVICTLR_EXLEVEL_SHIFT) |
|
#define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_SHIFT) |
|
#define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_SHIFT) |
|
|
|
#define ETM_TRCIDR1_ARCH_MAJOR_SHIFT 8 |
|
#define ETM_TRCIDR1_ARCH_MAJOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT) |
|
#define ETM_TRCIDR1_ARCH_MAJOR(x) \ |
|
(((x) & ETM_TRCIDR1_ARCH_MAJOR_MASK) >> ETM_TRCIDR1_ARCH_MAJOR_SHIFT) |
|
#define ETM_TRCIDR1_ARCH_MINOR_SHIFT 4 |
|
#define ETM_TRCIDR1_ARCH_MINOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MINOR_SHIFT) |
|
#define ETM_TRCIDR1_ARCH_MINOR(x) \ |
|
(((x) & ETM_TRCIDR1_ARCH_MINOR_MASK) >> ETM_TRCIDR1_ARCH_MINOR_SHIFT) |
|
#define ETM_TRCIDR1_ARCH_SHIFT ETM_TRCIDR1_ARCH_MINOR_SHIFT |
|
#define ETM_TRCIDR1_ARCH_MASK \ |
|
(ETM_TRCIDR1_ARCH_MAJOR_MASK | ETM_TRCIDR1_ARCH_MINOR_MASK) |
|
|
|
#define ETM_TRCIDR1_ARCH_ETMv4 0x4 |
|
|
|
/* |
|
* Driver representation of the ETM architecture. |
|
* The version of an ETM component can be detected from |
|
* |
|
* TRCDEVARCH - CoreSight architected register |
|
* - Bits[15:12] - Major version |
|
* - Bits[19:16] - Minor version |
|
* TRCIDR1 - ETM architected register |
|
* - Bits[11:8] - Major version |
|
* - Bits[7:4] - Minor version |
|
* We must rely on TRCDEVARCH for the version information, |
|
* however we don't want to break the support for potential |
|
* old implementations which might not implement it. Thus |
|
* we fall back to TRCIDR1 if TRCDEVARCH is not implemented |
|
* for memory mapped components. |
|
* Now to make certain decisions easier based on the version |
|
* we use an internal representation of the version in the |
|
* driver, as follows : |
|
* |
|
* ETM_ARCH_VERSION[7:0], where : |
|
* Bits[7:4] - Major version |
|
* Bits[3:0] - Minro version |
|
*/ |
|
#define ETM_ARCH_VERSION(major, minor) \ |
|
((((major) & 0xfU) << 4) | (((minor) & 0xfU))) |
|
#define ETM_ARCH_MAJOR_VERSION(arch) (((arch) >> 4) & 0xfU) |
|
#define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU) |
|
|
|
#define ETM_ARCH_V4 ETM_ARCH_VERSION(4, 0) |
|
#define ETM_ARCH_ETE ETM_ARCH_VERSION(5, 0) |
|
|
|
/* Interpretation of resource numbers change at ETM v4.3 architecture */ |
|
#define ETM_ARCH_V4_3 ETM_ARCH_VERSION(4, 3) |
|
|
|
static inline u8 etm_devarch_to_arch(u32 devarch) |
|
{ |
|
return ETM_ARCH_VERSION(ETM_DEVARCH_ARCHID_ARCH_VER(devarch), |
|
ETM_DEVARCH_REVISION(devarch)); |
|
} |
|
|
|
static inline u8 etm_trcidr_to_arch(u32 trcidr1) |
|
{ |
|
return ETM_ARCH_VERSION(ETM_TRCIDR1_ARCH_MAJOR(trcidr1), |
|
ETM_TRCIDR1_ARCH_MINOR(trcidr1)); |
|
} |
|
|
|
enum etm_impdef_type { |
|
ETM4_IMPDEF_HISI_CORE_COMMIT, |
|
ETM4_IMPDEF_FEATURE_MAX, |
|
}; |
|
|
|
/** |
|
* struct etmv4_config - configuration information related to an ETMv4 |
|
* @mode: Controls various modes supported by this ETM. |
|
* @pe_sel: Controls which PE to trace. |
|
* @cfg: Controls the tracing options. |
|
* @eventctrl0: Controls the tracing of arbitrary events. |
|
* @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects. |
|
* @stallctl: If functionality that prevents trace unit buffer overflows |
|
* is available. |
|
* @ts_ctrl: Controls the insertion of global timestamps in the |
|
* trace streams. |
|
* @syncfreq: Controls how often trace synchronization requests occur. |
|
* the TRCCCCTLR register. |
|
* @ccctlr: Sets the threshold value for cycle counting. |
|
* @vinst_ctrl: Controls instruction trace filtering. |
|
* @viiectlr: Set or read, the address range comparators. |
|
* @vissctlr: Set, or read, the single address comparators that control the |
|
* ViewInst start-stop logic. |
|
* @vipcssctlr: Set, or read, which PE comparator inputs can control the |
|
* ViewInst start-stop logic. |
|
* @seq_idx: Sequencor index selector. |
|
* @seq_ctrl: Control for the sequencer state transition control register. |
|
* @seq_rst: Moves the sequencer to state 0 when a programmed event occurs. |
|
* @seq_state: Set, or read the sequencer state. |
|
* @cntr_idx: Counter index seletor. |
|
* @cntrldvr: Sets or returns the reload count value for a counter. |
|
* @cntr_ctrl: Controls the operation of a counter. |
|
* @cntr_val: Sets or returns the value for a counter. |
|
* @res_idx: Resource index selector. |
|
* @res_ctrl: Controls the selection of the resources in the trace unit. |
|
* @ss_idx: Single-shot index selector. |
|
* @ss_ctrl: Controls the corresponding single-shot comparator resource. |
|
* @ss_status: The status of the corresponding single-shot comparator. |
|
* @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control. |
|
* @addr_idx: Address comparator index selector. |
|
* @addr_val: Value for address comparator. |
|
* @addr_acc: Address comparator access type. |
|
* @addr_type: Current status of the comparator register. |
|
* @ctxid_idx: Context ID index selector. |
|
* @ctxid_pid: Value of the context ID comparator. |
|
* @ctxid_mask0:Context ID comparator mask for comparator 0-3. |
|
* @ctxid_mask1:Context ID comparator mask for comparator 4-7. |
|
* @vmid_idx: VM ID index selector. |
|
* @vmid_val: Value of the VM ID comparator. |
|
* @vmid_mask0: VM ID comparator mask for comparator 0-3. |
|
* @vmid_mask1: VM ID comparator mask for comparator 4-7. |
|
* @ext_inp: External input selection. |
|
* @s_ex_level: Secure ELs where tracing is supported. |
|
*/ |
|
struct etmv4_config { |
|
u32 mode; |
|
u32 pe_sel; |
|
u32 cfg; |
|
u32 eventctrl0; |
|
u32 eventctrl1; |
|
u32 stall_ctrl; |
|
u32 ts_ctrl; |
|
u32 syncfreq; |
|
u32 ccctlr; |
|
u32 bb_ctrl; |
|
u32 vinst_ctrl; |
|
u32 viiectlr; |
|
u32 vissctlr; |
|
u32 vipcssctlr; |
|
u8 seq_idx; |
|
u32 seq_ctrl[ETM_MAX_SEQ_STATES]; |
|
u32 seq_rst; |
|
u32 seq_state; |
|
u8 cntr_idx; |
|
u32 cntrldvr[ETMv4_MAX_CNTR]; |
|
u32 cntr_ctrl[ETMv4_MAX_CNTR]; |
|
u32 cntr_val[ETMv4_MAX_CNTR]; |
|
u8 res_idx; |
|
u32 res_ctrl[ETM_MAX_RES_SEL]; |
|
u8 ss_idx; |
|
u32 ss_ctrl[ETM_MAX_SS_CMP]; |
|
u32 ss_status[ETM_MAX_SS_CMP]; |
|
u32 ss_pe_cmp[ETM_MAX_SS_CMP]; |
|
u8 addr_idx; |
|
u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP]; |
|
u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP]; |
|
u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP]; |
|
u8 ctxid_idx; |
|
u64 ctxid_pid[ETMv4_MAX_CTXID_CMP]; |
|
u32 ctxid_mask0; |
|
u32 ctxid_mask1; |
|
u8 vmid_idx; |
|
u64 vmid_val[ETM_MAX_VMID_CMP]; |
|
u32 vmid_mask0; |
|
u32 vmid_mask1; |
|
u32 ext_inp; |
|
u8 s_ex_level; |
|
}; |
|
|
|
/** |
|
* struct etm4_save_state - state to be preserved when ETM is without power |
|
*/ |
|
struct etmv4_save_state { |
|
u32 trcprgctlr; |
|
u32 trcprocselr; |
|
u32 trcconfigr; |
|
u32 trcauxctlr; |
|
u32 trceventctl0r; |
|
u32 trceventctl1r; |
|
u32 trcstallctlr; |
|
u32 trctsctlr; |
|
u32 trcsyncpr; |
|
u32 trcccctlr; |
|
u32 trcbbctlr; |
|
u32 trctraceidr; |
|
u32 trcqctlr; |
|
|
|
u32 trcvictlr; |
|
u32 trcviiectlr; |
|
u32 trcvissctlr; |
|
u32 trcvipcssctlr; |
|
u32 trcvdctlr; |
|
u32 trcvdsacctlr; |
|
u32 trcvdarcctlr; |
|
|
|
u32 trcseqevr[ETM_MAX_SEQ_STATES]; |
|
u32 trcseqrstevr; |
|
u32 trcseqstr; |
|
u32 trcextinselr; |
|
u32 trccntrldvr[ETMv4_MAX_CNTR]; |
|
u32 trccntctlr[ETMv4_MAX_CNTR]; |
|
u32 trccntvr[ETMv4_MAX_CNTR]; |
|
|
|
u32 trcrsctlr[ETM_MAX_RES_SEL]; |
|
|
|
u32 trcssccr[ETM_MAX_SS_CMP]; |
|
u32 trcsscsr[ETM_MAX_SS_CMP]; |
|
u32 trcsspcicr[ETM_MAX_SS_CMP]; |
|
|
|
u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP]; |
|
u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP]; |
|
u64 trccidcvr[ETMv4_MAX_CTXID_CMP]; |
|
u64 trcvmidcvr[ETM_MAX_VMID_CMP]; |
|
u32 trccidcctlr0; |
|
u32 trccidcctlr1; |
|
u32 trcvmidcctlr0; |
|
u32 trcvmidcctlr1; |
|
|
|
u32 trcclaimset; |
|
|
|
u32 cntr_val[ETMv4_MAX_CNTR]; |
|
u32 seq_state; |
|
u32 vinst_ctrl; |
|
u32 ss_status[ETM_MAX_SS_CMP]; |
|
|
|
u32 trcpdcr; |
|
}; |
|
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/** |
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* struct etm4_drvdata - specifics associated to an ETM component |
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* @base: Memory mapped base address for this component. |
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* @csdev: Component vitals needed by the framework. |
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* @spinlock: Only one at a time pls. |
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* @mode: This tracer's mode, i.e sysFS, Perf or disabled. |
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* @cpu: The cpu this component is affined to. |
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* @arch: ETM architecture version. |
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* @nr_pe: The number of processing entity available for tracing. |
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* @nr_pe_cmp: The number of processing entity comparator inputs that are |
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* available for tracing. |
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* @nr_addr_cmp:Number of pairs of address comparators available |
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* as found in ETMIDR4 0-3. |
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* @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30. |
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* @nr_ext_inp: Number of external input. |
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* @numcidc: Number of contextID comparators. |
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* @numvmidc: Number of VMID comparators. |
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* @nrseqstate: The number of sequencer states that are implemented. |
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* @nr_event: Indicates how many events the trace unit support. |
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* @nr_resource:The number of resource selection pairs available for tracing. |
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* @nr_ss_cmp: Number of single-shot comparator controls that are available. |
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* @trcid: value of the current ID for this component. |
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* @trcid_size: Indicates the trace ID width. |
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* @ts_size: Global timestamp size field. |
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* @ctxid_size: Size of the context ID field to consider. |
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* @vmid_size: Size of the VM ID comparator to consider. |
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* @ccsize: Indicates the size of the cycle counter in bits. |
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* @ccitmin: minimum value that can be programmed in |
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* @s_ex_level: In secure state, indicates whether instruction tracing is |
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* supported for the corresponding Exception level. |
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* @ns_ex_level:In non-secure state, indicates whether instruction tracing is |
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* supported for the corresponding Exception level. |
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* @sticky_enable: true if ETM base configuration has been done. |
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* @boot_enable:True if we should start tracing at boot time. |
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* @os_unlock: True if access to management registers is allowed. |
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* @instrp0: Tracing of load and store instructions |
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* as P0 elements is supported. |
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* @trcbb: Indicates if the trace unit supports branch broadcast tracing. |
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* @trccond: If the trace unit supports conditional |
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* instruction tracing. |
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* @retstack: Indicates if the implementation supports a return stack. |
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* @trccci: Indicates if the trace unit supports cycle counting |
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* for instruction. |
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* @q_support: Q element support characteristics. |
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* @trc_error: Whether a trace unit can trace a system |
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* error exception. |
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* @syncpr: Indicates if an implementation has a fixed |
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* synchronization period. |
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* @stall_ctrl: Enables trace unit functionality that prevents trace |
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* unit buffer overflows. |
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* @sysstall: Does the system support stall control of the PE? |
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* @nooverflow: Indicate if overflow prevention is supported. |
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* @atbtrig: If the implementation can support ATB triggers |
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* @lpoverride: If the implementation can support low-power state over. |
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* @trfcr: If the CPU supports FEAT_TRF, value of the TRFCR_ELx that |
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* allows tracing at all ELs. We don't want to compute this |
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* at runtime, due to the additional setting of TRFCR_CX when |
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* in EL2. Otherwise, 0. |
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* @config: structure holding configuration parameters. |
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* @save_trfcr: Saved TRFCR_EL1 register during a CPU PM event. |
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* @save_state: State to be preserved across power loss |
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* @state_needs_restore: True when there is context to restore after PM exit |
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* @skip_power_up: Indicates if an implementation can skip powering up |
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* the trace unit. |
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* @arch_features: Bitmap of arch features of etmv4 devices. |
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*/ |
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struct etmv4_drvdata { |
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void __iomem *base; |
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struct coresight_device *csdev; |
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spinlock_t spinlock; |
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local_t mode; |
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int cpu; |
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u8 arch; |
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u8 nr_pe; |
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u8 nr_pe_cmp; |
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u8 nr_addr_cmp; |
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u8 nr_cntr; |
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u8 nr_ext_inp; |
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u8 numcidc; |
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u8 numvmidc; |
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u8 nrseqstate; |
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u8 nr_event; |
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u8 nr_resource; |
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u8 nr_ss_cmp; |
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u8 trcid; |
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u8 trcid_size; |
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u8 ts_size; |
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u8 ctxid_size; |
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u8 vmid_size; |
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u8 ccsize; |
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u8 ccitmin; |
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u8 s_ex_level; |
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u8 ns_ex_level; |
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u8 q_support; |
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u8 os_lock_model; |
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bool sticky_enable; |
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bool boot_enable; |
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bool os_unlock; |
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bool instrp0; |
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bool trcbb; |
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bool trccond; |
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bool retstack; |
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bool trccci; |
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bool trc_error; |
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bool syncpr; |
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bool stallctl; |
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bool sysstall; |
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bool nooverflow; |
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bool atbtrig; |
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bool lpoverride; |
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u64 trfcr; |
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struct etmv4_config config; |
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u64 save_trfcr; |
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struct etmv4_save_state *save_state; |
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bool state_needs_restore; |
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bool skip_power_up; |
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DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); |
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}; |
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/* Address comparator access types */ |
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enum etm_addr_acctype { |
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ETM_INSTR_ADDR, |
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ETM_DATA_LOAD_ADDR, |
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ETM_DATA_STORE_ADDR, |
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ETM_DATA_LOAD_STORE_ADDR, |
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}; |
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/* Address comparator context types */ |
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enum etm_addr_ctxtype { |
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ETM_CTX_NONE, |
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ETM_CTX_CTXID, |
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ETM_CTX_VMID, |
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ETM_CTX_CTXID_VMID, |
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}; |
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extern const struct attribute_group *coresight_etmv4_groups[]; |
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void etm4_config_trace_mode(struct etmv4_config *config); |
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u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit); |
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void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit); |
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static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata) |
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{ |
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return drvdata->arch >= ETM_ARCH_ETE; |
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} |
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#endif
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