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645 lines
17 KiB
645 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* amd-pstate.c - AMD Processor P-state Frequency Driver |
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* |
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* Copyright (C) 2021 Advanced Micro Devices, Inc. All Rights Reserved. |
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* |
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* Author: Huang Rui <[email protected]> |
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* |
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* AMD P-State introduces a new CPU performance scaling design for AMD |
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* processors using the ACPI Collaborative Performance and Power Control (CPPC) |
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* feature which works with the AMD SMU firmware providing a finer grained |
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* frequency control range. It is to replace the legacy ACPI P-States control, |
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* allows a flexible, low-latency interface for the Linux kernel to directly |
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* communicate the performance hints to hardware. |
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* |
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* AMD P-State is supported on recent AMD Zen base CPU series include some of |
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* Zen2 and Zen3 processors. _CPC needs to be present in the ACPI tables of AMD |
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* P-State supported system. And there are two types of hardware implementations |
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* for AMD P-State: 1) Full MSR Solution and 2) Shared Memory Solution. |
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* X86_FEATURE_CPPC CPU feature flag is used to distinguish the different types. |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/smp.h> |
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#include <linux/sched.h> |
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#include <linux/cpufreq.h> |
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#include <linux/compiler.h> |
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#include <linux/dmi.h> |
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#include <linux/slab.h> |
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#include <linux/acpi.h> |
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#include <linux/io.h> |
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#include <linux/delay.h> |
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#include <linux/uaccess.h> |
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#include <linux/static_call.h> |
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#include <acpi/processor.h> |
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#include <acpi/cppc_acpi.h> |
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#include <asm/msr.h> |
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#include <asm/processor.h> |
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#include <asm/cpufeature.h> |
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#include <asm/cpu_device_id.h> |
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#include "amd-pstate-trace.h" |
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#define AMD_PSTATE_TRANSITION_LATENCY 0x20000 |
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#define AMD_PSTATE_TRANSITION_DELAY 500 |
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/* |
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* TODO: We need more time to fine tune processors with shared memory solution |
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* with community together. |
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* |
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* There are some performance drops on the CPU benchmarks which reports from |
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* Suse. We are co-working with them to fine tune the shared memory solution. So |
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* we disable it by default to go acpi-cpufreq on these processors and add a |
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* module parameter to be able to enable it manually for debugging. |
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*/ |
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static bool shared_mem = false; |
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module_param(shared_mem, bool, 0444); |
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MODULE_PARM_DESC(shared_mem, |
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"enable amd-pstate on processors with shared memory solution (false = disabled (default), true = enabled)"); |
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static struct cpufreq_driver amd_pstate_driver; |
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/** |
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* struct amd_cpudata - private CPU data for AMD P-State |
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* @cpu: CPU number |
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* @req: constraint request to apply |
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* @cppc_req_cached: cached performance request hints |
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* @highest_perf: the maximum performance an individual processor may reach, |
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* assuming ideal conditions |
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* @nominal_perf: the maximum sustained performance level of the processor, |
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* assuming ideal operating conditions |
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* @lowest_nonlinear_perf: the lowest performance level at which nonlinear power |
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* savings are achieved |
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* @lowest_perf: the absolute lowest performance level of the processor |
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* @max_freq: the frequency that mapped to highest_perf |
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* @min_freq: the frequency that mapped to lowest_perf |
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* @nominal_freq: the frequency that mapped to nominal_perf |
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* @lowest_nonlinear_freq: the frequency that mapped to lowest_nonlinear_perf |
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* @boost_supported: check whether the Processor or SBIOS supports boost mode |
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* |
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* The amd_cpudata is key private data for each CPU thread in AMD P-State, and |
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* represents all the attributes and goals that AMD P-State requests at runtime. |
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*/ |
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struct amd_cpudata { |
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int cpu; |
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struct freq_qos_request req[2]; |
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u64 cppc_req_cached; |
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u32 highest_perf; |
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u32 nominal_perf; |
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u32 lowest_nonlinear_perf; |
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u32 lowest_perf; |
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u32 max_freq; |
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u32 min_freq; |
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u32 nominal_freq; |
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u32 lowest_nonlinear_freq; |
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bool boost_supported; |
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}; |
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static inline int pstate_enable(bool enable) |
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{ |
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return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable); |
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} |
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static int cppc_enable(bool enable) |
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{ |
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int cpu, ret = 0; |
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for_each_present_cpu(cpu) { |
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ret = cppc_set_enable(cpu, enable); |
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if (ret) |
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return ret; |
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} |
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return ret; |
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} |
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DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable); |
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static inline int amd_pstate_enable(bool enable) |
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{ |
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return static_call(amd_pstate_enable)(enable); |
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} |
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static int pstate_init_perf(struct amd_cpudata *cpudata) |
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{ |
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u64 cap1; |
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int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, |
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&cap1); |
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if (ret) |
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return ret; |
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/* |
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* TODO: Introduce AMD specific power feature. |
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* |
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* CPPC entry doesn't indicate the highest performance in some ASICs. |
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*/ |
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WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf()); |
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WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); |
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WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); |
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WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1)); |
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return 0; |
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} |
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static int cppc_init_perf(struct amd_cpudata *cpudata) |
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{ |
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struct cppc_perf_caps cppc_perf; |
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int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); |
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if (ret) |
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return ret; |
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WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf()); |
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WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); |
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WRITE_ONCE(cpudata->lowest_nonlinear_perf, |
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cppc_perf.lowest_nonlinear_perf); |
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WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); |
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return 0; |
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} |
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DEFINE_STATIC_CALL(amd_pstate_init_perf, pstate_init_perf); |
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static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata) |
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{ |
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return static_call(amd_pstate_init_perf)(cpudata); |
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} |
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static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, |
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u32 des_perf, u32 max_perf, bool fast_switch) |
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{ |
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if (fast_switch) |
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wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached)); |
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else |
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wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, |
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READ_ONCE(cpudata->cppc_req_cached)); |
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} |
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static void cppc_update_perf(struct amd_cpudata *cpudata, |
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u32 min_perf, u32 des_perf, |
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u32 max_perf, bool fast_switch) |
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{ |
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struct cppc_perf_ctrls perf_ctrls; |
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perf_ctrls.max_perf = max_perf; |
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perf_ctrls.min_perf = min_perf; |
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perf_ctrls.desired_perf = des_perf; |
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cppc_set_perf(cpudata->cpu, &perf_ctrls); |
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} |
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DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf); |
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static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, |
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u32 min_perf, u32 des_perf, |
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u32 max_perf, bool fast_switch) |
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{ |
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static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf, |
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max_perf, fast_switch); |
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} |
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static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, |
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u32 des_perf, u32 max_perf, bool fast_switch) |
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{ |
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u64 prev = READ_ONCE(cpudata->cppc_req_cached); |
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u64 value = prev; |
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value &= ~AMD_CPPC_MIN_PERF(~0L); |
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value |= AMD_CPPC_MIN_PERF(min_perf); |
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value &= ~AMD_CPPC_DES_PERF(~0L); |
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value |= AMD_CPPC_DES_PERF(des_perf); |
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value &= ~AMD_CPPC_MAX_PERF(~0L); |
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value |= AMD_CPPC_MAX_PERF(max_perf); |
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trace_amd_pstate_perf(min_perf, des_perf, max_perf, |
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cpudata->cpu, (value != prev), fast_switch); |
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if (value == prev) |
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return; |
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WRITE_ONCE(cpudata->cppc_req_cached, value); |
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amd_pstate_update_perf(cpudata, min_perf, des_perf, |
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max_perf, fast_switch); |
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} |
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static int amd_pstate_verify(struct cpufreq_policy_data *policy) |
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{ |
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cpufreq_verify_within_cpu_limits(policy); |
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return 0; |
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} |
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static int amd_pstate_target(struct cpufreq_policy *policy, |
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unsigned int target_freq, |
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unsigned int relation) |
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{ |
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struct cpufreq_freqs freqs; |
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struct amd_cpudata *cpudata = policy->driver_data; |
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unsigned long max_perf, min_perf, des_perf, cap_perf; |
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if (!cpudata->max_freq) |
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return -ENODEV; |
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cap_perf = READ_ONCE(cpudata->highest_perf); |
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min_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); |
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max_perf = cap_perf; |
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freqs.old = policy->cur; |
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freqs.new = target_freq; |
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des_perf = DIV_ROUND_CLOSEST(target_freq * cap_perf, |
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cpudata->max_freq); |
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cpufreq_freq_transition_begin(policy, &freqs); |
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amd_pstate_update(cpudata, min_perf, des_perf, |
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max_perf, false); |
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cpufreq_freq_transition_end(policy, &freqs, false); |
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return 0; |
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} |
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static void amd_pstate_adjust_perf(unsigned int cpu, |
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unsigned long _min_perf, |
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unsigned long target_perf, |
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unsigned long capacity) |
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{ |
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unsigned long max_perf, min_perf, des_perf, |
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cap_perf, lowest_nonlinear_perf; |
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struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); |
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struct amd_cpudata *cpudata = policy->driver_data; |
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cap_perf = READ_ONCE(cpudata->highest_perf); |
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lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); |
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des_perf = cap_perf; |
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if (target_perf < capacity) |
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des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity); |
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min_perf = READ_ONCE(cpudata->highest_perf); |
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if (_min_perf < capacity) |
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min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity); |
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if (min_perf < lowest_nonlinear_perf) |
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min_perf = lowest_nonlinear_perf; |
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max_perf = cap_perf; |
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if (max_perf < min_perf) |
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max_perf = min_perf; |
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des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); |
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amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true); |
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} |
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static int amd_get_min_freq(struct amd_cpudata *cpudata) |
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{ |
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struct cppc_perf_caps cppc_perf; |
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int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); |
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if (ret) |
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return ret; |
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/* Switch to khz */ |
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return cppc_perf.lowest_freq * 1000; |
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} |
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static int amd_get_max_freq(struct amd_cpudata *cpudata) |
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{ |
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struct cppc_perf_caps cppc_perf; |
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u32 max_perf, max_freq, nominal_freq, nominal_perf; |
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u64 boost_ratio; |
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int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); |
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if (ret) |
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return ret; |
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nominal_freq = cppc_perf.nominal_freq; |
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nominal_perf = READ_ONCE(cpudata->nominal_perf); |
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max_perf = READ_ONCE(cpudata->highest_perf); |
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boost_ratio = div_u64(max_perf << SCHED_CAPACITY_SHIFT, |
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nominal_perf); |
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max_freq = nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT; |
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/* Switch to khz */ |
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return max_freq * 1000; |
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} |
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static int amd_get_nominal_freq(struct amd_cpudata *cpudata) |
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{ |
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struct cppc_perf_caps cppc_perf; |
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int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); |
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if (ret) |
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return ret; |
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/* Switch to khz */ |
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return cppc_perf.nominal_freq * 1000; |
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} |
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static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) |
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{ |
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struct cppc_perf_caps cppc_perf; |
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u32 lowest_nonlinear_freq, lowest_nonlinear_perf, |
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nominal_freq, nominal_perf; |
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u64 lowest_nonlinear_ratio; |
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int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); |
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if (ret) |
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return ret; |
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nominal_freq = cppc_perf.nominal_freq; |
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nominal_perf = READ_ONCE(cpudata->nominal_perf); |
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lowest_nonlinear_perf = cppc_perf.lowest_nonlinear_perf; |
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lowest_nonlinear_ratio = div_u64(lowest_nonlinear_perf << SCHED_CAPACITY_SHIFT, |
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nominal_perf); |
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lowest_nonlinear_freq = nominal_freq * lowest_nonlinear_ratio >> SCHED_CAPACITY_SHIFT; |
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/* Switch to khz */ |
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return lowest_nonlinear_freq * 1000; |
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} |
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static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) |
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{ |
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struct amd_cpudata *cpudata = policy->driver_data; |
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int ret; |
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if (!cpudata->boost_supported) { |
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pr_err("Boost mode is not supported by this processor or SBIOS\n"); |
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return -EINVAL; |
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} |
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if (state) |
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policy->cpuinfo.max_freq = cpudata->max_freq; |
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else |
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policy->cpuinfo.max_freq = cpudata->nominal_freq; |
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policy->max = policy->cpuinfo.max_freq; |
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ret = freq_qos_update_request(&cpudata->req[1], |
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policy->cpuinfo.max_freq); |
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if (ret < 0) |
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return ret; |
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return 0; |
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} |
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static void amd_pstate_boost_init(struct amd_cpudata *cpudata) |
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{ |
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u32 highest_perf, nominal_perf; |
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highest_perf = READ_ONCE(cpudata->highest_perf); |
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nominal_perf = READ_ONCE(cpudata->nominal_perf); |
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if (highest_perf <= nominal_perf) |
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return; |
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cpudata->boost_supported = true; |
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amd_pstate_driver.boost_enabled = true; |
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} |
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static int amd_pstate_cpu_init(struct cpufreq_policy *policy) |
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{ |
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int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; |
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struct device *dev; |
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struct amd_cpudata *cpudata; |
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dev = get_cpu_device(policy->cpu); |
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if (!dev) |
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return -ENODEV; |
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cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL); |
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if (!cpudata) |
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return -ENOMEM; |
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cpudata->cpu = policy->cpu; |
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ret = amd_pstate_init_perf(cpudata); |
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if (ret) |
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goto free_cpudata1; |
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min_freq = amd_get_min_freq(cpudata); |
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max_freq = amd_get_max_freq(cpudata); |
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nominal_freq = amd_get_nominal_freq(cpudata); |
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lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata); |
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if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) { |
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dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n", |
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min_freq, max_freq); |
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ret = -EINVAL; |
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goto free_cpudata1; |
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} |
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policy->cpuinfo.transition_latency = AMD_PSTATE_TRANSITION_LATENCY; |
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policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY; |
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policy->min = min_freq; |
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policy->max = max_freq; |
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policy->cpuinfo.min_freq = min_freq; |
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policy->cpuinfo.max_freq = max_freq; |
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/* It will be updated by governor */ |
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policy->cur = policy->cpuinfo.min_freq; |
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if (boot_cpu_has(X86_FEATURE_CPPC)) |
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policy->fast_switch_possible = true; |
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ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], |
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FREQ_QOS_MIN, policy->cpuinfo.min_freq); |
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if (ret < 0) { |
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dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); |
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goto free_cpudata1; |
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} |
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ret = freq_qos_add_request(&policy->constraints, &cpudata->req[1], |
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FREQ_QOS_MAX, policy->cpuinfo.max_freq); |
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if (ret < 0) { |
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dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); |
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goto free_cpudata2; |
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} |
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/* Initial processor data capability frequencies */ |
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cpudata->max_freq = max_freq; |
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cpudata->min_freq = min_freq; |
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cpudata->nominal_freq = nominal_freq; |
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cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq; |
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policy->driver_data = cpudata; |
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amd_pstate_boost_init(cpudata); |
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return 0; |
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free_cpudata2: |
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freq_qos_remove_request(&cpudata->req[0]); |
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free_cpudata1: |
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kfree(cpudata); |
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return ret; |
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} |
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static int amd_pstate_cpu_exit(struct cpufreq_policy *policy) |
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{ |
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struct amd_cpudata *cpudata; |
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cpudata = policy->driver_data; |
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freq_qos_remove_request(&cpudata->req[1]); |
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freq_qos_remove_request(&cpudata->req[0]); |
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kfree(cpudata); |
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return 0; |
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} |
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/* Sysfs attributes */ |
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/* |
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* This frequency is to indicate the maximum hardware frequency. |
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* If boost is not active but supported, the frequency will be larger than the |
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* one in cpuinfo. |
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*/ |
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static ssize_t show_amd_pstate_max_freq(struct cpufreq_policy *policy, |
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char *buf) |
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{ |
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int max_freq; |
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struct amd_cpudata *cpudata; |
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cpudata = policy->driver_data; |
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max_freq = amd_get_max_freq(cpudata); |
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if (max_freq < 0) |
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return max_freq; |
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return sprintf(&buf[0], "%u\n", max_freq); |
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} |
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static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *policy, |
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char *buf) |
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{ |
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int freq; |
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struct amd_cpudata *cpudata; |
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cpudata = policy->driver_data; |
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freq = amd_get_lowest_nonlinear_freq(cpudata); |
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if (freq < 0) |
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return freq; |
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return sprintf(&buf[0], "%u\n", freq); |
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} |
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/* |
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* In some of ASICs, the highest_perf is not the one in the _CPC table, so we |
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* need to expose it to sysfs. |
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*/ |
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static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, |
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char *buf) |
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{ |
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u32 perf; |
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struct amd_cpudata *cpudata = policy->driver_data; |
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perf = READ_ONCE(cpudata->highest_perf); |
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return sprintf(&buf[0], "%u\n", perf); |
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} |
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cpufreq_freq_attr_ro(amd_pstate_max_freq); |
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cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); |
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cpufreq_freq_attr_ro(amd_pstate_highest_perf); |
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static struct freq_attr *amd_pstate_attr[] = { |
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&amd_pstate_max_freq, |
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&amd_pstate_lowest_nonlinear_freq, |
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&amd_pstate_highest_perf, |
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NULL, |
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}; |
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|
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static struct cpufreq_driver amd_pstate_driver = { |
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.flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, |
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.verify = amd_pstate_verify, |
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.target = amd_pstate_target, |
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.init = amd_pstate_cpu_init, |
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.exit = amd_pstate_cpu_exit, |
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.set_boost = amd_pstate_set_boost, |
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.name = "amd-pstate", |
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.attr = amd_pstate_attr, |
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}; |
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static int __init amd_pstate_init(void) |
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{ |
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int ret; |
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|
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) |
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return -ENODEV; |
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if (!acpi_cpc_valid()) { |
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pr_debug("the _CPC object is not present in SBIOS\n"); |
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return -ENODEV; |
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} |
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|
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/* don't keep reloading if cpufreq_driver exists */ |
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if (cpufreq_get_current_driver()) |
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return -EEXIST; |
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|
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/* capability check */ |
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if (boot_cpu_has(X86_FEATURE_CPPC)) { |
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pr_debug("AMD CPPC MSR based functionality is supported\n"); |
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amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf; |
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} else if (shared_mem) { |
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static_call_update(amd_pstate_enable, cppc_enable); |
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static_call_update(amd_pstate_init_perf, cppc_init_perf); |
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static_call_update(amd_pstate_update_perf, cppc_update_perf); |
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} else { |
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pr_info("This processor supports shared memory solution, you can enable it with amd_pstate.shared_mem=1\n"); |
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return -ENODEV; |
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} |
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|
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/* enable amd pstate feature */ |
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ret = amd_pstate_enable(true); |
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if (ret) { |
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pr_err("failed to enable amd-pstate with return %d\n", ret); |
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return ret; |
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} |
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ret = cpufreq_register_driver(&amd_pstate_driver); |
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if (ret) |
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pr_err("failed to register amd_pstate_driver with return %d\n", |
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ret); |
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return ret; |
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} |
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static void __exit amd_pstate_exit(void) |
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{ |
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cpufreq_unregister_driver(&amd_pstate_driver); |
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|
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amd_pstate_enable(false); |
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} |
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module_init(amd_pstate_init); |
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module_exit(amd_pstate_exit); |
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|
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MODULE_AUTHOR("Huang Rui <[email protected]>"); |
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MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); |
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MODULE_LICENSE("GPL");
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