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230 lines
5.7 KiB
230 lines
5.7 KiB
// SPDX-License-Identifier: GPL-2.0 OR MIT |
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/* |
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* Copyright (C) 2021 StarFive Technology Co., Ltd. |
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* Copyright (C) 2021 Emil Renner Berthing <[email protected]> |
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*/ |
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/dts-v1/; |
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#include <dt-bindings/clock/starfive-jh7100.h> |
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#include <dt-bindings/reset/starfive-jh7100.h> |
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/ { |
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compatible = "starfive,jh7100"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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compatible = "sifive,u74-mc", "riscv"; |
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reg = <0>; |
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d-cache-block-size = <64>; |
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d-cache-sets = <64>; |
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d-cache-size = <32768>; |
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d-tlb-sets = <1>; |
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d-tlb-size = <32>; |
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device_type = "cpu"; |
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i-cache-block-size = <64>; |
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i-cache-sets = <64>; |
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i-cache-size = <32768>; |
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i-tlb-sets = <1>; |
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i-tlb-size = <32>; |
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mmu-type = "riscv,sv39"; |
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riscv,isa = "rv64imafdc"; |
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tlb-split; |
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cpu0_intc: interrupt-controller { |
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compatible = "riscv,cpu-intc"; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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}; |
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}; |
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cpu@1 { |
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compatible = "sifive,u74-mc", "riscv"; |
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reg = <1>; |
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d-cache-block-size = <64>; |
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d-cache-sets = <64>; |
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d-cache-size = <32768>; |
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d-tlb-sets = <1>; |
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d-tlb-size = <32>; |
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device_type = "cpu"; |
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i-cache-block-size = <64>; |
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i-cache-sets = <64>; |
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i-cache-size = <32768>; |
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i-tlb-sets = <1>; |
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i-tlb-size = <32>; |
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mmu-type = "riscv,sv39"; |
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riscv,isa = "rv64imafdc"; |
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tlb-split; |
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cpu1_intc: interrupt-controller { |
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compatible = "riscv,cpu-intc"; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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}; |
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}; |
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}; |
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osc_sys: osc_sys { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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/* This value must be overridden by the board */ |
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clock-frequency = <0>; |
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}; |
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osc_aud: osc_aud { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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/* This value must be overridden by the board */ |
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clock-frequency = <0>; |
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}; |
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gmac_rmii_ref: gmac_rmii_ref { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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/* Should be overridden by the board when needed */ |
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clock-frequency = <0>; |
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}; |
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gmac_gr_mii_rxclk: gmac_gr_mii_rxclk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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/* Should be overridden by the board when needed */ |
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clock-frequency = <0>; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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interrupt-parent = <&plic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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clint: clint@2000000 { |
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compatible = "starfive,jh7100-clint", "sifive,clint0"; |
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reg = <0x0 0x2000000 0x0 0x10000>; |
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interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 |
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&cpu1_intc 3 &cpu1_intc 7>; |
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}; |
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plic: interrupt-controller@c000000 { |
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compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0"; |
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reg = <0x0 0xc000000 0x0 0x4000000>; |
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interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9 |
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&cpu1_intc 11 &cpu1_intc 9>; |
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interrupt-controller; |
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#address-cells = <0>; |
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#interrupt-cells = <1>; |
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riscv,ndev = <127>; |
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}; |
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clkgen: clock-controller@11800000 { |
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compatible = "starfive,jh7100-clkgen"; |
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reg = <0x0 0x11800000 0x0 0x10000>; |
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clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; |
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clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; |
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#clock-cells = <1>; |
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}; |
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rstgen: reset-controller@11840000 { |
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compatible = "starfive,jh7100-reset"; |
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reg = <0x0 0x11840000 0x0 0x10000>; |
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#reset-cells = <1>; |
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}; |
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i2c0: i2c@118b0000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0x0 0x118b0000 0x0 0x10000>; |
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clocks = <&clkgen JH7100_CLK_I2C0_CORE>, |
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<&clkgen JH7100_CLK_I2C0_APB>; |
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clock-names = "ref", "pclk"; |
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resets = <&rstgen JH7100_RSTN_I2C0_APB>; |
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interrupts = <96>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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i2c1: i2c@118c0000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0x0 0x118c0000 0x0 0x10000>; |
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clocks = <&clkgen JH7100_CLK_I2C1_CORE>, |
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<&clkgen JH7100_CLK_I2C1_APB>; |
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clock-names = "ref", "pclk"; |
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resets = <&rstgen JH7100_RSTN_I2C1_APB>; |
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interrupts = <97>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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gpio: pinctrl@11910000 { |
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compatible = "starfive,jh7100-pinctrl"; |
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reg = <0x0 0x11910000 0x0 0x10000>, |
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<0x0 0x11858000 0x0 0x1000>; |
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reg-names = "gpio", "padctl"; |
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clocks = <&clkgen JH7100_CLK_GPIO_APB>; |
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resets = <&rstgen JH7100_RSTN_GPIO_APB>; |
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interrupts = <32>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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uart2: serial@12430000 { |
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compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; |
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reg = <0x0 0x12430000 0x0 0x10000>; |
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clocks = <&clkgen JH7100_CLK_UART2_CORE>, |
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<&clkgen JH7100_CLK_UART2_APB>; |
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clock-names = "baudclk", "apb_pclk"; |
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resets = <&rstgen JH7100_RSTN_UART2_APB>; |
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interrupts = <72>; |
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reg-io-width = <4>; |
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reg-shift = <2>; |
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status = "disabled"; |
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}; |
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uart3: serial@12440000 { |
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compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; |
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reg = <0x0 0x12440000 0x0 0x10000>; |
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clocks = <&clkgen JH7100_CLK_UART3_CORE>, |
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<&clkgen JH7100_CLK_UART3_APB>; |
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clock-names = "baudclk", "apb_pclk"; |
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resets = <&rstgen JH7100_RSTN_UART3_APB>; |
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interrupts = <73>; |
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reg-io-width = <4>; |
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reg-shift = <2>; |
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status = "disabled"; |
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}; |
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i2c2: i2c@12450000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0x0 0x12450000 0x0 0x10000>; |
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clocks = <&clkgen JH7100_CLK_I2C2_CORE>, |
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<&clkgen JH7100_CLK_I2C2_APB>; |
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clock-names = "ref", "pclk"; |
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resets = <&rstgen JH7100_RSTN_I2C2_APB>; |
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interrupts = <74>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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i2c3: i2c@12460000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0x0 0x12460000 0x0 0x10000>; |
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clocks = <&clkgen JH7100_CLK_I2C3_CORE>, |
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<&clkgen JH7100_CLK_I2C3_APB>; |
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clock-names = "ref", "pclk"; |
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resets = <&rstgen JH7100_RSTN_I2C3_APB>; |
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interrupts = <75>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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}; |
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};
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