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250 lines
6.0 KiB
250 lines
6.0 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* ARCv2 supports 64-bit exclusive load (LLOCKD) / store (SCONDD) |
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* - The address HAS to be 64-bit aligned |
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*/ |
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#ifndef _ASM_ARC_ATOMIC64_ARCV2_H |
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#define _ASM_ARC_ATOMIC64_ARCV2_H |
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typedef struct { |
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s64 __aligned(8) counter; |
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} atomic64_t; |
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#define ATOMIC64_INIT(a) { (a) } |
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static inline s64 arch_atomic64_read(const atomic64_t *v) |
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{ |
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s64 val; |
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__asm__ __volatile__( |
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" ldd %0, [%1] \n" |
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: "=r"(val) |
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: "r"(&v->counter)); |
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return val; |
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} |
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static inline void arch_atomic64_set(atomic64_t *v, s64 a) |
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{ |
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/* |
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* This could have been a simple assignment in "C" but would need |
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* explicit volatile. Otherwise gcc optimizers could elide the store |
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* which borked atomic64 self-test |
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* In the inline asm version, memory clobber needed for exact same |
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* reason, to tell gcc about the store. |
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* |
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* This however is not needed for sibling atomic64_add() etc since both |
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* load/store are explicitly done in inline asm. As long as API is used |
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* for each access, gcc has no way to optimize away any load/store |
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*/ |
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__asm__ __volatile__( |
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" std %0, [%1] \n" |
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: |
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: "r"(a), "r"(&v->counter) |
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: "memory"); |
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} |
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#define ATOMIC64_OP(op, op1, op2) \ |
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static inline void arch_atomic64_##op(s64 a, atomic64_t *v) \ |
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{ \ |
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s64 val; \ |
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\ |
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__asm__ __volatile__( \ |
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"1: \n" \ |
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" llockd %0, [%1] \n" \ |
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" " #op1 " %L0, %L0, %L2 \n" \ |
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" " #op2 " %H0, %H0, %H2 \n" \ |
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" scondd %0, [%1] \n" \ |
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" bnz 1b \n" \ |
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: "=&r"(val) \ |
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: "r"(&v->counter), "ir"(a) \ |
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: "cc"); \ |
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} \ |
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#define ATOMIC64_OP_RETURN(op, op1, op2) \ |
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static inline s64 arch_atomic64_##op##_return_relaxed(s64 a, atomic64_t *v) \ |
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{ \ |
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s64 val; \ |
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\ |
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__asm__ __volatile__( \ |
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"1: \n" \ |
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" llockd %0, [%1] \n" \ |
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" " #op1 " %L0, %L0, %L2 \n" \ |
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" " #op2 " %H0, %H0, %H2 \n" \ |
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" scondd %0, [%1] \n" \ |
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" bnz 1b \n" \ |
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: [val] "=&r"(val) \ |
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: "r"(&v->counter), "ir"(a) \ |
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: "cc"); /* memory clobber comes from smp_mb() */ \ |
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\ |
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return val; \ |
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} |
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#define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed |
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#define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed |
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#define ATOMIC64_FETCH_OP(op, op1, op2) \ |
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static inline s64 arch_atomic64_fetch_##op##_relaxed(s64 a, atomic64_t *v) \ |
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{ \ |
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s64 val, orig; \ |
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\ |
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__asm__ __volatile__( \ |
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"1: \n" \ |
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" llockd %0, [%2] \n" \ |
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" " #op1 " %L1, %L0, %L3 \n" \ |
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" " #op2 " %H1, %H0, %H3 \n" \ |
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" scondd %1, [%2] \n" \ |
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" bnz 1b \n" \ |
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: "=&r"(orig), "=&r"(val) \ |
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: "r"(&v->counter), "ir"(a) \ |
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: "cc"); /* memory clobber comes from smp_mb() */ \ |
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\ |
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return orig; \ |
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} |
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#define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed |
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#define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed |
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#define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed |
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#define arch_atomic64_fetch_andnot_relaxed arch_atomic64_fetch_andnot_relaxed |
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#define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed |
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#define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed |
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#define ATOMIC64_OPS(op, op1, op2) \ |
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ATOMIC64_OP(op, op1, op2) \ |
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ATOMIC64_OP_RETURN(op, op1, op2) \ |
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ATOMIC64_FETCH_OP(op, op1, op2) |
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ATOMIC64_OPS(add, add.f, adc) |
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ATOMIC64_OPS(sub, sub.f, sbc) |
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#undef ATOMIC64_OPS |
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#define ATOMIC64_OPS(op, op1, op2) \ |
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ATOMIC64_OP(op, op1, op2) \ |
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ATOMIC64_FETCH_OP(op, op1, op2) |
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ATOMIC64_OPS(and, and, and) |
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ATOMIC64_OPS(andnot, bic, bic) |
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ATOMIC64_OPS(or, or, or) |
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ATOMIC64_OPS(xor, xor, xor) |
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#define arch_atomic64_andnot arch_atomic64_andnot |
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#undef ATOMIC64_OPS |
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#undef ATOMIC64_FETCH_OP |
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#undef ATOMIC64_OP_RETURN |
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#undef ATOMIC64_OP |
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static inline s64 |
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arch_atomic64_cmpxchg(atomic64_t *ptr, s64 expected, s64 new) |
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{ |
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s64 prev; |
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smp_mb(); |
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__asm__ __volatile__( |
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"1: llockd %0, [%1] \n" |
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" brne %L0, %L2, 2f \n" |
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" brne %H0, %H2, 2f \n" |
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" scondd %3, [%1] \n" |
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" bnz 1b \n" |
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"2: \n" |
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: "=&r"(prev) |
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: "r"(ptr), "ir"(expected), "r"(new) |
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: "cc"); /* memory clobber comes from smp_mb() */ |
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smp_mb(); |
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return prev; |
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} |
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static inline s64 arch_atomic64_xchg(atomic64_t *ptr, s64 new) |
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{ |
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s64 prev; |
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smp_mb(); |
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__asm__ __volatile__( |
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"1: llockd %0, [%1] \n" |
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" scondd %2, [%1] \n" |
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" bnz 1b \n" |
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"2: \n" |
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: "=&r"(prev) |
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: "r"(ptr), "r"(new) |
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: "cc"); /* memory clobber comes from smp_mb() */ |
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smp_mb(); |
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return prev; |
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} |
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/** |
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* arch_atomic64_dec_if_positive - decrement by 1 if old value positive |
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* @v: pointer of type atomic64_t |
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* |
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* The function returns the old value of *v minus 1, even if |
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* the atomic variable, v, was not decremented. |
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*/ |
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static inline s64 arch_atomic64_dec_if_positive(atomic64_t *v) |
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{ |
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s64 val; |
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smp_mb(); |
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__asm__ __volatile__( |
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"1: llockd %0, [%1] \n" |
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" sub.f %L0, %L0, 1 # w0 - 1, set C on borrow\n" |
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" sub.c %H0, %H0, 1 # if C set, w1 - 1\n" |
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" brlt %H0, 0, 2f \n" |
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" scondd %0, [%1] \n" |
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" bnz 1b \n" |
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"2: \n" |
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: "=&r"(val) |
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: "r"(&v->counter) |
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: "cc"); /* memory clobber comes from smp_mb() */ |
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smp_mb(); |
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return val; |
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} |
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#define arch_atomic64_dec_if_positive arch_atomic64_dec_if_positive |
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/** |
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* arch_atomic64_fetch_add_unless - add unless the number is a given value |
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* @v: pointer of type atomic64_t |
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* @a: the amount to add to v... |
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* @u: ...unless v is equal to u. |
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* |
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* Atomically adds @a to @v, if it was not @u. |
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* Returns the old value of @v |
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*/ |
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static inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u) |
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{ |
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s64 old, temp; |
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smp_mb(); |
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__asm__ __volatile__( |
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"1: llockd %0, [%2] \n" |
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" brne %L0, %L4, 2f # continue to add since v != u \n" |
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" breq.d %H0, %H4, 3f # return since v == u \n" |
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"2: \n" |
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" add.f %L1, %L0, %L3 \n" |
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" adc %H1, %H0, %H3 \n" |
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" scondd %1, [%2] \n" |
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" bnz 1b \n" |
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"3: \n" |
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: "=&r"(old), "=&r" (temp) |
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: "r"(&v->counter), "r"(a), "r"(u) |
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: "cc"); /* memory clobber comes from smp_mb() */ |
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smp_mb(); |
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return old; |
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} |
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#define arch_atomic64_fetch_add_unless arch_atomic64_fetch_add_unless |
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#endif
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