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399 lines
8.9 KiB
399 lines
8.9 KiB
/***********************license start*************** |
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* Author: Cavium Networks |
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* |
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* Contact: [email protected] |
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* This file is part of the OCTEON SDK |
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* |
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* Copyright (c) 2003-2012 Cavium Networks |
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* |
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* This file is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License, Version 2, as |
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* published by the Free Software Foundation. |
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* |
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* This file is distributed in the hope that it will be useful, but |
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or |
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* NONINFRINGEMENT. See the GNU General Public License for more |
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* details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this file; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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* or visit http://www.gnu.org/licenses/. |
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* |
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* This file may also be available under a different license from Cavium. |
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* Contact Cavium Networks for more information |
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***********************license end**************************************/ |
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#ifndef __CVMX_GPIO_DEFS_H__ |
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#define __CVMX_GPIO_DEFS_H__ |
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#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8) |
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#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull)) |
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#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8) |
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#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8) |
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#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) |
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#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull)) |
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#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull)) |
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#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull)) |
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#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull)) |
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#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) |
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#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull)) |
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#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull)) |
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#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16) |
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union cvmx_gpio_bit_cfgx { |
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uint64_t u64; |
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struct cvmx_gpio_bit_cfgx_s { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_21_63:42; |
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uint64_t output_sel:5; |
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uint64_t synce_sel:2; |
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uint64_t clk_gen:1; |
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uint64_t clk_sel:2; |
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uint64_t fil_sel:4; |
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uint64_t fil_cnt:4; |
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uint64_t int_type:1; |
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uint64_t int_en:1; |
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uint64_t rx_xor:1; |
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uint64_t tx_oe:1; |
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#else |
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uint64_t tx_oe:1; |
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uint64_t rx_xor:1; |
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uint64_t int_en:1; |
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uint64_t int_type:1; |
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uint64_t fil_cnt:4; |
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uint64_t fil_sel:4; |
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uint64_t clk_sel:2; |
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uint64_t clk_gen:1; |
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uint64_t synce_sel:2; |
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uint64_t output_sel:5; |
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uint64_t reserved_21_63:42; |
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#endif |
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} s; |
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struct cvmx_gpio_bit_cfgx_cn30xx { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_12_63:52; |
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uint64_t fil_sel:4; |
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uint64_t fil_cnt:4; |
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uint64_t int_type:1; |
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uint64_t int_en:1; |
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uint64_t rx_xor:1; |
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uint64_t tx_oe:1; |
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#else |
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uint64_t tx_oe:1; |
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uint64_t rx_xor:1; |
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uint64_t int_en:1; |
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uint64_t int_type:1; |
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uint64_t fil_cnt:4; |
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uint64_t fil_sel:4; |
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uint64_t reserved_12_63:52; |
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#endif |
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} cn30xx; |
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struct cvmx_gpio_bit_cfgx_cn52xx { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_15_63:49; |
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uint64_t clk_gen:1; |
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uint64_t clk_sel:2; |
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uint64_t fil_sel:4; |
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uint64_t fil_cnt:4; |
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uint64_t int_type:1; |
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uint64_t int_en:1; |
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uint64_t rx_xor:1; |
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uint64_t tx_oe:1; |
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#else |
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uint64_t tx_oe:1; |
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uint64_t rx_xor:1; |
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uint64_t int_en:1; |
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uint64_t int_type:1; |
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uint64_t fil_cnt:4; |
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uint64_t fil_sel:4; |
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uint64_t clk_sel:2; |
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uint64_t clk_gen:1; |
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uint64_t reserved_15_63:49; |
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#endif |
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} cn52xx; |
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}; |
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union cvmx_gpio_boot_ena { |
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uint64_t u64; |
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struct cvmx_gpio_boot_ena_s { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_12_63:52; |
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uint64_t boot_ena:4; |
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uint64_t reserved_0_7:8; |
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#else |
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uint64_t reserved_0_7:8; |
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uint64_t boot_ena:4; |
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uint64_t reserved_12_63:52; |
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#endif |
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} s; |
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}; |
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union cvmx_gpio_clk_genx { |
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uint64_t u64; |
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struct cvmx_gpio_clk_genx_s { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_32_63:32; |
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uint64_t n:32; |
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#else |
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uint64_t n:32; |
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uint64_t reserved_32_63:32; |
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#endif |
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} s; |
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}; |
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union cvmx_gpio_clk_qlmx { |
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uint64_t u64; |
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struct cvmx_gpio_clk_qlmx_s { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_11_63:53; |
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uint64_t qlm_sel:3; |
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uint64_t reserved_3_7:5; |
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uint64_t div:1; |
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uint64_t lane_sel:2; |
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#else |
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uint64_t lane_sel:2; |
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uint64_t div:1; |
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uint64_t reserved_3_7:5; |
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uint64_t qlm_sel:3; |
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uint64_t reserved_11_63:53; |
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#endif |
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} s; |
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struct cvmx_gpio_clk_qlmx_cn61xx { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_10_63:54; |
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uint64_t qlm_sel:2; |
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uint64_t reserved_3_7:5; |
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uint64_t div:1; |
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uint64_t lane_sel:2; |
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#else |
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uint64_t lane_sel:2; |
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uint64_t div:1; |
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uint64_t reserved_3_7:5; |
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uint64_t qlm_sel:2; |
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uint64_t reserved_10_63:54; |
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#endif |
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} cn61xx; |
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struct cvmx_gpio_clk_qlmx_cn63xx { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_3_63:61; |
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uint64_t div:1; |
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uint64_t lane_sel:2; |
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#else |
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uint64_t lane_sel:2; |
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uint64_t div:1; |
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uint64_t reserved_3_63:61; |
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#endif |
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} cn63xx; |
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}; |
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union cvmx_gpio_dbg_ena { |
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uint64_t u64; |
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struct cvmx_gpio_dbg_ena_s { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_21_63:43; |
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uint64_t dbg_ena:21; |
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#else |
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uint64_t dbg_ena:21; |
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uint64_t reserved_21_63:43; |
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#endif |
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} s; |
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}; |
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union cvmx_gpio_int_clr { |
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uint64_t u64; |
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struct cvmx_gpio_int_clr_s { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_16_63:48; |
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uint64_t type:16; |
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#else |
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uint64_t type:16; |
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uint64_t reserved_16_63:48; |
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#endif |
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} s; |
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}; |
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union cvmx_gpio_multi_cast { |
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uint64_t u64; |
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struct cvmx_gpio_multi_cast_s { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_1_63:63; |
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uint64_t en:1; |
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#else |
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uint64_t en:1; |
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uint64_t reserved_1_63:63; |
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#endif |
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} s; |
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}; |
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union cvmx_gpio_pin_ena { |
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uint64_t u64; |
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struct cvmx_gpio_pin_ena_s { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_20_63:44; |
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uint64_t ena19:1; |
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uint64_t ena18:1; |
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uint64_t reserved_0_17:18; |
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#else |
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uint64_t reserved_0_17:18; |
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uint64_t ena18:1; |
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uint64_t ena19:1; |
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uint64_t reserved_20_63:44; |
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#endif |
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} s; |
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}; |
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union cvmx_gpio_rx_dat { |
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uint64_t u64; |
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struct cvmx_gpio_rx_dat_s { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_24_63:40; |
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uint64_t dat:24; |
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#else |
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uint64_t dat:24; |
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uint64_t reserved_24_63:40; |
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#endif |
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} s; |
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struct cvmx_gpio_rx_dat_cn38xx { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_16_63:48; |
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uint64_t dat:16; |
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#else |
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uint64_t dat:16; |
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uint64_t reserved_16_63:48; |
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#endif |
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} cn38xx; |
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struct cvmx_gpio_rx_dat_cn61xx { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_20_63:44; |
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uint64_t dat:20; |
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#else |
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uint64_t dat:20; |
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uint64_t reserved_20_63:44; |
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#endif |
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} cn61xx; |
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}; |
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union cvmx_gpio_tim_ctl { |
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uint64_t u64; |
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struct cvmx_gpio_tim_ctl_s { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_4_63:60; |
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uint64_t sel:4; |
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#else |
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uint64_t sel:4; |
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uint64_t reserved_4_63:60; |
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#endif |
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} s; |
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}; |
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union cvmx_gpio_tx_clr { |
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uint64_t u64; |
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struct cvmx_gpio_tx_clr_s { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_24_63:40; |
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uint64_t clr:24; |
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#else |
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uint64_t clr:24; |
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uint64_t reserved_24_63:40; |
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#endif |
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} s; |
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struct cvmx_gpio_tx_clr_cn38xx { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_16_63:48; |
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uint64_t clr:16; |
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#else |
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uint64_t clr:16; |
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uint64_t reserved_16_63:48; |
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#endif |
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} cn38xx; |
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struct cvmx_gpio_tx_clr_cn61xx { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_20_63:44; |
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uint64_t clr:20; |
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#else |
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uint64_t clr:20; |
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uint64_t reserved_20_63:44; |
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#endif |
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} cn61xx; |
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}; |
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union cvmx_gpio_tx_set { |
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uint64_t u64; |
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struct cvmx_gpio_tx_set_s { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_24_63:40; |
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uint64_t set:24; |
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#else |
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uint64_t set:24; |
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uint64_t reserved_24_63:40; |
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#endif |
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} s; |
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struct cvmx_gpio_tx_set_cn38xx { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_16_63:48; |
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uint64_t set:16; |
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#else |
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uint64_t set:16; |
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uint64_t reserved_16_63:48; |
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#endif |
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} cn38xx; |
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struct cvmx_gpio_tx_set_cn61xx { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_20_63:44; |
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uint64_t set:20; |
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#else |
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uint64_t set:20; |
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uint64_t reserved_20_63:44; |
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#endif |
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} cn61xx; |
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}; |
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union cvmx_gpio_xbit_cfgx { |
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uint64_t u64; |
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struct cvmx_gpio_xbit_cfgx_s { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_17_63:47; |
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uint64_t synce_sel:2; |
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uint64_t clk_gen:1; |
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uint64_t clk_sel:2; |
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uint64_t fil_sel:4; |
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uint64_t fil_cnt:4; |
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uint64_t int_type:1; |
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uint64_t int_en:1; |
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uint64_t rx_xor:1; |
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uint64_t tx_oe:1; |
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#else |
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uint64_t tx_oe:1; |
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uint64_t rx_xor:1; |
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uint64_t int_en:1; |
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uint64_t int_type:1; |
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uint64_t fil_cnt:4; |
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uint64_t fil_sel:4; |
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uint64_t clk_sel:2; |
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uint64_t clk_gen:1; |
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uint64_t synce_sel:2; |
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uint64_t reserved_17_63:47; |
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#endif |
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} s; |
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struct cvmx_gpio_xbit_cfgx_cn30xx { |
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#ifdef __BIG_ENDIAN_BITFIELD |
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uint64_t reserved_12_63:52; |
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uint64_t fil_sel:4; |
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uint64_t fil_cnt:4; |
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uint64_t reserved_2_3:2; |
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uint64_t rx_xor:1; |
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uint64_t tx_oe:1; |
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#else |
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uint64_t tx_oe:1; |
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uint64_t rx_xor:1; |
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uint64_t reserved_2_3:2; |
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uint64_t fil_cnt:4; |
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uint64_t fil_sel:4; |
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uint64_t reserved_12_63:52; |
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#endif |
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} cn30xx; |
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}; |
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#endif
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