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619 lines
18 KiB
619 lines
18 KiB
/***********************license start*************** |
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* Author: Cavium Networks |
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* |
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* Contact: [email protected] |
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* This file is part of the OCTEON SDK |
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* |
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* Copyright (c) 2003-2008 Cavium Networks |
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* |
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* This file is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License, Version 2, as |
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* published by the Free Software Foundation. |
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* |
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* This file is distributed in the hope that it will be useful, but |
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or |
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* NONINFRINGEMENT. See the GNU General Public License for more |
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* details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this file; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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* or visit http://www.gnu.org/licenses/. |
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* |
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* This file may also be available under a different license from Cavium. |
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* Contact Cavium Networks for more information |
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***********************license end**************************************/ |
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|
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/* |
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* Interface to the hardware Fetch and Add Unit. |
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*/ |
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|
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#ifndef __CVMX_FAU_H__ |
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#define __CVMX_FAU_H__ |
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|
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/* |
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* Octeon Fetch and Add Unit (FAU) |
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*/ |
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#define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0) |
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#define CVMX_FAU_BITS_SCRADDR 63, 56 |
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#define CVMX_FAU_BITS_LEN 55, 48 |
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#define CVMX_FAU_BITS_INEVAL 35, 14 |
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#define CVMX_FAU_BITS_TAGWAIT 13, 13 |
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#define CVMX_FAU_BITS_NOADD 13, 13 |
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#define CVMX_FAU_BITS_SIZE 12, 11 |
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#define CVMX_FAU_BITS_REGISTER 10, 0 |
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typedef enum { |
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CVMX_FAU_OP_SIZE_8 = 0, |
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CVMX_FAU_OP_SIZE_16 = 1, |
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CVMX_FAU_OP_SIZE_32 = 2, |
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CVMX_FAU_OP_SIZE_64 = 3 |
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} cvmx_fau_op_size_t; |
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|
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/** |
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* Tagwait return definition. If a timeout occurs, the error |
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* bit will be set. Otherwise the value of the register before |
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* the update will be returned. |
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*/ |
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typedef struct { |
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uint64_t error:1; |
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int64_t value:63; |
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} cvmx_fau_tagwait64_t; |
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|
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/** |
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* Tagwait return definition. If a timeout occurs, the error |
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* bit will be set. Otherwise the value of the register before |
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* the update will be returned. |
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*/ |
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typedef struct { |
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uint64_t error:1; |
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int32_t value:31; |
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} cvmx_fau_tagwait32_t; |
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|
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/** |
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* Tagwait return definition. If a timeout occurs, the error |
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* bit will be set. Otherwise the value of the register before |
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* the update will be returned. |
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*/ |
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typedef struct { |
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uint64_t error:1; |
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int16_t value:15; |
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} cvmx_fau_tagwait16_t; |
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|
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/** |
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* Tagwait return definition. If a timeout occurs, the error |
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* bit will be set. Otherwise the value of the register before |
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* the update will be returned. |
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*/ |
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typedef struct { |
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uint64_t error:1; |
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int8_t value:7; |
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} cvmx_fau_tagwait8_t; |
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|
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/** |
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* Asynchronous tagwait return definition. If a timeout occurs, |
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* the error bit will be set. Otherwise the value of the |
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* register before the update will be returned. |
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*/ |
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typedef union { |
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uint64_t u64; |
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struct { |
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uint64_t invalid:1; |
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uint64_t data:63; /* unpredictable if invalid is set */ |
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} s; |
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} cvmx_fau_async_tagwait_result_t; |
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#ifdef __BIG_ENDIAN_BITFIELD |
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#define SWIZZLE_8 0 |
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#define SWIZZLE_16 0 |
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#define SWIZZLE_32 0 |
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#else |
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#define SWIZZLE_8 0x7 |
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#define SWIZZLE_16 0x6 |
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#define SWIZZLE_32 0x4 |
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#endif |
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/** |
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* Builds a store I/O address for writing to the FAU |
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* |
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* @noadd: 0 = Store value is atomically added to the current value |
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* 1 = Store value is atomically written over the current value |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 2 for 16 bit access. |
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* - Step by 4 for 32 bit access. |
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* - Step by 8 for 64 bit access. |
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* Returns Address to store for atomic update |
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*/ |
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static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) |
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{ |
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return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | |
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cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) | |
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cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); |
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} |
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/** |
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* Builds a I/O address for accessing the FAU |
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* |
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* @tagwait: Should the atomic add wait for the current tag switch |
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* operation to complete. |
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* - 0 = Don't wait |
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* - 1 = Wait for tag switch to complete |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 2 for 16 bit access. |
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* - Step by 4 for 32 bit access. |
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* - Step by 8 for 64 bit access. |
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* @value: Signed value to add. |
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* Note: When performing 32 and 64 bit access, only the low |
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* 22 bits are available. |
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* Returns Address to read from for atomic update |
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*/ |
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static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, |
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int64_t value) |
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{ |
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return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | |
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cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | |
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cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | |
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cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); |
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} |
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/** |
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* Perform an atomic 64 bit add |
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* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 8 for 64 bit access. |
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* @value: Signed value to add. |
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* Note: Only the low 22 bits are available. |
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* Returns Value of the register before the update |
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*/ |
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static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, |
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int64_t value) |
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{ |
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return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); |
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} |
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/** |
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* Perform an atomic 32 bit add |
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* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 4 for 32 bit access. |
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* @value: Signed value to add. |
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* Note: Only the low 22 bits are available. |
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* Returns Value of the register before the update |
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*/ |
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static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, |
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int32_t value) |
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{ |
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reg ^= SWIZZLE_32; |
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return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); |
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} |
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/** |
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* Perform an atomic 16 bit add |
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* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 2 for 16 bit access. |
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* @value: Signed value to add. |
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* Returns Value of the register before the update |
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*/ |
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static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, |
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int16_t value) |
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{ |
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reg ^= SWIZZLE_16; |
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return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value)); |
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} |
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/** |
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* Perform an atomic 8 bit add |
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* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* @value: Signed value to add. |
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* Returns Value of the register before the update |
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*/ |
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static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) |
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{ |
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reg ^= SWIZZLE_8; |
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return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value)); |
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} |
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|
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/** |
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* Perform an atomic 64 bit add after the current tag switch |
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* completes |
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* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 8 for 64 bit access. |
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* @value: Signed value to add. |
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* Note: Only the low 22 bits are available. |
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* Returns If a timeout occurs, the error bit will be set. Otherwise |
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* the value of the register before the update will be |
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* returned |
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*/ |
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static inline cvmx_fau_tagwait64_t |
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cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) |
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{ |
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union { |
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uint64_t i64; |
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cvmx_fau_tagwait64_t t; |
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} result; |
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result.i64 = |
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cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value)); |
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return result.t; |
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} |
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/** |
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* Perform an atomic 32 bit add after the current tag switch |
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* completes |
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* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 4 for 32 bit access. |
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* @value: Signed value to add. |
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* Note: Only the low 22 bits are available. |
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* Returns If a timeout occurs, the error bit will be set. Otherwise |
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* the value of the register before the update will be |
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* returned |
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*/ |
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static inline cvmx_fau_tagwait32_t |
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cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) |
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{ |
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union { |
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uint64_t i32; |
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cvmx_fau_tagwait32_t t; |
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} result; |
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reg ^= SWIZZLE_32; |
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result.i32 = |
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cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value)); |
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return result.t; |
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} |
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|
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/** |
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* Perform an atomic 16 bit add after the current tag switch |
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* completes |
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* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 2 for 16 bit access. |
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* @value: Signed value to add. |
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* Returns If a timeout occurs, the error bit will be set. Otherwise |
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* the value of the register before the update will be |
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* returned |
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*/ |
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static inline cvmx_fau_tagwait16_t |
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cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) |
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{ |
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union { |
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uint64_t i16; |
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cvmx_fau_tagwait16_t t; |
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} result; |
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reg ^= SWIZZLE_16; |
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result.i16 = |
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cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value)); |
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return result.t; |
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} |
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|
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/** |
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* Perform an atomic 8 bit add after the current tag switch |
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* completes |
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* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* @value: Signed value to add. |
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* Returns If a timeout occurs, the error bit will be set. Otherwise |
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* the value of the register before the update will be |
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* returned |
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*/ |
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static inline cvmx_fau_tagwait8_t |
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cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) |
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{ |
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union { |
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uint64_t i8; |
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cvmx_fau_tagwait8_t t; |
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} result; |
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reg ^= SWIZZLE_8; |
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result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value)); |
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return result.t; |
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} |
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/** |
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* Builds I/O data for async operations |
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* |
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* @scraddr: Scratch pad byte address to write to. Must be 8 byte aligned |
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* @value: Signed value to add. |
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* Note: When performing 32 and 64 bit access, only the low |
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* 22 bits are available. |
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* @tagwait: Should the atomic add wait for the current tag switch |
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* operation to complete. |
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* - 0 = Don't wait |
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* - 1 = Wait for tag switch to complete |
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* @size: The size of the operation: |
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* - CVMX_FAU_OP_SIZE_8 (0) = 8 bits |
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* - CVMX_FAU_OP_SIZE_16 (1) = 16 bits |
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* - CVMX_FAU_OP_SIZE_32 (2) = 32 bits |
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* - CVMX_FAU_OP_SIZE_64 (3) = 64 bits |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 2 for 16 bit access. |
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* - Step by 4 for 32 bit access. |
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* - Step by 8 for 64 bit access. |
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* Returns Data to write using cvmx_send_single |
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*/ |
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static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, |
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uint64_t tagwait, |
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cvmx_fau_op_size_t size, |
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uint64_t reg) |
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{ |
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return CVMX_FAU_LOAD_IO_ADDRESS | |
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cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) | |
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cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) | |
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cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | |
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cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | |
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cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) | |
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cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); |
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} |
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|
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/** |
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* Perform an async atomic 64 bit add. The old value is |
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* placed in the scratch memory at byte address scraddr. |
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* |
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* @scraddr: Scratch memory byte address to put response in. |
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* Must be 8 byte aligned. |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 8 for 64 bit access. |
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* @value: Signed value to add. |
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* Note: Only the low 22 bits are available. |
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* Returns Placed in the scratch pad register |
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*/ |
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static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr, |
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cvmx_fau_reg_64_t reg, |
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int64_t value) |
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{ |
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cvmx_send_single(__cvmx_fau_iobdma_data |
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(scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg)); |
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} |
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|
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/** |
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* Perform an async atomic 32 bit add. The old value is |
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* placed in the scratch memory at byte address scraddr. |
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* |
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* @scraddr: Scratch memory byte address to put response in. |
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* Must be 8 byte aligned. |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 4 for 32 bit access. |
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* @value: Signed value to add. |
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* Note: Only the low 22 bits are available. |
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* Returns Placed in the scratch pad register |
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*/ |
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static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, |
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cvmx_fau_reg_32_t reg, |
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int32_t value) |
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{ |
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cvmx_send_single(__cvmx_fau_iobdma_data |
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(scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg)); |
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} |
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|
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/** |
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* Perform an async atomic 16 bit add. The old value is |
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* placed in the scratch memory at byte address scraddr. |
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* |
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* @scraddr: Scratch memory byte address to put response in. |
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* Must be 8 byte aligned. |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 2 for 16 bit access. |
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* @value: Signed value to add. |
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* Returns Placed in the scratch pad register |
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*/ |
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static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr, |
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cvmx_fau_reg_16_t reg, |
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int16_t value) |
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{ |
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cvmx_send_single(__cvmx_fau_iobdma_data |
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(scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg)); |
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} |
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|
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/** |
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* Perform an async atomic 8 bit add. The old value is |
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* placed in the scratch memory at byte address scraddr. |
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* |
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* @scraddr: Scratch memory byte address to put response in. |
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* Must be 8 byte aligned. |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* @value: Signed value to add. |
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* Returns Placed in the scratch pad register |
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*/ |
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static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr, |
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cvmx_fau_reg_8_t reg, |
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int8_t value) |
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{ |
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cvmx_send_single(__cvmx_fau_iobdma_data |
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(scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg)); |
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} |
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|
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/** |
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* Perform an async atomic 64 bit add after the current tag |
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* switch completes. |
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* |
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* @scraddr: Scratch memory byte address to put response in. Must be |
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* 8 byte aligned. If a timeout occurs, the error bit (63) |
|
* will be set. Otherwise the value of the register before |
|
* the update will be returned |
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* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 8 for 64 bit access. |
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* @value: Signed value to add. |
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* Note: Only the low 22 bits are available. |
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* Returns Placed in the scratch pad register |
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*/ |
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static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, |
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cvmx_fau_reg_64_t reg, |
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int64_t value) |
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{ |
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cvmx_send_single(__cvmx_fau_iobdma_data |
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(scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg)); |
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} |
|
|
|
/** |
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* Perform an async atomic 32 bit add after the current tag |
|
* switch completes. |
|
* |
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* @scraddr: Scratch memory byte address to put response in. Must be |
|
* 8 byte aligned. If a timeout occurs, the error bit (63) |
|
* will be set. Otherwise the value of the register before |
|
* the update will be returned |
|
* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
|
* - Step by 4 for 32 bit access. |
|
* @value: Signed value to add. |
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* Note: Only the low 22 bits are available. |
|
* Returns Placed in the scratch pad register |
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*/ |
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static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, |
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cvmx_fau_reg_32_t reg, |
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int32_t value) |
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{ |
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cvmx_send_single(__cvmx_fau_iobdma_data |
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(scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg)); |
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} |
|
|
|
/** |
|
* Perform an async atomic 16 bit add after the current tag |
|
* switch completes. |
|
* |
|
* @scraddr: Scratch memory byte address to put response in. Must be |
|
* 8 byte aligned. If a timeout occurs, the error bit (63) |
|
* will be set. Otherwise the value of the register before |
|
* the update will be returned |
|
* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 2 for 16 bit access. |
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* @value: Signed value to add. |
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* |
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* Returns Placed in the scratch pad register |
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*/ |
|
static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr, |
|
cvmx_fau_reg_16_t reg, |
|
int16_t value) |
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{ |
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cvmx_send_single(__cvmx_fau_iobdma_data |
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(scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg)); |
|
} |
|
|
|
/** |
|
* Perform an async atomic 8 bit add after the current tag |
|
* switch completes. |
|
* |
|
* @scraddr: Scratch memory byte address to put response in. Must be |
|
* 8 byte aligned. If a timeout occurs, the error bit (63) |
|
* will be set. Otherwise the value of the register before |
|
* the update will be returned |
|
* |
|
* @reg: FAU atomic register to access. 0 <= reg < 2048. |
|
* @value: Signed value to add. |
|
* |
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* Returns Placed in the scratch pad register |
|
*/ |
|
static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr, |
|
cvmx_fau_reg_8_t reg, |
|
int8_t value) |
|
{ |
|
cvmx_send_single(__cvmx_fau_iobdma_data |
|
(scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg)); |
|
} |
|
|
|
/** |
|
* Perform an atomic 64 bit add |
|
* |
|
* @reg: FAU atomic register to access. 0 <= reg < 2048. |
|
* - Step by 8 for 64 bit access. |
|
* @value: Signed value to add. |
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*/ |
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static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) |
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{ |
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cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value); |
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} |
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/** |
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* Perform an atomic 32 bit add |
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* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 4 for 32 bit access. |
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* @value: Signed value to add. |
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*/ |
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static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) |
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{ |
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reg ^= SWIZZLE_32; |
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cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value); |
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} |
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|
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/** |
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* Perform an atomic 16 bit add |
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* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 2 for 16 bit access. |
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* @value: Signed value to add. |
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*/ |
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static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value) |
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{ |
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reg ^= SWIZZLE_16; |
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cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value); |
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} |
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|
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/** |
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* Perform an atomic 8 bit add |
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* |
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* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* @value: Signed value to add. |
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*/ |
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static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value) |
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{ |
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reg ^= SWIZZLE_8; |
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cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value); |
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} |
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|
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/** |
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* Perform an atomic 64 bit write |
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* |
|
* @reg: FAU atomic register to access. 0 <= reg < 2048. |
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* - Step by 8 for 64 bit access. |
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* @value: Signed value to write. |
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*/ |
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static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) |
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{ |
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cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value); |
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} |
|
|
|
/** |
|
* Perform an atomic 32 bit write |
|
* |
|
* @reg: FAU atomic register to access. 0 <= reg < 2048. |
|
* - Step by 4 for 32 bit access. |
|
* @value: Signed value to write. |
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*/ |
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static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) |
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{ |
|
reg ^= SWIZZLE_32; |
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cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value); |
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} |
|
|
|
/** |
|
* Perform an atomic 16 bit write |
|
* |
|
* @reg: FAU atomic register to access. 0 <= reg < 2048. |
|
* - Step by 2 for 16 bit access. |
|
* @value: Signed value to write. |
|
*/ |
|
static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value) |
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{ |
|
reg ^= SWIZZLE_16; |
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cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value); |
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} |
|
|
|
/** |
|
* Perform an atomic 8 bit write |
|
* |
|
* @reg: FAU atomic register to access. 0 <= reg < 2048. |
|
* @value: Signed value to write. |
|
*/ |
|
static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value) |
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{ |
|
reg ^= SWIZZLE_8; |
|
cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value); |
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} |
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|
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#endif /* __CVMX_FAU_H__ */
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