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69 lines
1.9 KiB
69 lines
1.9 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* |
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* Copyright (C) 2010 John Crispin <[email protected]> |
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*/ |
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#ifndef _LTQ_FALCON_H__ |
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#define _LTQ_FALCON_H__ |
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#ifdef CONFIG_SOC_FALCON |
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#include <linux/pinctrl/pinctrl.h> |
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#include <lantiq.h> |
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/* Chip IDs */ |
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#define SOC_ID_FALCON 0x01B8 |
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/* SoC Types */ |
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#define SOC_TYPE_FALCON 0x01 |
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/* |
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* during early_printk no ioremap possible at this early stage |
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* let's use KSEG1 instead |
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*/ |
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#define LTQ_ASC0_BASE_ADDR 0x1E100C00 |
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#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) |
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/* WDT */ |
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#define LTQ_RST_CAUSE_WDTRST 0x0002 |
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/* CHIP ID */ |
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#define LTQ_STATUS_BASE_ADDR 0x1E802000 |
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#define FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c)) |
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#define FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38)) |
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#define FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40)) |
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/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */ |
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#define SYSCTL_SYS1 0 |
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#define SYSCTL_SYSETH 1 |
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#define SYSCTL_SYSGPE 2 |
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/* BOOT_SEL - find what boot media we have */ |
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#define BS_FLASH 0x1 |
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#define BS_SPI 0x4 |
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/* global register ranges */ |
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extern __iomem void *ltq_ebu_membase; |
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extern __iomem void *ltq_sys1_membase; |
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#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) |
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#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) |
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#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y)) |
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#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x)) |
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#define ltq_sys1_w32_mask(clear, set, reg) \ |
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ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) |
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/* allow the gpio and pinctrl drivers to talk to eachother */ |
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extern int pinctrl_falcon_get_range_size(int id); |
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extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range); |
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/* |
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* to keep the irq code generic we need to define this to 0 as falcon |
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* has no EIU/EBU |
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*/ |
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#define LTQ_EBU_PCC_ISTAT 0 |
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#endif /* CONFIG_SOC_FALCON */ |
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#endif /* _LTQ_XWAY_H__ */
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