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97 lines
2.4 KiB
97 lines
2.4 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd |
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* Author: Tony Xie <[email protected]> |
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*/ |
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#ifndef __MACH_ROCKCHIP_PM_H |
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#define __MACH_ROCKCHIP_PM_H |
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extern unsigned long rkpm_bootdata_cpusp; |
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extern unsigned long rkpm_bootdata_cpu_code; |
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extern unsigned long rkpm_bootdata_l2ctlr_f; |
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extern unsigned long rkpm_bootdata_l2ctlr; |
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extern unsigned long rkpm_bootdata_ddr_code; |
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extern unsigned long rkpm_bootdata_ddr_data; |
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extern unsigned long rk3288_bootram_sz; |
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void rockchip_slp_cpu_resume(void); |
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#ifdef CONFIG_PM_SLEEP |
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void __init rockchip_suspend_init(void); |
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#else |
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static inline void rockchip_suspend_init(void) |
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{ |
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} |
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#endif |
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/****** following is rk3288 defined **********/ |
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#define RK3288_PMU_WAKEUP_CFG0 0x00 |
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#define RK3288_PMU_WAKEUP_CFG1 0x04 |
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#define RK3288_PMU_PWRMODE_CON 0x18 |
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#define RK3288_PMU_OSC_CNT 0x20 |
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#define RK3288_PMU_PLL_CNT 0x24 |
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#define RK3288_PMU_STABL_CNT 0x28 |
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#define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c |
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#define RK3288_PMU_DDR1IO_PWRON_CNT 0x30 |
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#define RK3288_PMU_CORE_PWRDWN_CNT 0x34 |
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#define RK3288_PMU_CORE_PWRUP_CNT 0x38 |
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#define RK3288_PMU_GPU_PWRDWN_CNT 0x3c |
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#define RK3288_PMU_GPU_PWRUP_CNT 0x40 |
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#define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44 |
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#define RK3288_PMU_PWRMODE_CON1 0x90 |
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#define RK3288_SGRF_SOC_CON0 (0x0000) |
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#define RK3288_SGRF_FAST_BOOT_ADDR (0x0120) |
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#define SGRF_PCLK_WDT_GATE BIT(6) |
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#define SGRF_PCLK_WDT_GATE_WRITE BIT(22) |
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#define SGRF_FAST_BOOT_EN BIT(8) |
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#define SGRF_FAST_BOOT_EN_WRITE BIT(24) |
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#define RK3288_SGRF_CPU_CON0 (0x40) |
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#define SGRF_DAPDEVICEEN BIT(0) |
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#define SGRF_DAPDEVICEEN_WRITE BIT(16) |
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/* PMU_WAKEUP_CFG1 bits */ |
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#define PMU_ARMINT_WAKEUP_EN BIT(0) |
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#define PMU_GPIOINT_WAKEUP_EN BIT(3) |
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enum rk3288_pwr_mode_con { |
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PMU_PWR_MODE_EN = 0, |
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PMU_CLK_CORE_SRC_GATE_EN, |
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PMU_GLOBAL_INT_DISABLE, |
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PMU_L2FLUSH_EN, |
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PMU_BUS_PD_EN, |
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PMU_A12_0_PD_EN, |
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PMU_SCU_EN, |
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PMU_PLL_PD_EN, |
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PMU_CHIP_PD_EN, /* POWER OFF PIN ENABLE */ |
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PMU_PWROFF_COMB, |
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PMU_ALIVE_USE_LF, |
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PMU_PMU_USE_LF, |
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PMU_OSC_24M_DIS, |
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PMU_INPUT_CLAMP_EN, |
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PMU_WAKEUP_RESET_EN, |
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PMU_SREF0_ENTER_EN, |
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PMU_SREF1_ENTER_EN, |
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PMU_DDR0IO_RET_EN, |
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PMU_DDR1IO_RET_EN, |
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PMU_DDR0_GATING_EN, |
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PMU_DDR1_GATING_EN, |
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PMU_DDR0IO_RET_DE_REQ, |
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PMU_DDR1IO_RET_DE_REQ |
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}; |
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enum rk3288_pwr_mode_con1 { |
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PMU_CLR_BUS = 0, |
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PMU_CLR_CORE, |
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PMU_CLR_CPUP, |
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PMU_CLR_ALIVE, |
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PMU_CLR_DMA, |
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PMU_CLR_PERI, |
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PMU_CLR_GPU, |
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PMU_CLR_VIDEO, |
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PMU_CLR_HEVC, |
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PMU_CLR_VIO, |
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}; |
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#endif /* __MACH_ROCKCHIP_PM_H */
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