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306 lines
6.7 KiB
306 lines
6.7 KiB
/* |
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* Accelerated CRC32(C) using ARM CRC, NEON and Crypto Extensions instructions |
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* |
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* Copyright (C) 2016 Linaro Ltd <ard.biesheuvel@linaro.org> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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/* GPL HEADER START |
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* |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 only, |
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* as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, but |
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* WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* General Public License version 2 for more details (a copy is included |
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* in the LICENSE file that accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License |
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* version 2 along with this program; If not, see http://www.gnu.org/licenses |
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* |
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* Please visit http://www.xyratex.com/contact if you need additional |
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* information or have any questions. |
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* |
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* GPL HEADER END |
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*/ |
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/* |
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* Copyright 2012 Xyratex Technology Limited |
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* |
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* Using hardware provided PCLMULQDQ instruction to accelerate the CRC32 |
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* calculation. |
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* CRC32 polynomial:0x04c11db7(BE)/0xEDB88320(LE) |
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* PCLMULQDQ is a new instruction in Intel SSE4.2, the reference can be found |
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* at: |
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* https://www.intel.com/products/processor/manuals/ |
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* Intel(R) 64 and IA-32 Architectures Software Developer's Manual |
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* Volume 2B: Instruction Set Reference, N-Z |
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* |
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* Authors: Gregory Prestas <Gregory_Prestas@us.xyratex.com> |
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* Alexander Boyko <Alexander_Boyko@xyratex.com> |
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*/ |
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#include <linux/linkage.h> |
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#include <asm/assembler.h> |
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.text |
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.align 6 |
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.arch armv8-a |
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.arch_extension crc |
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.fpu crypto-neon-fp-armv8 |
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.Lcrc32_constants: |
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/* |
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* [x4*128+32 mod P(x) << 32)]' << 1 = 0x154442bd4 |
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* #define CONSTANT_R1 0x154442bd4LL |
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* |
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* [(x4*128-32 mod P(x) << 32)]' << 1 = 0x1c6e41596 |
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* #define CONSTANT_R2 0x1c6e41596LL |
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*/ |
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.quad 0x0000000154442bd4 |
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.quad 0x00000001c6e41596 |
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/* |
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* [(x128+32 mod P(x) << 32)]' << 1 = 0x1751997d0 |
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* #define CONSTANT_R3 0x1751997d0LL |
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* |
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* [(x128-32 mod P(x) << 32)]' << 1 = 0x0ccaa009e |
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* #define CONSTANT_R4 0x0ccaa009eLL |
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*/ |
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.quad 0x00000001751997d0 |
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.quad 0x00000000ccaa009e |
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/* |
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* [(x64 mod P(x) << 32)]' << 1 = 0x163cd6124 |
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* #define CONSTANT_R5 0x163cd6124LL |
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*/ |
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.quad 0x0000000163cd6124 |
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.quad 0x00000000FFFFFFFF |
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/* |
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* #define CRCPOLY_TRUE_LE_FULL 0x1DB710641LL |
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* |
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* Barrett Reduction constant (u64`) = u` = (x**64 / P(x))` |
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* = 0x1F7011641LL |
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* #define CONSTANT_RU 0x1F7011641LL |
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*/ |
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.quad 0x00000001DB710641 |
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.quad 0x00000001F7011641 |
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.Lcrc32c_constants: |
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.quad 0x00000000740eef02 |
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.quad 0x000000009e4addf8 |
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.quad 0x00000000f20c0dfe |
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.quad 0x000000014cd00bd6 |
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.quad 0x00000000dd45aab8 |
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.quad 0x00000000FFFFFFFF |
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.quad 0x0000000105ec76f0 |
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.quad 0x00000000dea713f1 |
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dCONSTANTl .req d0 |
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dCONSTANTh .req d1 |
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qCONSTANT .req q0 |
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BUF .req r0 |
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LEN .req r1 |
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CRC .req r2 |
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qzr .req q9 |
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/** |
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* Calculate crc32 |
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* BUF - buffer |
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* LEN - sizeof buffer (multiple of 16 bytes), LEN should be > 63 |
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* CRC - initial crc32 |
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* return %eax crc32 |
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* uint crc32_pmull_le(unsigned char const *buffer, |
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* size_t len, uint crc32) |
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*/ |
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ENTRY(crc32_pmull_le) |
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adr r3, .Lcrc32_constants |
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b 0f |
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ENTRY(crc32c_pmull_le) |
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adr r3, .Lcrc32c_constants |
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0: bic LEN, LEN, #15 |
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vld1.8 {q1-q2}, [BUF, :128]! |
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vld1.8 {q3-q4}, [BUF, :128]! |
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vmov.i8 qzr, #0 |
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vmov.i8 qCONSTANT, #0 |
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vmov.32 dCONSTANTl[0], CRC |
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veor.8 d2, d2, dCONSTANTl |
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sub LEN, LEN, #0x40 |
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cmp LEN, #0x40 |
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blt less_64 |
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vld1.64 {qCONSTANT}, [r3] |
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loop_64: /* 64 bytes Full cache line folding */ |
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sub LEN, LEN, #0x40 |
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vmull.p64 q5, d3, dCONSTANTh |
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vmull.p64 q6, d5, dCONSTANTh |
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vmull.p64 q7, d7, dCONSTANTh |
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vmull.p64 q8, d9, dCONSTANTh |
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vmull.p64 q1, d2, dCONSTANTl |
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vmull.p64 q2, d4, dCONSTANTl |
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vmull.p64 q3, d6, dCONSTANTl |
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vmull.p64 q4, d8, dCONSTANTl |
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veor.8 q1, q1, q5 |
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vld1.8 {q5}, [BUF, :128]! |
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veor.8 q2, q2, q6 |
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vld1.8 {q6}, [BUF, :128]! |
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veor.8 q3, q3, q7 |
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vld1.8 {q7}, [BUF, :128]! |
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veor.8 q4, q4, q8 |
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vld1.8 {q8}, [BUF, :128]! |
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veor.8 q1, q1, q5 |
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veor.8 q2, q2, q6 |
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veor.8 q3, q3, q7 |
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veor.8 q4, q4, q8 |
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cmp LEN, #0x40 |
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bge loop_64 |
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less_64: /* Folding cache line into 128bit */ |
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vldr dCONSTANTl, [r3, #16] |
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vldr dCONSTANTh, [r3, #24] |
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vmull.p64 q5, d3, dCONSTANTh |
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vmull.p64 q1, d2, dCONSTANTl |
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veor.8 q1, q1, q5 |
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veor.8 q1, q1, q2 |
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vmull.p64 q5, d3, dCONSTANTh |
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vmull.p64 q1, d2, dCONSTANTl |
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veor.8 q1, q1, q5 |
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veor.8 q1, q1, q3 |
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vmull.p64 q5, d3, dCONSTANTh |
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vmull.p64 q1, d2, dCONSTANTl |
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veor.8 q1, q1, q5 |
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veor.8 q1, q1, q4 |
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teq LEN, #0 |
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beq fold_64 |
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loop_16: /* Folding rest buffer into 128bit */ |
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subs LEN, LEN, #0x10 |
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vld1.8 {q2}, [BUF, :128]! |
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vmull.p64 q5, d3, dCONSTANTh |
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vmull.p64 q1, d2, dCONSTANTl |
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veor.8 q1, q1, q5 |
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veor.8 q1, q1, q2 |
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bne loop_16 |
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fold_64: |
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/* perform the last 64 bit fold, also adds 32 zeroes |
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* to the input stream */ |
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vmull.p64 q2, d2, dCONSTANTh |
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vext.8 q1, q1, qzr, #8 |
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veor.8 q1, q1, q2 |
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/* final 32-bit fold */ |
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vldr dCONSTANTl, [r3, #32] |
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vldr d6, [r3, #40] |
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vmov.i8 d7, #0 |
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vext.8 q2, q1, qzr, #4 |
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vand.8 d2, d2, d6 |
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vmull.p64 q1, d2, dCONSTANTl |
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veor.8 q1, q1, q2 |
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/* Finish up with the bit-reversed barrett reduction 64 ==> 32 bits */ |
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vldr dCONSTANTl, [r3, #48] |
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vldr dCONSTANTh, [r3, #56] |
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vand.8 q2, q1, q3 |
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vext.8 q2, qzr, q2, #8 |
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vmull.p64 q2, d5, dCONSTANTh |
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vand.8 q2, q2, q3 |
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vmull.p64 q2, d4, dCONSTANTl |
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veor.8 q1, q1, q2 |
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vmov r0, s5 |
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bx lr |
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ENDPROC(crc32_pmull_le) |
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ENDPROC(crc32c_pmull_le) |
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.macro __crc32, c |
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subs ip, r2, #8 |
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bmi .Ltail\c |
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tst r1, #3 |
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bne .Lunaligned\c |
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teq ip, #0 |
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.Laligned8\c: |
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ldrd r2, r3, [r1], #8 |
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ARM_BE8(rev r2, r2 ) |
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ARM_BE8(rev r3, r3 ) |
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crc32\c\()w r0, r0, r2 |
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crc32\c\()w r0, r0, r3 |
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bxeq lr |
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subs ip, ip, #8 |
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bpl .Laligned8\c |
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.Ltail\c: |
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tst ip, #4 |
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beq 2f |
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ldr r3, [r1], #4 |
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ARM_BE8(rev r3, r3 ) |
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crc32\c\()w r0, r0, r3 |
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2: tst ip, #2 |
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beq 1f |
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ldrh r3, [r1], #2 |
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ARM_BE8(rev16 r3, r3 ) |
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crc32\c\()h r0, r0, r3 |
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1: tst ip, #1 |
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bxeq lr |
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ldrb r3, [r1] |
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crc32\c\()b r0, r0, r3 |
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bx lr |
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.Lunaligned\c: |
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tst r1, #1 |
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beq 2f |
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ldrb r3, [r1], #1 |
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subs r2, r2, #1 |
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crc32\c\()b r0, r0, r3 |
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tst r1, #2 |
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beq 0f |
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2: ldrh r3, [r1], #2 |
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subs r2, r2, #2 |
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ARM_BE8(rev16 r3, r3 ) |
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crc32\c\()h r0, r0, r3 |
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0: subs ip, r2, #8 |
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bpl .Laligned8\c |
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b .Ltail\c |
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.endm |
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.align 5 |
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ENTRY(crc32_armv8_le) |
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__crc32 |
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ENDPROC(crc32_armv8_le) |
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.align 5 |
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ENTRY(crc32c_armv8_le) |
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__crc32 c |
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ENDPROC(crc32c_armv8_le)
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