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103 lines
2.4 KiB
103 lines
2.4 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2004, 2007-2010, 2011-2012, 2019-20 Synopsys, Inc. (www.synopsys.com) |
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* |
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* MMUv3 (arc700) / MMUv4 (archs) are software page walked and software managed. |
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* This file contains the TLB access registers and commands |
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*/ |
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#ifndef _ASM_ARC_MMU_ARCV2_H |
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#define _ASM_ARC_MMU_ARCV2_H |
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/* |
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* TLB Management regs |
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*/ |
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#define ARC_REG_MMU_BCR 0x06f |
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#ifdef CONFIG_ARC_MMU_V3 |
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#define ARC_REG_TLBPD0 0x405 |
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#define ARC_REG_TLBPD1 0x406 |
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#define ARC_REG_TLBPD1HI 0 /* Dummy: allows common code */ |
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#define ARC_REG_TLBINDEX 0x407 |
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#define ARC_REG_TLBCOMMAND 0x408 |
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#define ARC_REG_PID 0x409 |
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#define ARC_REG_SCRATCH_DATA0 0x418 |
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#else |
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#define ARC_REG_TLBPD0 0x460 |
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#define ARC_REG_TLBPD1 0x461 |
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#define ARC_REG_TLBPD1HI 0x463 |
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#define ARC_REG_TLBINDEX 0x464 |
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#define ARC_REG_TLBCOMMAND 0x465 |
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#define ARC_REG_PID 0x468 |
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#define ARC_REG_SCRATCH_DATA0 0x46c |
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#endif |
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/* Bits in MMU PID reg */ |
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#define __TLB_ENABLE (1 << 31) |
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#define __PROG_ENABLE (1 << 30) |
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#define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE) |
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/* Bits in TLB Index reg */ |
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#define TLB_LKUP_ERR 0x80000000 |
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#ifdef CONFIG_ARC_MMU_V3 |
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#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001) |
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#else |
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#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000) |
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#endif |
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/* |
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* TLB Commands |
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*/ |
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#define TLBWrite 0x1 |
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#define TLBRead 0x2 |
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#define TLBGetIndex 0x3 |
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#define TLBProbe 0x4 |
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#define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */ |
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#define TLBIVUTLB 0x6 /* explicitly inv uTLBs */ |
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#ifdef CONFIG_ARC_MMU_V4 |
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#define TLBInsertEntry 0x7 |
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#define TLBDeleteEntry 0x8 |
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#endif |
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/* Masks for actual TLB "PD"s */ |
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#define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_HW_SZ) |
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#define PTE_BITS_RWX (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ) |
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#define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK_PHYS | _PAGE_CACHEABLE) |
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#ifndef __ASSEMBLY__ |
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struct mm_struct; |
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extern int pae40_exist_but_not_enab(void); |
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static inline int is_pae40_enabled(void) |
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{ |
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return IS_ENABLED(CONFIG_ARC_HAS_PAE40); |
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} |
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static inline void mmu_setup_asid(struct mm_struct *mm, unsigned long asid) |
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{ |
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write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE); |
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} |
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static inline void mmu_setup_pgd(struct mm_struct *mm, void *pgd) |
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{ |
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/* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */ |
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#ifdef CONFIG_ISA_ARCV2 |
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write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd); |
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#endif |
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} |
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#else |
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.macro ARC_MMU_REENABLE reg |
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lr \reg, [ARC_REG_PID] |
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or \reg, \reg, MMU_ENABLE |
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sr \reg, [ARC_REG_PID] |
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.endm |
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#endif /* !__ASSEMBLY__ */ |
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#endif
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