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1276 lines
35 KiB
1276 lines
35 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. |
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* |
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* lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include <linux/regmap.h> |
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#include <sound/soc.h> |
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#include <sound/soc-dai.h> |
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#include "lpass-lpaif-reg.h" |
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#include "lpass.h" |
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|
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#define LPASS_CPU_MAX_MI2S_LINES 4 |
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#define LPASS_CPU_I2S_SD0_MASK BIT(0) |
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#define LPASS_CPU_I2S_SD1_MASK BIT(1) |
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#define LPASS_CPU_I2S_SD2_MASK BIT(2) |
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#define LPASS_CPU_I2S_SD3_MASK BIT(3) |
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#define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0) |
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#define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2) |
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#define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0) |
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#define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0) |
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#define LPASS_REG_READ 1 |
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#define LPASS_REG_WRITE 0 |
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|
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/* |
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* Channel maps for Quad channel playbacks on MI2S Secondary |
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*/ |
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static struct snd_pcm_chmap_elem lpass_quad_chmaps[] = { |
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{ .channels = 4, |
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.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_RL, |
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SNDRV_CHMAP_FR, SNDRV_CHMAP_RR } }, |
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{ } |
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}; |
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static int lpass_cpu_init_i2sctl_bitfields(struct device *dev, |
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struct lpaif_i2sctl *i2sctl, struct regmap *map) |
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{ |
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struct lpass_data *drvdata = dev_get_drvdata(dev); |
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struct lpass_variant *v = drvdata->variant; |
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|
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i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback); |
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i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken); |
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i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode); |
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i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono); |
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i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen); |
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i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode); |
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i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono); |
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i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc); |
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i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth); |
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if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) || |
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IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) || |
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IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) || |
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IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) || |
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IS_ERR(i2sctl->bitwidth)) |
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return -EINVAL; |
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return 0; |
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} |
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|
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static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
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unsigned int freq, int dir) |
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{ |
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); |
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int ret; |
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ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq); |
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if (ret) |
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dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n", |
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freq, ret); |
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return ret; |
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} |
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static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); |
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int ret; |
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ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]); |
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if (ret) { |
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dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret); |
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return ret; |
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} |
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ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]); |
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if (ret) { |
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dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); |
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clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); |
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return ret; |
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} |
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return 0; |
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} |
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static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); |
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struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; |
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unsigned int id = dai->driver->id; |
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|
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clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); |
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/* |
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* Ensure LRCLK is disabled even in device node validation. |
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* Will not impact if disabled in lpass_cpu_daiops_trigger() |
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* suspend. |
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*/ |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_DISABLE); |
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else |
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regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_DISABLE); |
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|
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/* |
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* BCLK may not be enabled if lpass_cpu_daiops_prepare is called before |
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* lpass_cpu_daiops_shutdown. It's paired with the clk_enable in |
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* lpass_cpu_daiops_prepare. |
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*/ |
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if (drvdata->mi2s_was_prepared[dai->driver->id]) { |
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drvdata->mi2s_was_prepared[dai->driver->id] = false; |
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clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]); |
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} |
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clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]); |
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} |
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static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) |
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{ |
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); |
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struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; |
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unsigned int id = dai->driver->id; |
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snd_pcm_format_t format = params_format(params); |
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unsigned int channels = params_channels(params); |
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unsigned int rate = params_rate(params); |
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unsigned int mode; |
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unsigned int regval; |
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int bitwidth, ret; |
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bitwidth = snd_pcm_format_width(format); |
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if (bitwidth < 0) { |
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dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth); |
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return bitwidth; |
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} |
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ret = regmap_fields_write(i2sctl->loopback, id, |
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LPAIF_I2SCTL_LOOPBACK_DISABLE); |
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if (ret) { |
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dev_err(dai->dev, "error updating loopback field: %d\n", ret); |
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return ret; |
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} |
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ret = regmap_fields_write(i2sctl->wssrc, id, |
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LPAIF_I2SCTL_WSSRC_INTERNAL); |
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if (ret) { |
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dev_err(dai->dev, "error updating wssrc field: %d\n", ret); |
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return ret; |
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} |
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|
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switch (bitwidth) { |
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case 16: |
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regval = LPAIF_I2SCTL_BITWIDTH_16; |
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break; |
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case 24: |
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regval = LPAIF_I2SCTL_BITWIDTH_24; |
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break; |
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case 32: |
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regval = LPAIF_I2SCTL_BITWIDTH_32; |
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break; |
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default: |
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dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth); |
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return -EINVAL; |
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} |
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ret = regmap_fields_write(i2sctl->bitwidth, id, regval); |
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if (ret) { |
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dev_err(dai->dev, "error updating bitwidth field: %d\n", ret); |
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return ret; |
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} |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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mode = drvdata->mi2s_playback_sd_mode[id]; |
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else |
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mode = drvdata->mi2s_capture_sd_mode[id]; |
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|
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if (!mode) { |
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dev_err(dai->dev, "no line is assigned\n"); |
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return -EINVAL; |
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} |
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switch (channels) { |
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case 1: |
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case 2: |
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switch (mode) { |
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case LPAIF_I2SCTL_MODE_QUAD01: |
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case LPAIF_I2SCTL_MODE_6CH: |
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case LPAIF_I2SCTL_MODE_8CH: |
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mode = LPAIF_I2SCTL_MODE_SD0; |
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break; |
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case LPAIF_I2SCTL_MODE_QUAD23: |
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mode = LPAIF_I2SCTL_MODE_SD2; |
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break; |
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} |
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|
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break; |
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case 4: |
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if (mode < LPAIF_I2SCTL_MODE_QUAD01) { |
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dev_err(dai->dev, "cannot configure 4 channels with mode %d\n", |
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mode); |
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return -EINVAL; |
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} |
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switch (mode) { |
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case LPAIF_I2SCTL_MODE_6CH: |
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case LPAIF_I2SCTL_MODE_8CH: |
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mode = LPAIF_I2SCTL_MODE_QUAD01; |
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break; |
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} |
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break; |
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case 6: |
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if (mode < LPAIF_I2SCTL_MODE_6CH) { |
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dev_err(dai->dev, "cannot configure 6 channels with mode %d\n", |
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mode); |
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return -EINVAL; |
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} |
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switch (mode) { |
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case LPAIF_I2SCTL_MODE_8CH: |
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mode = LPAIF_I2SCTL_MODE_6CH; |
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break; |
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} |
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break; |
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case 8: |
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if (mode < LPAIF_I2SCTL_MODE_8CH) { |
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dev_err(dai->dev, "cannot configure 8 channels with mode %d\n", |
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mode); |
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return -EINVAL; |
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} |
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break; |
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default: |
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dev_err(dai->dev, "invalid channels given: %u\n", channels); |
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return -EINVAL; |
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} |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
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ret = regmap_fields_write(i2sctl->spkmode, id, |
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LPAIF_I2SCTL_SPKMODE(mode)); |
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if (ret) { |
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dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n", |
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ret); |
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return ret; |
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} |
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if (channels >= 2) |
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ret = regmap_fields_write(i2sctl->spkmono, id, |
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LPAIF_I2SCTL_SPKMONO_STEREO); |
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else |
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ret = regmap_fields_write(i2sctl->spkmono, id, |
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LPAIF_I2SCTL_SPKMONO_MONO); |
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} else { |
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ret = regmap_fields_write(i2sctl->micmode, id, |
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LPAIF_I2SCTL_MICMODE(mode)); |
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if (ret) { |
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dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n", |
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ret); |
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return ret; |
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} |
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if (channels >= 2) |
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ret = regmap_fields_write(i2sctl->micmono, id, |
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LPAIF_I2SCTL_MICMONO_STEREO); |
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else |
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ret = regmap_fields_write(i2sctl->micmono, id, |
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LPAIF_I2SCTL_MICMONO_MONO); |
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} |
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if (ret) { |
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dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n", |
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ret); |
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return ret; |
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} |
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ret = clk_set_rate(drvdata->mi2s_bit_clk[id], |
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rate * bitwidth * 2); |
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if (ret) { |
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dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n", |
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rate * bitwidth * 2, ret); |
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return ret; |
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} |
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return 0; |
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} |
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static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream, |
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int cmd, struct snd_soc_dai *dai) |
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{ |
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); |
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struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; |
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unsigned int id = dai->driver->id; |
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int ret = -EINVAL; |
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|
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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/* |
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* Ensure lpass BCLK/LRCLK is enabled during |
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* device resume as lpass_cpu_daiops_prepare() is not called |
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* after the device resumes. We don't check mi2s_was_prepared before |
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* enable/disable BCLK in trigger events because: |
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* 1. These trigger events are paired, so the BCLK |
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* enable_count is balanced. |
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* 2. the BCLK can be shared (ex: headset and headset mic), |
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* we need to increase the enable_count so that we don't |
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* turn off the shared BCLK while other devices are using |
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* it. |
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*/ |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
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ret = regmap_fields_write(i2sctl->spken, id, |
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LPAIF_I2SCTL_SPKEN_ENABLE); |
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} else { |
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ret = regmap_fields_write(i2sctl->micen, id, |
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LPAIF_I2SCTL_MICEN_ENABLE); |
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} |
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if (ret) |
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dev_err(dai->dev, "error writing to i2sctl reg: %d\n", |
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ret); |
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|
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ret = clk_enable(drvdata->mi2s_bit_clk[id]); |
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if (ret) { |
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dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); |
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clk_disable(drvdata->mi2s_osr_clk[id]); |
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return ret; |
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} |
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break; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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/* |
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* To ensure lpass BCLK/LRCLK is disabled during |
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* device suspend. |
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*/ |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
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ret = regmap_fields_write(i2sctl->spken, id, |
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LPAIF_I2SCTL_SPKEN_DISABLE); |
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} else { |
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ret = regmap_fields_write(i2sctl->micen, id, |
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LPAIF_I2SCTL_MICEN_DISABLE); |
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} |
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if (ret) |
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dev_err(dai->dev, "error writing to i2sctl reg: %d\n", |
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ret); |
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|
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clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]); |
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|
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break; |
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} |
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|
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return ret; |
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} |
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|
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static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); |
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struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; |
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unsigned int id = dai->driver->id; |
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int ret; |
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|
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/* |
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* Ensure lpass BCLK/LRCLK is enabled bit before playback/capture |
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* data flow starts. This allows other codec to have some delay before |
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* the data flow. |
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* (ex: to drop start up pop noise before capture starts). |
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*/ |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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ret = regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_ENABLE); |
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else |
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ret = regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_ENABLE); |
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|
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if (ret) { |
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dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret); |
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return ret; |
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} |
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|
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/* |
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* Check mi2s_was_prepared before enabling BCLK as lpass_cpu_daiops_prepare can |
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* be called multiple times. It's paired with the clk_disable in |
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* lpass_cpu_daiops_shutdown. |
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*/ |
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if (!drvdata->mi2s_was_prepared[dai->driver->id]) { |
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ret = clk_enable(drvdata->mi2s_bit_clk[id]); |
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if (ret) { |
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dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); |
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return ret; |
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} |
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drvdata->mi2s_was_prepared[dai->driver->id] = true; |
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} |
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return 0; |
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} |
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|
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const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = { |
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.set_sysclk = lpass_cpu_daiops_set_sysclk, |
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.startup = lpass_cpu_daiops_startup, |
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.shutdown = lpass_cpu_daiops_shutdown, |
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.hw_params = lpass_cpu_daiops_hw_params, |
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.trigger = lpass_cpu_daiops_trigger, |
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.prepare = lpass_cpu_daiops_prepare, |
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}; |
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EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops); |
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|
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int lpass_cpu_pcm_new(struct snd_soc_pcm_runtime *rtd, |
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struct snd_soc_dai *dai) |
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{ |
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int ret; |
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struct snd_soc_dai_driver *drv = dai->driver; |
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); |
|
|
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if (drvdata->mi2s_playback_sd_mode[dai->id] == LPAIF_I2SCTL_MODE_QUAD01) { |
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ret = snd_pcm_add_chmap_ctls(rtd->pcm, SNDRV_PCM_STREAM_PLAYBACK, |
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lpass_quad_chmaps, drv->playback.channels_max, 0, |
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NULL); |
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if (ret < 0) |
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return ret; |
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} |
|
|
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(lpass_cpu_pcm_new); |
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|
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int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai) |
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{ |
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); |
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int ret; |
|
|
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/* ensure audio hardware is disabled */ |
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ret = regmap_write(drvdata->lpaif_map, |
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LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0); |
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if (ret) |
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dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret); |
|
|
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return ret; |
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} |
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EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe); |
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|
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static int asoc_qcom_of_xlate_dai_name(struct snd_soc_component *component, |
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const struct of_phandle_args *args, |
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const char **dai_name) |
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{ |
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struct lpass_data *drvdata = snd_soc_component_get_drvdata(component); |
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struct lpass_variant *variant = drvdata->variant; |
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int id = args->args[0]; |
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int ret = -EINVAL; |
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int i; |
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|
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for (i = 0; i < variant->num_dai; i++) { |
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if (variant->dai_driver[i].id == id) { |
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*dai_name = variant->dai_driver[i].name; |
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ret = 0; |
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break; |
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} |
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} |
|
|
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return ret; |
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} |
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|
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static const struct snd_soc_component_driver lpass_cpu_comp_driver = { |
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.name = "lpass-cpu", |
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.of_xlate_dai_name = asoc_qcom_of_xlate_dai_name, |
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}; |
|
|
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static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg) |
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{ |
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struct lpass_data *drvdata = dev_get_drvdata(dev); |
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struct lpass_variant *v = drvdata->variant; |
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int i; |
|
|
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for (i = 0; i < v->i2s_ports; ++i) |
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if (reg == LPAIF_I2SCTL_REG(v, i)) |
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return true; |
|
|
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for (i = 0; i < v->irq_ports; ++i) { |
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if (reg == LPAIF_IRQEN_REG(v, i)) |
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return true; |
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if (reg == LPAIF_IRQCLEAR_REG(v, i)) |
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return true; |
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} |
|
|
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for (i = 0; i < v->rdma_channels; ++i) { |
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if (reg == LPAIF_RDMACTL_REG(v, i)) |
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return true; |
|
if (reg == LPAIF_RDMABASE_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_RDMABUFF_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_RDMAPER_REG(v, i)) |
|
return true; |
|
} |
|
|
|
for (i = 0; i < v->wrdma_channels; ++i) { |
|
if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) |
|
return true; |
|
if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) |
|
return true; |
|
if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) |
|
return true; |
|
if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) |
|
return true; |
|
} |
|
|
|
return false; |
|
} |
|
|
|
static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg) |
|
{ |
|
struct lpass_data *drvdata = dev_get_drvdata(dev); |
|
struct lpass_variant *v = drvdata->variant; |
|
int i; |
|
|
|
for (i = 0; i < v->i2s_ports; ++i) |
|
if (reg == LPAIF_I2SCTL_REG(v, i)) |
|
return true; |
|
|
|
for (i = 0; i < v->irq_ports; ++i) { |
|
if (reg == LPAIF_IRQCLEAR_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_IRQEN_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_IRQSTAT_REG(v, i)) |
|
return true; |
|
} |
|
|
|
for (i = 0; i < v->rdma_channels; ++i) { |
|
if (reg == LPAIF_RDMACTL_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_RDMABASE_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_RDMABUFF_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_RDMACURR_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_RDMAPER_REG(v, i)) |
|
return true; |
|
} |
|
|
|
for (i = 0; i < v->wrdma_channels; ++i) { |
|
if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) |
|
return true; |
|
if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) |
|
return true; |
|
if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) |
|
return true; |
|
if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) |
|
return true; |
|
if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) |
|
return true; |
|
} |
|
|
|
return false; |
|
} |
|
|
|
static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg) |
|
{ |
|
struct lpass_data *drvdata = dev_get_drvdata(dev); |
|
struct lpass_variant *v = drvdata->variant; |
|
int i; |
|
|
|
for (i = 0; i < v->irq_ports; ++i) { |
|
if (reg == LPAIF_IRQCLEAR_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_IRQSTAT_REG(v, i)) |
|
return true; |
|
} |
|
|
|
for (i = 0; i < v->rdma_channels; ++i) |
|
if (reg == LPAIF_RDMACURR_REG(v, i)) |
|
return true; |
|
|
|
for (i = 0; i < v->wrdma_channels; ++i) |
|
if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) |
|
return true; |
|
|
|
return false; |
|
} |
|
|
|
static struct regmap_config lpass_cpu_regmap_config = { |
|
.name = "lpass_cpu", |
|
.reg_bits = 32, |
|
.reg_stride = 4, |
|
.val_bits = 32, |
|
.writeable_reg = lpass_cpu_regmap_writeable, |
|
.readable_reg = lpass_cpu_regmap_readable, |
|
.volatile_reg = lpass_cpu_regmap_volatile, |
|
.cache_type = REGCACHE_FLAT, |
|
}; |
|
|
|
static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map) |
|
{ |
|
struct lpass_data *drvdata = dev_get_drvdata(dev); |
|
struct lpass_variant *v = drvdata->variant; |
|
unsigned int i; |
|
struct lpass_hdmi_tx_ctl *tx_ctl; |
|
struct regmap_field *legacy_en; |
|
struct lpass_vbit_ctrl *vbit_ctl; |
|
struct regmap_field *tx_parity; |
|
struct lpass_dp_metadata_ctl *meta_ctl; |
|
struct lpass_sstream_ctl *sstream_ctl; |
|
struct regmap_field *ch_msb; |
|
struct regmap_field *ch_lsb; |
|
struct lpass_hdmitx_dmactl *tx_dmactl; |
|
int rval; |
|
|
|
tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL); |
|
if (!tx_ctl) |
|
return -ENOMEM; |
|
|
|
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset); |
|
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset); |
|
drvdata->tx_ctl = tx_ctl; |
|
|
|
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en); |
|
drvdata->hdmitx_legacy_en = legacy_en; |
|
|
|
vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL); |
|
if (!vbit_ctl) |
|
return -ENOMEM; |
|
|
|
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit); |
|
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream); |
|
drvdata->vbit_ctl = vbit_ctl; |
|
|
|
|
|
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity); |
|
drvdata->hdmitx_parity_calc_en = tx_parity; |
|
|
|
meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL); |
|
if (!meta_ctl) |
|
return -ENOMEM; |
|
|
|
rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7); |
|
if (rval) |
|
return rval; |
|
drvdata->meta_ctl = meta_ctl; |
|
|
|
sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL); |
|
if (!sstream_ctl) |
|
return -ENOMEM; |
|
|
|
rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9); |
|
if (rval) |
|
return rval; |
|
|
|
drvdata->sstream_ctl = sstream_ctl; |
|
|
|
for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) { |
|
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb); |
|
drvdata->hdmitx_ch_msb[i] = ch_msb; |
|
|
|
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb); |
|
drvdata->hdmitx_ch_lsb[i] = ch_lsb; |
|
|
|
tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL); |
|
if (!tx_dmactl) |
|
return -ENOMEM; |
|
|
|
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs); |
|
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr); |
|
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel); |
|
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel); |
|
drvdata->hdmi_tx_dmactl[i] = tx_dmactl; |
|
} |
|
return 0; |
|
} |
|
|
|
static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg) |
|
{ |
|
struct lpass_data *drvdata = dev_get_drvdata(dev); |
|
struct lpass_variant *v = drvdata->variant; |
|
int i; |
|
|
|
if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_DP_ADDR(v)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) |
|
return true; |
|
if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) |
|
return true; |
|
if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v)) |
|
return true; |
|
|
|
for (i = 0; i < v->hdmi_rdma_channels; i++) { |
|
if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) |
|
return true; |
|
} |
|
|
|
for (i = 0; i < v->hdmi_rdma_channels; ++i) { |
|
if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) |
|
return true; |
|
} |
|
return false; |
|
} |
|
|
|
static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg) |
|
{ |
|
struct lpass_data *drvdata = dev_get_drvdata(dev); |
|
struct lpass_variant *v = drvdata->variant; |
|
int i; |
|
|
|
if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) |
|
return true; |
|
|
|
for (i = 0; i < v->hdmi_rdma_channels; i++) { |
|
if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) |
|
return true; |
|
} |
|
|
|
if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_DP_ADDR(v)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) |
|
return true; |
|
if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) |
|
return true; |
|
if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) |
|
return true; |
|
|
|
for (i = 0; i < v->hdmi_rdma_channels; ++i) { |
|
if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) |
|
return true; |
|
} |
|
|
|
return false; |
|
} |
|
|
|
static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg) |
|
{ |
|
struct lpass_data *drvdata = dev_get_drvdata(dev); |
|
struct lpass_variant *v = drvdata->variant; |
|
int i; |
|
|
|
if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) |
|
return true; |
|
if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) |
|
return true; |
|
|
|
for (i = 0; i < v->hdmi_rdma_channels; ++i) { |
|
if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) |
|
return true; |
|
} |
|
return false; |
|
} |
|
|
|
static struct regmap_config lpass_hdmi_regmap_config = { |
|
.name = "lpass_hdmi", |
|
.reg_bits = 32, |
|
.reg_stride = 4, |
|
.val_bits = 32, |
|
.writeable_reg = lpass_hdmi_regmap_writeable, |
|
.readable_reg = lpass_hdmi_regmap_readable, |
|
.volatile_reg = lpass_hdmi_regmap_volatile, |
|
.cache_type = REGCACHE_FLAT, |
|
}; |
|
|
|
static bool __lpass_rxtx_regmap_accessible(struct device *dev, unsigned int reg, bool rw) |
|
{ |
|
struct lpass_data *drvdata = dev_get_drvdata(dev); |
|
struct lpass_variant *v = drvdata->variant; |
|
int i; |
|
|
|
for (i = 0; i < v->rxtx_irq_ports; ++i) { |
|
if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_RXTX_IRQEN_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i)) |
|
return true; |
|
} |
|
|
|
for (i = 0; i < v->rxtx_rdma_channels; ++i) { |
|
if (reg == LPAIF_CDC_RXTX_RDMACTL_REG(v, i, LPASS_CDC_DMA_RX0)) |
|
return true; |
|
if (reg == LPAIF_CDC_RXTX_RDMABASE_REG(v, i, LPASS_CDC_DMA_RX0)) |
|
return true; |
|
if (reg == LPAIF_CDC_RXTX_RDMABUFF_REG(v, i, LPASS_CDC_DMA_RX0)) |
|
return true; |
|
if (rw == LPASS_REG_READ) { |
|
if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0)) |
|
return true; |
|
} |
|
if (reg == LPAIF_CDC_RXTX_RDMAPER_REG(v, i, LPASS_CDC_DMA_RX0)) |
|
return true; |
|
if (reg == LPAIF_CDC_RXTX_RDMA_INTF_REG(v, i, LPASS_CDC_DMA_RX0)) |
|
return true; |
|
} |
|
|
|
for (i = 0; i < v->rxtx_wrdma_channels; ++i) { |
|
if (reg == LPAIF_CDC_RXTX_WRDMACTL_REG(v, i + v->rxtx_wrdma_channel_start, |
|
LPASS_CDC_DMA_TX3)) |
|
return true; |
|
if (reg == LPAIF_CDC_RXTX_WRDMABASE_REG(v, i + v->rxtx_wrdma_channel_start, |
|
LPASS_CDC_DMA_TX3)) |
|
return true; |
|
if (reg == LPAIF_CDC_RXTX_WRDMABUFF_REG(v, i + v->rxtx_wrdma_channel_start, |
|
LPASS_CDC_DMA_TX3)) |
|
return true; |
|
if (rw == LPASS_REG_READ) { |
|
if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i, LPASS_CDC_DMA_RX0)) |
|
return true; |
|
} |
|
if (reg == LPAIF_CDC_RXTX_WRDMAPER_REG(v, i + v->rxtx_wrdma_channel_start, |
|
LPASS_CDC_DMA_TX3)) |
|
return true; |
|
if (reg == LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, i + v->rxtx_wrdma_channel_start, |
|
LPASS_CDC_DMA_TX3)) |
|
return true; |
|
} |
|
return false; |
|
} |
|
|
|
static bool lpass_rxtx_regmap_writeable(struct device *dev, unsigned int reg) |
|
{ |
|
return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_WRITE); |
|
} |
|
|
|
static bool lpass_rxtx_regmap_readable(struct device *dev, unsigned int reg) |
|
{ |
|
return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_READ); |
|
} |
|
|
|
static bool lpass_rxtx_regmap_volatile(struct device *dev, unsigned int reg) |
|
{ |
|
struct lpass_data *drvdata = dev_get_drvdata(dev); |
|
struct lpass_variant *v = drvdata->variant; |
|
int i; |
|
|
|
for (i = 0; i < v->rxtx_irq_ports; ++i) { |
|
if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i)) |
|
return true; |
|
} |
|
|
|
for (i = 0; i < v->rxtx_rdma_channels; ++i) |
|
if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0)) |
|
return true; |
|
|
|
for (i = 0; i < v->rxtx_wrdma_channels; ++i) |
|
if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i + v->rxtx_wrdma_channel_start, |
|
LPASS_CDC_DMA_TX3)) |
|
return true; |
|
|
|
return false; |
|
} |
|
|
|
static bool __lpass_va_regmap_accessible(struct device *dev, unsigned int reg, bool rw) |
|
{ |
|
struct lpass_data *drvdata = dev_get_drvdata(dev); |
|
struct lpass_variant *v = drvdata->variant; |
|
int i; |
|
|
|
for (i = 0; i < v->va_irq_ports; ++i) { |
|
if (reg == LPAIF_VA_IRQCLEAR_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_VA_IRQEN_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_VA_IRQSTAT_REG(v, i)) |
|
return true; |
|
} |
|
|
|
for (i = 0; i < v->va_wrdma_channels; ++i) { |
|
if (reg == LPAIF_CDC_VA_WRDMACTL_REG(v, i + v->va_wrdma_channel_start, |
|
LPASS_CDC_DMA_VA_TX0)) |
|
return true; |
|
if (reg == LPAIF_CDC_VA_WRDMABASE_REG(v, i + v->va_wrdma_channel_start, |
|
LPASS_CDC_DMA_VA_TX0)) |
|
return true; |
|
if (reg == LPAIF_CDC_VA_WRDMABUFF_REG(v, i + v->va_wrdma_channel_start, |
|
LPASS_CDC_DMA_VA_TX0)) |
|
return true; |
|
if (rw == LPASS_REG_READ) { |
|
if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start, |
|
LPASS_CDC_DMA_VA_TX0)) |
|
return true; |
|
} |
|
if (reg == LPAIF_CDC_VA_WRDMAPER_REG(v, i + v->va_wrdma_channel_start, |
|
LPASS_CDC_DMA_VA_TX0)) |
|
return true; |
|
if (reg == LPAIF_CDC_VA_WRDMA_INTF_REG(v, i + v->va_wrdma_channel_start, |
|
LPASS_CDC_DMA_VA_TX0)) |
|
return true; |
|
} |
|
return false; |
|
} |
|
|
|
static bool lpass_va_regmap_writeable(struct device *dev, unsigned int reg) |
|
{ |
|
return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_WRITE); |
|
} |
|
|
|
static bool lpass_va_regmap_readable(struct device *dev, unsigned int reg) |
|
{ |
|
return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_READ); |
|
} |
|
|
|
static bool lpass_va_regmap_volatile(struct device *dev, unsigned int reg) |
|
{ |
|
struct lpass_data *drvdata = dev_get_drvdata(dev); |
|
struct lpass_variant *v = drvdata->variant; |
|
int i; |
|
|
|
for (i = 0; i < v->va_irq_ports; ++i) { |
|
if (reg == LPAIF_VA_IRQCLEAR_REG(v, i)) |
|
return true; |
|
if (reg == LPAIF_VA_IRQSTAT_REG(v, i)) |
|
return true; |
|
} |
|
|
|
for (i = 0; i < v->va_wrdma_channels; ++i) { |
|
if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start, |
|
LPASS_CDC_DMA_VA_TX0)) |
|
return true; |
|
} |
|
|
|
return false; |
|
} |
|
|
|
static struct regmap_config lpass_rxtx_regmap_config = { |
|
.reg_bits = 32, |
|
.reg_stride = 4, |
|
.val_bits = 32, |
|
.writeable_reg = lpass_rxtx_regmap_writeable, |
|
.readable_reg = lpass_rxtx_regmap_readable, |
|
.volatile_reg = lpass_rxtx_regmap_volatile, |
|
.cache_type = REGCACHE_FLAT, |
|
}; |
|
|
|
static struct regmap_config lpass_va_regmap_config = { |
|
.reg_bits = 32, |
|
.reg_stride = 4, |
|
.val_bits = 32, |
|
.writeable_reg = lpass_va_regmap_writeable, |
|
.readable_reg = lpass_va_regmap_readable, |
|
.volatile_reg = lpass_va_regmap_volatile, |
|
.cache_type = REGCACHE_FLAT, |
|
}; |
|
|
|
static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev, |
|
struct device_node *node, |
|
const char *name) |
|
{ |
|
unsigned int lines[LPASS_CPU_MAX_MI2S_LINES]; |
|
unsigned int sd_line_mask = 0; |
|
int num_lines, i; |
|
|
|
num_lines = of_property_read_variable_u32_array(node, name, lines, 0, |
|
LPASS_CPU_MAX_MI2S_LINES); |
|
if (num_lines < 0) |
|
return LPAIF_I2SCTL_MODE_NONE; |
|
|
|
for (i = 0; i < num_lines; i++) |
|
sd_line_mask |= BIT(lines[i]); |
|
|
|
switch (sd_line_mask) { |
|
case LPASS_CPU_I2S_SD0_MASK: |
|
return LPAIF_I2SCTL_MODE_SD0; |
|
case LPASS_CPU_I2S_SD1_MASK: |
|
return LPAIF_I2SCTL_MODE_SD1; |
|
case LPASS_CPU_I2S_SD2_MASK: |
|
return LPAIF_I2SCTL_MODE_SD2; |
|
case LPASS_CPU_I2S_SD3_MASK: |
|
return LPAIF_I2SCTL_MODE_SD3; |
|
case LPASS_CPU_I2S_SD0_1_MASK: |
|
return LPAIF_I2SCTL_MODE_QUAD01; |
|
case LPASS_CPU_I2S_SD2_3_MASK: |
|
return LPAIF_I2SCTL_MODE_QUAD23; |
|
case LPASS_CPU_I2S_SD0_1_2_MASK: |
|
return LPAIF_I2SCTL_MODE_6CH; |
|
case LPASS_CPU_I2S_SD0_1_2_3_MASK: |
|
return LPAIF_I2SCTL_MODE_8CH; |
|
default: |
|
dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask); |
|
return LPAIF_I2SCTL_MODE_NONE; |
|
} |
|
} |
|
|
|
static void of_lpass_cpu_parse_dai_data(struct device *dev, |
|
struct lpass_data *data) |
|
{ |
|
struct device_node *node; |
|
int ret, id; |
|
|
|
/* Allow all channels by default for backwards compatibility */ |
|
for (id = 0; id < data->variant->num_dai; id++) { |
|
data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; |
|
data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; |
|
} |
|
|
|
for_each_child_of_node(dev->of_node, node) { |
|
ret = of_property_read_u32(node, "reg", &id); |
|
if (ret || id < 0) { |
|
dev_err(dev, "valid dai id not found: %d\n", ret); |
|
continue; |
|
} |
|
if (id == LPASS_DP_RX) { |
|
data->hdmi_port_enable = 1; |
|
} else if (is_cdc_dma_port(id)) { |
|
data->codec_dma_enable = 1; |
|
} else { |
|
data->mi2s_playback_sd_mode[id] = |
|
of_lpass_cpu_parse_sd_lines(dev, node, |
|
"qcom,playback-sd-lines"); |
|
data->mi2s_capture_sd_mode[id] = |
|
of_lpass_cpu_parse_sd_lines(dev, node, |
|
"qcom,capture-sd-lines"); |
|
} |
|
} |
|
} |
|
|
|
static int of_lpass_cdc_dma_clks_parse(struct device *dev, |
|
struct lpass_data *data) |
|
{ |
|
data->codec_mem0 = devm_clk_get(dev, "audio_cc_codec_mem0"); |
|
if (IS_ERR(data->codec_mem0)) |
|
return PTR_ERR(data->codec_mem0); |
|
|
|
data->codec_mem1 = devm_clk_get(dev, "audio_cc_codec_mem1"); |
|
if (IS_ERR(data->codec_mem1)) |
|
return PTR_ERR(data->codec_mem1); |
|
|
|
data->codec_mem2 = devm_clk_get(dev, "audio_cc_codec_mem2"); |
|
if (IS_ERR(data->codec_mem2)) |
|
return PTR_ERR(data->codec_mem2); |
|
|
|
data->va_mem0 = devm_clk_get(dev, "aon_cc_va_mem0"); |
|
if (IS_ERR(data->va_mem0)) |
|
return PTR_ERR(data->va_mem0); |
|
|
|
return 0; |
|
} |
|
|
|
int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) |
|
{ |
|
struct lpass_data *drvdata; |
|
struct device_node *dsp_of_node; |
|
struct resource *res; |
|
struct lpass_variant *variant; |
|
struct device *dev = &pdev->dev; |
|
const struct of_device_id *match; |
|
int ret, i, dai_id; |
|
|
|
dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0); |
|
if (dsp_of_node) { |
|
dev_err(dev, "DSP exists and holds audio resources\n"); |
|
return -EBUSY; |
|
} |
|
|
|
drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL); |
|
if (!drvdata) |
|
return -ENOMEM; |
|
platform_set_drvdata(pdev, drvdata); |
|
|
|
match = of_match_device(dev->driver->of_match_table, dev); |
|
if (!match || !match->data) |
|
return -EINVAL; |
|
|
|
drvdata->variant = (struct lpass_variant *)match->data; |
|
variant = drvdata->variant; |
|
|
|
of_lpass_cpu_parse_dai_data(dev, drvdata); |
|
|
|
if (drvdata->codec_dma_enable) { |
|
drvdata->rxtx_lpaif = |
|
devm_platform_ioremap_resource_byname(pdev, "lpass-rxtx-lpaif"); |
|
if (IS_ERR(drvdata->rxtx_lpaif)) |
|
return PTR_ERR(drvdata->rxtx_lpaif); |
|
|
|
drvdata->va_lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-va-lpaif"); |
|
if (IS_ERR(drvdata->va_lpaif)) |
|
return PTR_ERR(drvdata->va_lpaif); |
|
|
|
lpass_rxtx_regmap_config.max_register = LPAIF_CDC_RXTX_WRDMAPER_REG(variant, |
|
variant->rxtx_wrdma_channels + |
|
variant->rxtx_wrdma_channel_start, LPASS_CDC_DMA_TX3); |
|
|
|
drvdata->rxtx_lpaif_map = devm_regmap_init_mmio(dev, drvdata->rxtx_lpaif, |
|
&lpass_rxtx_regmap_config); |
|
if (IS_ERR(drvdata->rxtx_lpaif_map)) |
|
return PTR_ERR(drvdata->rxtx_lpaif_map); |
|
|
|
lpass_va_regmap_config.max_register = LPAIF_CDC_VA_WRDMAPER_REG(variant, |
|
variant->va_wrdma_channels + |
|
variant->va_wrdma_channel_start, LPASS_CDC_DMA_VA_TX0); |
|
|
|
drvdata->va_lpaif_map = devm_regmap_init_mmio(dev, drvdata->va_lpaif, |
|
&lpass_va_regmap_config); |
|
if (IS_ERR(drvdata->va_lpaif_map)) |
|
return PTR_ERR(drvdata->va_lpaif_map); |
|
|
|
ret = of_lpass_cdc_dma_clks_parse(dev, drvdata); |
|
if (ret) { |
|
dev_err(dev, "failed to get cdc dma clocks %d\n", ret); |
|
return ret; |
|
} |
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-rxtx-cdc-dma-lpm"); |
|
drvdata->rxtx_cdc_dma_lpm_buf = res->start; |
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-va-cdc-dma-lpm"); |
|
drvdata->va_cdc_dma_lpm_buf = res->start; |
|
} |
|
|
|
drvdata->lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-lpaif"); |
|
if (IS_ERR(drvdata->lpaif)) |
|
return PTR_ERR(drvdata->lpaif); |
|
|
|
lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant, |
|
variant->wrdma_channels + |
|
variant->wrdma_channel_start); |
|
|
|
drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif, |
|
&lpass_cpu_regmap_config); |
|
if (IS_ERR(drvdata->lpaif_map)) { |
|
dev_err(dev, "error initializing regmap: %ld\n", |
|
PTR_ERR(drvdata->lpaif_map)); |
|
return PTR_ERR(drvdata->lpaif_map); |
|
} |
|
|
|
if (drvdata->hdmi_port_enable) { |
|
drvdata->hdmiif = devm_platform_ioremap_resource_byname(pdev, "lpass-hdmiif"); |
|
if (IS_ERR(drvdata->hdmiif)) |
|
return PTR_ERR(drvdata->hdmiif); |
|
|
|
lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant, |
|
variant->hdmi_rdma_channels - 1); |
|
drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif, |
|
&lpass_hdmi_regmap_config); |
|
if (IS_ERR(drvdata->hdmiif_map)) { |
|
dev_err(dev, "error initializing regmap: %ld\n", |
|
PTR_ERR(drvdata->hdmiif_map)); |
|
return PTR_ERR(drvdata->hdmiif_map); |
|
} |
|
} |
|
|
|
if (variant->init) { |
|
ret = variant->init(pdev); |
|
if (ret) { |
|
dev_err(dev, "error initializing variant: %d\n", ret); |
|
return ret; |
|
} |
|
} |
|
|
|
for (i = 0; i < variant->num_dai; i++) { |
|
dai_id = variant->dai_driver[i].id; |
|
if (dai_id == LPASS_DP_RX || is_cdc_dma_port(dai_id)) |
|
continue; |
|
|
|
drvdata->mi2s_osr_clk[dai_id] = devm_clk_get_optional(dev, |
|
variant->dai_osr_clk_names[i]); |
|
drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev, |
|
variant->dai_bit_clk_names[i]); |
|
if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) { |
|
dev_err(dev, |
|
"error getting %s: %ld\n", |
|
variant->dai_bit_clk_names[i], |
|
PTR_ERR(drvdata->mi2s_bit_clk[dai_id])); |
|
return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]); |
|
} |
|
if (drvdata->mi2s_playback_sd_mode[dai_id] == |
|
LPAIF_I2SCTL_MODE_QUAD01) { |
|
variant->dai_driver[dai_id].playback.channels_min = 4; |
|
variant->dai_driver[dai_id].playback.channels_max = 4; |
|
} |
|
} |
|
|
|
/* Allocation for i2sctl regmap fields */ |
|
drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl), |
|
GFP_KERNEL); |
|
|
|
/* Initialize bitfields for dai I2SCTL register */ |
|
ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl, |
|
drvdata->lpaif_map); |
|
if (ret) { |
|
dev_err(dev, "error init i2sctl field: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
if (drvdata->hdmi_port_enable) { |
|
ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map); |
|
if (ret) { |
|
dev_err(dev, "%s error hdmi init failed\n", __func__); |
|
return ret; |
|
} |
|
} |
|
ret = devm_snd_soc_register_component(dev, |
|
&lpass_cpu_comp_driver, |
|
variant->dai_driver, |
|
variant->num_dai); |
|
if (ret) { |
|
dev_err(dev, "error registering cpu driver: %d\n", ret); |
|
goto err; |
|
} |
|
|
|
ret = asoc_qcom_lpass_platform_register(pdev); |
|
if (ret) { |
|
dev_err(dev, "error registering platform driver: %d\n", ret); |
|
goto err; |
|
} |
|
|
|
err: |
|
return ret; |
|
} |
|
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe); |
|
|
|
int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev) |
|
{ |
|
struct lpass_data *drvdata = platform_get_drvdata(pdev); |
|
|
|
if (drvdata->variant->exit) |
|
drvdata->variant->exit(pdev); |
|
|
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove); |
|
|
|
void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev) |
|
{ |
|
struct lpass_data *drvdata = platform_get_drvdata(pdev); |
|
|
|
if (drvdata->variant->exit) |
|
drvdata->variant->exit(pdev); |
|
|
|
} |
|
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_shutdown); |
|
|
|
MODULE_DESCRIPTION("QTi LPASS CPU Driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|