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340 lines
8.3 KiB
340 lines
8.3 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// ALSA SoC IMX MQS driver |
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// |
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// Copyright (C) 2014-2015 Freescale Semiconductor, Inc. |
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// Copyright 2019 NXP |
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#include <linux/clk.h> |
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#include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/of.h> |
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#include <linux/pm.h> |
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#include <linux/slab.h> |
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#include <sound/soc.h> |
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#include <sound/pcm.h> |
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#include <sound/initval.h> |
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#define REG_MQS_CTRL 0x00 |
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#define MQS_EN_MASK (0x1 << 28) |
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#define MQS_EN_SHIFT (28) |
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#define MQS_SW_RST_MASK (0x1 << 24) |
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#define MQS_SW_RST_SHIFT (24) |
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#define MQS_OVERSAMPLE_MASK (0x1 << 20) |
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#define MQS_OVERSAMPLE_SHIFT (20) |
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#define MQS_CLK_DIV_MASK (0xFF << 0) |
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#define MQS_CLK_DIV_SHIFT (0) |
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/* codec private data */ |
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struct fsl_mqs { |
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struct regmap *regmap; |
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struct clk *mclk; |
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struct clk *ipg; |
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unsigned int reg_iomuxc_gpr2; |
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unsigned int reg_mqs_ctrl; |
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bool use_gpr; |
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}; |
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#define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) |
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#define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE |
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static int fsl_mqs_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_soc_component *component = dai->component; |
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struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); |
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unsigned long mclk_rate; |
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int div, res; |
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int lrclk; |
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mclk_rate = clk_get_rate(mqs_priv->mclk); |
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lrclk = params_rate(params); |
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/* |
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* mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate; |
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* if repeat_rate is 8, mqs can achieve better quality. |
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* oversample rate is fix to 32 currently. |
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*/ |
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div = mclk_rate / (32 * lrclk * 2 * 8); |
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res = mclk_rate % (32 * lrclk * 2 * 8); |
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if (res == 0 && div > 0 && div <= 256) { |
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if (mqs_priv->use_gpr) { |
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regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, |
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IMX6SX_GPR2_MQS_CLK_DIV_MASK, |
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(div - 1) << IMX6SX_GPR2_MQS_CLK_DIV_SHIFT); |
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regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, |
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IMX6SX_GPR2_MQS_OVERSAMPLE_MASK, 0); |
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} else { |
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regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, |
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MQS_CLK_DIV_MASK, |
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(div - 1) << MQS_CLK_DIV_SHIFT); |
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regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, |
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MQS_OVERSAMPLE_MASK, 0); |
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} |
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} else { |
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dev_err(component->dev, "can't get proper divider\n"); |
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} |
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return 0; |
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} |
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static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
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{ |
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/* Only LEFT_J & SLAVE mode is supported. */ |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_LEFT_J: |
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break; |
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default: |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_NB_NF: |
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break; |
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default: |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
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case SND_SOC_DAIFMT_CBC_CFC: |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int fsl_mqs_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_soc_component *component = dai->component; |
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struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); |
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if (mqs_priv->use_gpr) |
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regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, |
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IMX6SX_GPR2_MQS_EN_MASK, |
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1 << IMX6SX_GPR2_MQS_EN_SHIFT); |
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else |
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regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, |
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MQS_EN_MASK, |
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1 << MQS_EN_SHIFT); |
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return 0; |
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} |
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static void fsl_mqs_shutdown(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_soc_component *component = dai->component; |
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struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); |
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if (mqs_priv->use_gpr) |
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regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, |
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IMX6SX_GPR2_MQS_EN_MASK, 0); |
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else |
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regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, |
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MQS_EN_MASK, 0); |
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} |
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static const struct snd_soc_component_driver soc_codec_fsl_mqs = { |
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.idle_bias_on = 1, |
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.non_legacy_dai_naming = 1, |
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}; |
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static const struct snd_soc_dai_ops fsl_mqs_dai_ops = { |
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.startup = fsl_mqs_startup, |
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.shutdown = fsl_mqs_shutdown, |
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.hw_params = fsl_mqs_hw_params, |
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.set_fmt = fsl_mqs_set_dai_fmt, |
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}; |
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static struct snd_soc_dai_driver fsl_mqs_dai = { |
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.name = "fsl-mqs-dai", |
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.playback = { |
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.stream_name = "Playback", |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = FSL_MQS_RATES, |
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.formats = FSL_MQS_FORMATS, |
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}, |
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.ops = &fsl_mqs_dai_ops, |
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}; |
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static const struct regmap_config fsl_mqs_regmap_config = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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.max_register = REG_MQS_CTRL, |
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.cache_type = REGCACHE_NONE, |
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}; |
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static int fsl_mqs_probe(struct platform_device *pdev) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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struct device_node *gpr_np = NULL; |
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struct fsl_mqs *mqs_priv; |
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void __iomem *regs; |
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int ret; |
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mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL); |
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if (!mqs_priv) |
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return -ENOMEM; |
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/* On i.MX6sx the MQS control register is in GPR domain |
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* But in i.MX8QM/i.MX8QXP the control register is moved |
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* to its own domain. |
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*/ |
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if (of_device_is_compatible(np, "fsl,imx8qm-mqs")) |
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mqs_priv->use_gpr = false; |
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else |
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mqs_priv->use_gpr = true; |
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if (mqs_priv->use_gpr) { |
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gpr_np = of_parse_phandle(np, "gpr", 0); |
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if (!gpr_np) { |
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dev_err(&pdev->dev, "failed to get gpr node by phandle\n"); |
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return -EINVAL; |
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} |
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mqs_priv->regmap = syscon_node_to_regmap(gpr_np); |
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if (IS_ERR(mqs_priv->regmap)) { |
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dev_err(&pdev->dev, "failed to get gpr regmap\n"); |
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ret = PTR_ERR(mqs_priv->regmap); |
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goto err_free_gpr_np; |
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} |
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} else { |
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regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(regs)) |
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return PTR_ERR(regs); |
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mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, |
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"core", |
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regs, |
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&fsl_mqs_regmap_config); |
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if (IS_ERR(mqs_priv->regmap)) { |
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dev_err(&pdev->dev, "failed to init regmap: %ld\n", |
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PTR_ERR(mqs_priv->regmap)); |
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return PTR_ERR(mqs_priv->regmap); |
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} |
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mqs_priv->ipg = devm_clk_get(&pdev->dev, "core"); |
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if (IS_ERR(mqs_priv->ipg)) { |
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dev_err(&pdev->dev, "failed to get the clock: %ld\n", |
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PTR_ERR(mqs_priv->ipg)); |
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return PTR_ERR(mqs_priv->ipg); |
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} |
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} |
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mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk"); |
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if (IS_ERR(mqs_priv->mclk)) { |
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dev_err(&pdev->dev, "failed to get the clock: %ld\n", |
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PTR_ERR(mqs_priv->mclk)); |
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ret = PTR_ERR(mqs_priv->mclk); |
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goto err_free_gpr_np; |
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} |
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dev_set_drvdata(&pdev->dev, mqs_priv); |
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pm_runtime_enable(&pdev->dev); |
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ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs, |
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&fsl_mqs_dai, 1); |
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if (ret) |
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goto err_free_gpr_np; |
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return 0; |
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err_free_gpr_np: |
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of_node_put(gpr_np); |
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return ret; |
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} |
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static int fsl_mqs_remove(struct platform_device *pdev) |
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{ |
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pm_runtime_disable(&pdev->dev); |
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return 0; |
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} |
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#ifdef CONFIG_PM |
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static int fsl_mqs_runtime_resume(struct device *dev) |
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{ |
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struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); |
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int ret; |
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ret = clk_prepare_enable(mqs_priv->ipg); |
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if (ret) { |
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dev_err(dev, "failed to enable ipg clock\n"); |
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return ret; |
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} |
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ret = clk_prepare_enable(mqs_priv->mclk); |
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if (ret) { |
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dev_err(dev, "failed to enable mclk clock\n"); |
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clk_disable_unprepare(mqs_priv->ipg); |
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return ret; |
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} |
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if (mqs_priv->use_gpr) |
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regmap_write(mqs_priv->regmap, IOMUXC_GPR2, |
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mqs_priv->reg_iomuxc_gpr2); |
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else |
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regmap_write(mqs_priv->regmap, REG_MQS_CTRL, |
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mqs_priv->reg_mqs_ctrl); |
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return 0; |
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} |
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static int fsl_mqs_runtime_suspend(struct device *dev) |
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{ |
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struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); |
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if (mqs_priv->use_gpr) |
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regmap_read(mqs_priv->regmap, IOMUXC_GPR2, |
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&mqs_priv->reg_iomuxc_gpr2); |
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else |
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regmap_read(mqs_priv->regmap, REG_MQS_CTRL, |
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&mqs_priv->reg_mqs_ctrl); |
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clk_disable_unprepare(mqs_priv->mclk); |
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clk_disable_unprepare(mqs_priv->ipg); |
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return 0; |
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} |
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#endif |
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static const struct dev_pm_ops fsl_mqs_pm_ops = { |
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SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend, |
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fsl_mqs_runtime_resume, |
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NULL) |
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
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pm_runtime_force_resume) |
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}; |
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static const struct of_device_id fsl_mqs_dt_ids[] = { |
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{ .compatible = "fsl,imx8qm-mqs", }, |
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{ .compatible = "fsl,imx6sx-mqs", }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids); |
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static struct platform_driver fsl_mqs_driver = { |
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.probe = fsl_mqs_probe, |
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.remove = fsl_mqs_remove, |
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.driver = { |
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.name = "fsl-mqs", |
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.of_match_table = fsl_mqs_dt_ids, |
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.pm = &fsl_mqs_pm_ops, |
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}, |
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}; |
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module_platform_driver(fsl_mqs_driver); |
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MODULE_AUTHOR("Shengjiu Wang <[email protected]>"); |
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MODULE_DESCRIPTION("MQS codec driver"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_ALIAS("platform:fsl-mqs");
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