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139 lines
3.5 KiB
139 lines
3.5 KiB
/* SPDX-License-Identifier: GPL-2.0+ */ |
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/* |
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* PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and |
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* synchronization devices. |
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* |
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* Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. |
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*/ |
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#ifndef PTP_IDTCLOCKMATRIX_H |
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#define PTP_IDTCLOCKMATRIX_H |
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#include <linux/ktime.h> |
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#include <linux/mfd/idt8a340_reg.h> |
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#include <linux/regmap.h> |
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#define FW_FILENAME "idtcm.bin" |
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#define MAX_TOD (4) |
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#define MAX_PLL (8) |
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#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL) |
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#define TOD_MASK_ADDR (0xFFA5) |
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#define DEFAULT_TOD_MASK (0x04) |
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#define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8)) |
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#define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8)) |
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#define TOD0_PTP_PLL_ADDR (0xFFA8) |
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#define TOD1_PTP_PLL_ADDR (0xFFA9) |
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#define TOD2_PTP_PLL_ADDR (0xFFAA) |
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#define TOD3_PTP_PLL_ADDR (0xFFAB) |
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#define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0) |
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#define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2) |
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#define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4) |
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#define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6) |
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#define DEFAULT_OUTPUT_MASK_PLL0 (0x003) |
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#define DEFAULT_OUTPUT_MASK_PLL1 (0x00c) |
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#define DEFAULT_OUTPUT_MASK_PLL2 (0x030) |
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#define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0) |
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#define DEFAULT_TOD0_PTP_PLL (0) |
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#define DEFAULT_TOD1_PTP_PLL (1) |
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#define DEFAULT_TOD2_PTP_PLL (2) |
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#define DEFAULT_TOD3_PTP_PLL (3) |
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#define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED (150000) |
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#define PHASE_PULL_IN_THRESHOLD_NS (15000) |
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#define TOD_WRITE_OVERHEAD_COUNT_MAX (2) |
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#define TOD_BYTE_COUNT (11) |
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#define LOCK_TIMEOUT_MS (2000) |
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#define LOCK_POLL_INTERVAL_MS (10) |
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#define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef) |
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#define IDTCM_MAX_WRITE_COUNT (512) |
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#define PHASE_PULL_IN_MAX_PPB (144000) |
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#define PHASE_PULL_IN_MIN_THRESHOLD_NS (2) |
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/* |
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* Return register address based on passed in firmware version |
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*/ |
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#define IDTCM_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER)) |
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enum fw_version { |
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V_DEFAULT = 0, |
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V487 = 1, |
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V520 = 2, |
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}; |
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/* PTP PLL Mode */ |
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enum ptp_pll_mode { |
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PTP_PLL_MODE_MIN = 0, |
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PTP_PLL_MODE_WRITE_FREQUENCY = PTP_PLL_MODE_MIN, |
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PTP_PLL_MODE_WRITE_PHASE, |
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PTP_PLL_MODE_UNSUPPORTED, |
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PTP_PLL_MODE_MAX = PTP_PLL_MODE_UNSUPPORTED, |
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}; |
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struct idtcm; |
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struct idtcm_channel { |
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struct ptp_clock_info caps; |
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struct ptp_clock *ptp_clock; |
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struct idtcm *idtcm; |
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u16 dpll_phase; |
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u16 dpll_freq; |
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u16 dpll_n; |
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u16 dpll_ctrl_n; |
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u16 dpll_phase_pull_in; |
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u16 tod_read_primary; |
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u16 tod_write; |
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u16 tod_n; |
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u16 hw_dpll_n; |
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u8 sync_src; |
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enum ptp_pll_mode mode; |
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int (*configure_write_frequency)(struct idtcm_channel *channel); |
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int (*configure_write_phase)(struct idtcm_channel *channel); |
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int (*do_phase_pull_in)(struct idtcm_channel *channel, |
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s32 offset_ns, u32 max_ffo_ppb); |
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s32 current_freq_scaled_ppm; |
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bool phase_pull_in; |
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u32 dco_delay; |
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/* last input trigger for extts */ |
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u8 refn; |
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u8 pll; |
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u16 output_mask; |
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}; |
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struct idtcm { |
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struct idtcm_channel channel[MAX_TOD]; |
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struct device *dev; |
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u8 tod_mask; |
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char version[16]; |
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enum fw_version fw_ver; |
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/* Polls for external time stamps */ |
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u8 extts_mask; |
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struct delayed_work extts_work; |
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/* Remember the ptp channel to report extts */ |
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struct idtcm_channel *event_channel[MAX_TOD]; |
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/* Mutex to protect operations from being interrupted */ |
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struct mutex *lock; |
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struct device *mfd; |
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struct regmap *regmap; |
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/* Overhead calculation for adjtime */ |
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u8 calculate_overhead_flag; |
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s64 tod_write_overhead_ns; |
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ktime_t start_time; |
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}; |
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struct idtcm_fwrc { |
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u8 hiaddr; |
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u8 loaddr; |
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u8 value; |
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u8 reserved; |
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} __packed; |
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#endif /* PTP_IDTCLOCKMATRIX_H */
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